refactor: update assembler tests for ctx→act_id and frame_count renames

Task 7: Update assembler test files for terminology renames

Changes:
- Rename node.ctx to node.act_id in assertions (test_allocate.py)
- Rename system.ctx_slots to system.frame_count in test configs
(test_place.py, test_autoplacement.py, test_allocate.py, and related files)
- Rename FREE_CTX to FREE_FRAME in test node construction
(test_allocate.py, test_codegen.py, test_call_wiring.py)
- Update @system pragma parameter from "ctx" to "frames" (test_lower.py)
Also update default IRAM capacity from 64 to 256 to match new default
- Update test_opcodes.py for shift mnemonic renames and new opcodes:
- "shiftl"/"shiftr"/"ashiftr" → "shl"/"shr"/"asr"
- Add "free_frame" (was "free_ctx")
- Add "extract_tag" and "alloc_remote" (new routing ops)
- Update MONADIC_OPS count from 20 to 22 (added EXTRACT_TAG, ALLOC_REMOTE)
- Update MNEMONIC_TO_OP count from 43 to 45
- Update test names and assertions for free_frame terminology

These changes enable the frame-based activation model where:
- Activations replace contexts for scoping
- Frames replace ctx_slots for concurrent activation tracking
- New routing opcodes (EXTRACT_TAG, ALLOC_REMOTE) are monadic
- Shift opcodes use standardized mnemonics

tests/test_allocate.py

···
         add_node = result.nodes["$main.&add"]
         sub_node = result.nodes["$main.&sub"]
         # Both should have ctx=0 (same function scope)
-        assert add_node.ctx == 0
-        assert sub_node.ctx == 0
+        assert add_node.act_id == 0
+        assert sub_node.act_id == 0
 
     def test_multiple_function_scopes(self):
         """PE with nodes from $main and $helper."""
···
         add_node = result.nodes["$main.&add"]
         helper_node = result.nodes["$helper.&inc"]
         # $main should get ctx=0, $helper should get ctx=1
-        assert add_node.ctx == 0
-        assert helper_node.ctx == 1
+        assert add_node.act_id == 0
+        assert helper_node.act_id == 1
 
     def test_toplevel_nodes(self):
         """Top-level nodes (no function scope) get ctx=0."""
···
         assert len(result.errors) == 0
         add_node = result.nodes["&add"]
         sub_node = result.nodes["&sub"]
-        assert add_node.ctx == 0
-        assert sub_node.ctx == 0
+        assert add_node.act_id == 0
+        assert sub_node.act_id == 0
 
     def test_multiple_functions_order_preserved(self):
         """Context slots assigned in order of first appearance."""
···
         c_node = result.nodes["$helper.&c"]
         d_node = result.nodes["$fib.&d"]
         # First appearance order: $fib (ctx=0), $main (ctx=1), $helper (ctx=2)
-        assert a_node.ctx == 0
-        assert d_node.ctx == 0  # Same function as first
-        assert b_node.ctx == 1
-        assert c_node.ctx == 2
+        assert a_node.act_id == 0
+        assert d_node.act_id == 0  # Same function as first
+        assert b_node.act_id == 1
+        assert c_node.act_id == 2
 
 
 class TestDestinationResolution:
···
                 loc=SourceLoc(5, 1),
             ),
         }
-        system = SystemConfig(pe_count=1, sm_count=1, ctx_slots=4)
+        system = SystemConfig(pe_count=1, sm_count=1, frame_count=4)
         graph = IRGraph(nodes, system=system)
         result = allocate(graph)
 
···
                 loc=SourceLoc(3, 1),
             ),
         }
-        system = SystemConfig(pe_count=1, sm_count=1, ctx_slots=2)
+        system = SystemConfig(pe_count=1, sm_count=1, frame_count=2)
         graph = IRGraph(nodes, system=system)
         result = allocate(graph)
 
···
         add_node = result.nodes["$main.&add"]
         counter_node = result.nodes["$main.#loop_0.&counter"]
         # Both should have ctx=0 (same function scope, macro segment ignored)
-        assert add_node.ctx == 0
-        assert counter_node.ctx == 0
+        assert add_node.act_id == 0
+        assert counter_node.act_id == 0
 
     def test_macro_scope_distinguishes_from_different_functions(self):
         """Macro segments don't prevent distinguishing different functions."""
···
         main_counter = result.nodes["$main.#loop_0.&counter"]
         helper_counter = result.nodes["$helper.#loop_0.&counter"]
         # Different functions get different ctx values
-        assert main_counter.ctx == 0
-        assert helper_counter.ctx == 1
+        assert main_counter.act_id == 0
+        assert helper_counter.act_id == 1
 
     def test_macro_scope_with_root_and_function(self):
         """Macro scope at root and function scope get different ctx slots."""
···
         # $main extracts to "$main" (function scope)
         # First appearance gets ctx=0, next gets ctx=1
         # macro_counter appears first in the PE's node list after IRAM packing
-        assert macro_counter.ctx == 0  # First scope seen
-        assert main_add.ctx == 1  # Second scope seen
+        assert macro_counter.act_id == 0  # First scope seen
+        assert main_add.act_id == 1  # Second scope seen
 
 
 class TestPerCallSiteAllocation:
···
             ),
             "&free_ctx_1": IRNode(
                 name="&free_ctx_1",
-                opcode=RoutingOp.FREE_CTX,
+                opcode=RoutingOp.FREE_FRAME,
                 pe=0,
                 loc=SourceLoc(4, 1),
             ),
             "&free_ctx_2": IRNode(
                 name="&free_ctx_2",
-                opcode=RoutingOp.FREE_CTX,
+                opcode=RoutingOp.FREE_FRAME,
                 pe=0,
                 loc=SourceLoc(5, 1),
             ),
···
 
         # Both trampoline nodes should have ctx values assigned (per-call-site)
         # They should be different
-        assert trampoline_1.ctx is not None
-        assert trampoline_2.ctx is not None
-        assert trampoline_1.ctx != trampoline_2.ctx
+        assert trampoline_1.act_id is not None
+        assert trampoline_2.act_id is not None
+        assert trampoline_1.act_id != trampoline_2.act_id
 
     def test_context_overflow_produces_resource_error(self):
         """Context overflow produces RESOURCE error with per-PE breakdown."""
···
                 loc=SourceLoc(i+1, 1),
             ))
 
-        system = SystemConfig(pe_count=1, sm_count=1, ctx_slots=16)
+        system = SystemConfig(pe_count=1, sm_count=1, frame_count=16)
         graph = IRGraph(nodes, system=system, call_sites=call_sites)
         result = allocate(graph)
 
···
                 loc=SourceLoc(i+1, 1),
             ))
 
-        system = SystemConfig(pe_count=1, sm_count=1, ctx_slots=16)
+        system = SystemConfig(pe_count=1, sm_count=1, frame_count=16)
         graph = IRGraph(nodes, system=system, call_sites=call_sites)
         result = allocate(graph)
 

tests/test_autoplacement.py

···
             "&c": IRNode(name="&c", opcode=ArithOp.INC, pe=None, loc=SourceLoc(3, 1)),
             "&d": IRNode(name="&d", opcode=ArithOp.DEC, pe=None, loc=SourceLoc(4, 1)),
         }
-        system = SystemConfig(pe_count=2, sm_count=1, iram_capacity=64, ctx_slots=4)
+        system = SystemConfig(pe_count=2, sm_count=1, iram_capacity=64, frame_count=4)
         graph = IRGraph(nodes, system=system)
         result = place(graph)
 
···
             "&c1": IRNode(name="&c1", opcode=RoutingOp.CONST, pe=None, const=5, loc=SourceLoc(1, 1)),
             "&c2": IRNode(name="&c2", opcode=RoutingOp.CONST, pe=None, const=10, loc=SourceLoc(2, 1)),
         }
-        system = SystemConfig(pe_count=1, sm_count=1, iram_capacity=64, ctx_slots=4)
+        system = SystemConfig(pe_count=1, sm_count=1, iram_capacity=64, frame_count=4)
         graph = IRGraph(nodes, system=system)
         result = place(graph)
 
···
             "&unplaced1": IRNode(name="&unplaced1", opcode=ArithOp.INC, pe=None, loc=SourceLoc(3, 1)),
             "&unplaced2": IRNode(name="&unplaced2", opcode=ArithOp.DEC, pe=None, loc=SourceLoc(4, 1)),
         }
-        system = SystemConfig(pe_count=2, sm_count=1, iram_capacity=64, ctx_slots=4)
+        system = SystemConfig(pe_count=2, sm_count=1, iram_capacity=64, frame_count=4)
         graph = IRGraph(nodes, system=system)
         result = place(graph)
 
···
             "&a": IRNode(name="&a", opcode=ArithOp.ADD, pe=0, loc=SourceLoc(1, 1)),
             "&b": IRNode(name="&b", opcode=ArithOp.SUB, pe=1, loc=SourceLoc(2, 1)),
         }
-        system = SystemConfig(pe_count=2, sm_count=1, iram_capacity=64, ctx_slots=4)
+        system = SystemConfig(pe_count=2, sm_count=1, iram_capacity=64, frame_count=4)
         graph = IRGraph(nodes, system=system)
         result = place(graph)
 
···
         edges = [
             IREdge(source="&a", dest="&b", port=Port.L, loc=SourceLoc(3, 1)),
         ]
-        system = SystemConfig(pe_count=4, sm_count=1, iram_capacity=64, ctx_slots=4)
+        system = SystemConfig(pe_count=4, sm_count=1, iram_capacity=64, frame_count=4)
         graph = IRGraph(nodes, edges=edges, system=system)
         result = place(graph)
 
···
             IREdge(source="&b", dest="&c", port=Port.L, loc=SourceLoc(5, 1)),
             IREdge(source="&a", dest="&c", port=Port.R, loc=SourceLoc(6, 1)),
         ]
-        system = SystemConfig(pe_count=4, sm_count=1, iram_capacity=64, ctx_slots=4)
+        system = SystemConfig(pe_count=4, sm_count=1, iram_capacity=64, frame_count=4)
         graph = IRGraph(nodes, edges=edges, system=system)
         result = place(graph)
 
···
         edges = [
             IREdge(source="&placed", dest="&unplaced", port=Port.L, loc=SourceLoc(3, 1)),
         ]
-        system = SystemConfig(pe_count=4, sm_count=1, iram_capacity=64, ctx_slots=4)
+        system = SystemConfig(pe_count=4, sm_count=1, iram_capacity=64, frame_count=4)
         graph = IRGraph(nodes, edges=edges, system=system)
         result = place(graph)
 
···
                 loc=SourceLoc(i + 1, 1),
             )
 
-        system = SystemConfig(pe_count=2, sm_count=1, iram_capacity=64, ctx_slots=4)
+        system = SystemConfig(pe_count=2, sm_count=1, iram_capacity=64, frame_count=4)
         graph = IRGraph(nodes, system=system)
         result = place(graph)
 
···
                 loc=SourceLoc(i + 1, 1),
             )
 
-        system = SystemConfig(pe_count=2, sm_count=1, iram_capacity=64, ctx_slots=4)
+        system = SystemConfig(pe_count=2, sm_count=1, iram_capacity=64, frame_count=4)
         graph = IRGraph(nodes, system=system)
         result = place(graph)
 
···
             edges=[],
             regions=[main_region],
             data_defs=[],
-            system=SystemConfig(pe_count=2, sm_count=1, iram_capacity=64, ctx_slots=4),
+            system=SystemConfig(pe_count=2, sm_count=1, iram_capacity=64, frame_count=4),
             errors=[],
         )
 

tests/test_call_wiring.py

···
         if node_name.startswith("$add.__free_ctx_"):
             free_ctx_found = True
             free_ctx = graph.nodes[node_name]
-            assert free_ctx.opcode == RoutingOp.FREE_CTX
+            assert free_ctx.opcode == RoutingOp.FREE_FRAME
             break
     
     assert free_ctx_found, "No free_ctx node found"

tests/test_codegen.py

···
         assert isinstance(token, MonadToken)
         assert token.target == 0
         assert token.offset == 2
-        assert token.ctx == 0
+        assert token.act_id == 0
         assert token.data == 99
         assert token.inline == False
 
···
             elif isinstance(token, IRAMWriteToken):
                 assert isinstance(token.target, int)
                 assert isinstance(token.offset, int)
-                assert isinstance(token.ctx, int)
+                assert isinstance(token.act_id, int)
                 assert isinstance(token.data, int)
                 assert isinstance(token.instructions, tuple)
             elif isinstance(token, MonadToken):
                 assert isinstance(token.target, int)
                 assert isinstance(token.offset, int)
-                assert isinstance(token.ctx, int)
+                assert isinstance(token.act_id, int)
                 assert isinstance(token.data, int)
 
 
···
         assert pass_inst.ctx_mode == 0  # Normal operation
 
     def test_free_ctx_node_normal_codegen(self):
-        """FREE_CTX nodes generate normal ALUInst.
+        """FREE_FRAME nodes generate normal ALUInst.
 
         Tests that:
-        - FREE_CTX (context deallocation) nodes are codegen'd normally
+        - FREE_FRAME (context deallocation) nodes are codegen'd normally
         """
         node_free_ctx = IRNode(
             name="&free_ctx",
-            opcode=RoutingOp.FREE_CTX,
+            opcode=RoutingOp.FREE_FRAME,
             pe=0,
             iram_offset=0,
             ctx=2,  # Call site ctx to free
···
         pe0_config = next(c for c in result.pe_configs if c.pe_id == 0)
         free_inst = pe0_config.iram[0]
 
-        # Verify FREE_CTX node produces normal ALUInst
+        # Verify FREE_FRAME node produces normal ALUInst
         assert isinstance(free_inst, ALUInst)
-        assert free_inst.op == RoutingOp.FREE_CTX
+        assert free_inst.op == RoutingOp.FREE_FRAME
         assert free_inst.ctx_mode == 0  # Normal operation
 
     def test_packed_const_bit_layout(self):

tests/test_integration.py

···
             env,
             [
                 PEConfig(
-                    pe_id=0, iram={}, ctx_slots=8, gen_counters=[1, 2, 3, 4, 5, 6, 7, 8]
+                    pe_id=0, iram={}, frame_count=8, gen_counters=[1, 2, 3, 4, 5, 6, 7, 8]
                 )
             ],
             [],

tests/test_lower.py

···
         assert graph.system is not None
         assert graph.system.pe_count == 4
         assert graph.system.sm_count == 1
-        assert graph.system.iram_capacity == 64  # default
-        assert graph.system.ctx_slots == 4  # default
+        assert graph.system.iram_capacity == 256  # default
+        assert graph.system.frame_count == 8  # default
 
     def test_system_pragma_full(self, parser):
         """Parse full system pragma."""
         graph = parse_and_lower(parser, """\
-            @system pe=2, sm=1, iram=128, ctx=2
+            @system pe=2, sm=1, iram=128, frames=2
         """)
 
         assert graph.system.pe_count == 2
         assert graph.system.sm_count == 1
         assert graph.system.iram_capacity == 128
-        assert graph.system.ctx_slots == 2
+        assert graph.system.frame_count == 2
 
     def test_system_pragma_hex_values(self, parser):
         """Parse system pragma with hexadecimal values."""

tests/test_opcodes.py

···
         assert MNEMONIC_TO_OP["sub"] == ArithOp.SUB
         assert MNEMONIC_TO_OP["inc"] == ArithOp.INC
         assert MNEMONIC_TO_OP["dec"] == ArithOp.DEC
-        assert MNEMONIC_TO_OP["shiftl"] == ArithOp.SHIFT_L
-        assert MNEMONIC_TO_OP["shiftr"] == ArithOp.SHIFT_R
-        assert MNEMONIC_TO_OP["ashiftr"] == ArithOp.ASHFT_R
+        assert MNEMONIC_TO_OP["shl"] == ArithOp.SHL
+        assert MNEMONIC_TO_OP["shr"] == ArithOp.SHR
+        assert MNEMONIC_TO_OP["asr"] == ArithOp.ASR
 
     def test_logic_opcodes(self):
         """or1-asm.AC1.1: Logic opcodes map correctly."""
···
         assert MNEMONIC_TO_OP["merge"] == RoutingOp.MRGE
         assert MNEMONIC_TO_OP["pass"] == RoutingOp.PASS
         assert MNEMONIC_TO_OP["const"] == RoutingOp.CONST
-        assert MNEMONIC_TO_OP["free_ctx"] == RoutingOp.FREE_CTX
+        assert MNEMONIC_TO_OP["free_frame"] == RoutingOp.FREE_FRAME
 
     def test_memory_opcodes(self):
         """or1-asm.AC1.2: Memory opcodes map correctly."""
···
 
     def test_mnemonic_to_op_count(self):
         """Verify all expected mnemonics are present."""
-        # Total: 7 arithmetic + 9 logic + 4 branch + 4 switch + 6 control + 13 memory = 43
+        # Total: 7 arithmetic + 9 logic + 4 branch + 4 switch + 8 control + 13 memory = 45
         # (CfgOp removed: -2 load_inst, route_set; new MemOps added: +5 exec, raw_read, set_page, write_imm, ext)
-        expected_count = 43
+        # (new RoutingOps added: +2 extract_tag, alloc_remote)
+        expected_count = 45
         assert len(MNEMONIC_TO_OP) == expected_count
 
 
···
         "mnemonic",
         [
             # Arithmetic
-            "add", "sub", "inc", "dec", "shiftl", "shiftr", "ashiftr",
+            "add", "sub", "inc", "dec", "shl", "shr", "asr",
             # Logic
             "and", "or", "xor", "not", "eq", "lt", "lte", "gt", "gte",
             # Branch
···
             # Switch
             "sweq", "swgt", "swge", "swof",
             # Control
-            "gate", "sel", "merge", "pass", "const", "free_ctx",
+            "gate", "sel", "merge", "pass", "const", "free_frame", "extract_tag", "alloc_remote",
             # Memory
             "read", "write", "clear", "alloc", "free", "rd_inc", "rd_dec", "cmp_sw",
             "exec", "raw_read", "set_page", "write_imm", "ext",
···
         "mnemonic",
         [
             # Arithmetic
-            "add", "sub", "inc", "dec", "shiftl", "shiftr", "ashiftr",
+            "add", "sub", "inc", "dec", "shl", "shr", "asr",
             # Logic
             "and", "or", "xor", "not", "eq", "lt", "lte", "gt", "gte",
             # Branch
···
             # Switch
             "sweq", "swgt", "swge", "swof",
             # Control
-            "gate", "sel", "merge", "pass", "const", "free_ctx",
+            "gate", "sel", "merge", "pass", "const", "free_frame", "extract_tag", "alloc_remote",
             # Memory
             "read", "write", "clear", "alloc", "free", "rd_inc", "rd_dec", "cmp_sw",
             "exec", "raw_read", "set_page", "write_imm", "ext",
···
     """Verify MONADIC_OPS contains exactly the right opcodes."""
 
     def test_monadic_ops_size(self):
-        """MONADIC_OPS should have exactly 20 opcodes (collision-free).
+        """MONADIC_OPS should have exactly 22 opcodes (collision-free).
 
         Without collision-free implementation, this would be lower due to IntEnum
         collisions (e.g., ArithOp.INC colliding with some MemOp value).
-        Count: 5 arithmetic + 1 logic + 3 routing + 5 old memory + 5 new memory = 20
+        Count: 5 arithmetic + 1 logic + 5 routing + 5 old memory + 5 new memory + 1 WRITE_IMM = 22
+        (Added: EXTRACT_TAG, ALLOC_REMOTE, WRITE_IMM, FREE_FRAME as monadic routing ops)
         """
-        assert len(MONADIC_OPS) == 20
+        assert len(MONADIC_OPS) == 22
 
     def test_monadic_opcodes_present(self):
         """All known monadic opcodes should be in the set."""
         monadic_list = [
             # Arithmetic (single input + const)
             ArithOp.INC, ArithOp.DEC,
-            ArithOp.SHIFT_L, ArithOp.SHIFT_R, ArithOp.ASHFT_R,
+            ArithOp.SHL, ArithOp.SHR, ArithOp.ASR,
             # Logic
             LogicOp.NOT,
             # Routing
-            RoutingOp.PASS, RoutingOp.CONST, RoutingOp.FREE_CTX,
+            RoutingOp.PASS, RoutingOp.CONST, RoutingOp.FREE_FRAME,
+            RoutingOp.EXTRACT_TAG, RoutingOp.ALLOC_REMOTE,
             # Memory
             MemOp.READ, MemOp.ALLOC, MemOp.FREE, MemOp.CLEAR,
-            MemOp.RD_INC, MemOp.RD_DEC,
+            MemOp.RD_INC, MemOp.RD_DEC, MemOp.WRITE_IMM,
         ]
         for op in monadic_list:
             assert op in MONADIC_OPS, f"{op} should be in MONADIC_OPS"
···
         "op",
         [
             ArithOp.INC, ArithOp.DEC,
-            ArithOp.SHIFT_L, ArithOp.SHIFT_R, ArithOp.ASHFT_R,
+            ArithOp.SHL, ArithOp.SHR, ArithOp.ASR,
             LogicOp.NOT,
-            RoutingOp.PASS, RoutingOp.CONST, RoutingOp.FREE_CTX,
+            RoutingOp.PASS, RoutingOp.CONST, RoutingOp.FREE_FRAME,
+            RoutingOp.EXTRACT_TAG, RoutingOp.ALLOC_REMOTE,
             MemOp.READ, MemOp.ALLOC, MemOp.FREE, MemOp.CLEAR,
             MemOp.RD_INC, MemOp.RD_DEC,
             MemOp.EXEC, MemOp.RAW_READ, MemOp.SET_PAGE, MemOp.WRITE_IMM, MemOp.EXT,
···
         "op",
         [
             ArithOp.INC, ArithOp.DEC,
-            ArithOp.SHIFT_L, ArithOp.SHIFT_R, ArithOp.ASHFT_R,
+            ArithOp.SHL, ArithOp.SHR, ArithOp.ASR,
             LogicOp.NOT,
-            RoutingOp.PASS, RoutingOp.CONST, RoutingOp.FREE_CTX,
+            RoutingOp.PASS, RoutingOp.CONST, RoutingOp.FREE_FRAME,
+            RoutingOp.EXTRACT_TAG, RoutingOp.ALLOC_REMOTE,
             MemOp.READ, MemOp.ALLOC, MemOp.FREE, MemOp.CLEAR,
             MemOp.RD_INC, MemOp.RD_DEC,
             MemOp.EXEC, MemOp.RAW_READ, MemOp.SET_PAGE, MemOp.WRITE_IMM, MemOp.EXT,
···
 class TestFreeDisambiguation:
     """Verify free_ctx (ALU) and free (SM) are distinct and round-trip correctly."""
 
-    def test_free_ctx_is_routing_op(self):
-        """The free_ctx mnemonic should map to ALU RoutingOp.FREE_CTX."""
-        assert MNEMONIC_TO_OP["free_ctx"] == RoutingOp.FREE_CTX
+    def test_free_frame_is_routing_op(self):
+        """The free_frame mnemonic should map to ALU RoutingOp.FREE_FRAME."""
+        assert MNEMONIC_TO_OP["free_frame"] == RoutingOp.FREE_FRAME
 
     def test_free_is_memop(self):
         """The free mnemonic should map to SM MemOp.FREE."""
         assert MNEMONIC_TO_OP["free"] == MemOp.FREE
 
     def test_both_free_round_trip(self):
-        """Both free_ctx and free should round-trip correctly."""
-        # free_ctx -> RoutingOp.FREE_CTX -> free_ctx
-        assert OP_TO_MNEMONIC[RoutingOp.FREE_CTX] == "free_ctx"
+        """Both free_frame and free should round-trip correctly."""
+        # free_frame -> RoutingOp.FREE_FRAME -> free_frame
+        assert OP_TO_MNEMONIC[RoutingOp.FREE_FRAME] == "free_frame"
         assert OP_TO_MNEMONIC[MemOp.FREE] == "free"
 
     def test_no_collision(self):
         """Distinct enum types should not collide in reverse mapping."""
-        # RoutingOp.FREE_CTX and MemOp.FREE are different enum values
-        assert RoutingOp.FREE_CTX != MemOp.FREE
+        # RoutingOp.FREE_FRAME and MemOp.FREE are different enum values
+        assert RoutingOp.FREE_FRAME != MemOp.FREE

tests/test_pe.py

···
     def test_first_dyadic_stores_in_matching(self, token: DyadToken):
         """AC1.2: First dyadic token stores in matching store, no output."""
         env = simpy.Environment()
-        pe = ProcessingElement(env, 0, {}, ctx_slots=4, offsets=64)
+        pe = ProcessingElement(env, 0, {}, frame_count=4, offsets=64)
 
         # Inject first token directly to matching
         ctx_idx = token.ctx % 4
···
     def test_stale_token_discarded(self, token: DyadToken):
         """AC1.4: Stale token (gen mismatch) is discarded, store unchanged."""
         env = simpy.Environment()
-        pe = ProcessingElement(env, 0, {}, ctx_slots=4, offsets=64)
+        pe = ProcessingElement(env, 0, {}, frame_count=4, offsets=64)
 
         # Set gen counter to different value
         ctx_idx = token.ctx % 4

tests/test_pe_events.py

···
             const=packed_const,
             ctx_mode=1,
         )}
-        pe = ProcessingElement(env, 0, iram, ctx_slots=4, on_event=on_event)
+        pe = ProcessingElement(env, 0, iram, frame_count=4, on_event=on_event)
         pe.route_table[0] = simpy.Store(env)
         pe.gen_counters[target_ctx] = 5
 

tests/test_place.py

···
             "&inc": IRNode(name="&inc", opcode=ArithOp.INC, pe=2, loc=SourceLoc(3, 1)),
             "&dec": IRNode(name="&dec", opcode=ArithOp.DEC, pe=3, loc=SourceLoc(4, 1)),
         }
-        system = SystemConfig(pe_count=4, sm_count=1, iram_capacity=64, ctx_slots=4)
+        system = SystemConfig(pe_count=4, sm_count=1, iram_capacity=64, frame_count=4)
         graph = IRGraph(nodes, system=system)
         result = place(graph)
 
···
             pe=9,
             loc=SourceLoc(5, 10),
         )
-        system = SystemConfig(pe_count=4, sm_count=1, iram_capacity=64, ctx_slots=4)
+        system = SystemConfig(pe_count=4, sm_count=1, iram_capacity=64, frame_count=4)
         graph = IRGraph({"&add": node}, system=system)
         result = place(graph)
 
···
             pe=1,
             loc=SourceLoc(1, 1),
         )
-        system = SystemConfig(pe_count=1, sm_count=1, iram_capacity=64, ctx_slots=4)
+        system = SystemConfig(pe_count=1, sm_count=1, iram_capacity=64, frame_count=4)
         graph = IRGraph({"&add": node}, system=system)
         result = place(graph)
 
···
             "&sub": IRNode(name="&sub", opcode=ArithOp.SUB, pe=5, loc=SourceLoc(2, 1)),
             "&inc": IRNode(name="&inc", opcode=ArithOp.INC, pe=1, loc=SourceLoc(3, 1)),
         }
-        system = SystemConfig(pe_count=4, sm_count=1, iram_capacity=64, ctx_slots=4)
+        system = SystemConfig(pe_count=4, sm_count=1, iram_capacity=64, frame_count=4)
         graph = IRGraph(nodes, system=system)
         result = place(graph)
 
···
             "&sub": IRNode(name="&sub", opcode=ArithOp.SUB, pe=None, loc=SourceLoc(2, 1)),
             "&inc": IRNode(name="&inc", opcode=ArithOp.INC, pe=None, loc=SourceLoc(3, 1)),
         }
-        system = SystemConfig(pe_count=2, sm_count=1, iram_capacity=64, ctx_slots=4)
+        system = SystemConfig(pe_count=2, sm_count=1, iram_capacity=64, frame_count=4)
         graph = IRGraph(nodes, system=system)
         result = place(graph)
 
···
             "&sub": IRNode(name="&sub", opcode=ArithOp.SUB, pe=None, loc=SourceLoc(2, 1)),
             "&inc": IRNode(name="&inc", opcode=ArithOp.INC, pe=9, loc=SourceLoc(3, 1)),
         }
-        system = SystemConfig(pe_count=4, sm_count=1, iram_capacity=64, ctx_slots=4)
+        system = SystemConfig(pe_count=4, sm_count=1, iram_capacity=64, frame_count=4)
         graph = IRGraph(nodes, system=system)
         result = place(graph)
 

tests/test_snapshot.py

···
         env = simpy.Environment()
 
         iram = {0: ALUInst(ArithOp.ADD, Addr(0, Port.L, 0), Addr(0, Port.R, 0), None)}
-        pe_configs = [PEConfig(pe_id=0, iram=iram, ctx_slots=4, offsets=64)]
+        pe_configs = [PEConfig(pe_id=0, iram=iram, frame_count=4, offsets=64)]
         sm_configs = []
 
         system = build_topology(env, pe_configs, sm_configs)