"Das U-Boot" Source Tree

clk: mediatek: add clock driver support for MediaTek MT7987 SoC

This patch adds clock driver support for MediaTek MT7987 SoC

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

authored by

Weijie Gao and committed by
Tom Rini
ece4e580 a416d9e6

+1055
+1
drivers/clk/mediatek/Makefile
··· 10 10 obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o 11 11 obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o 12 12 obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o 13 + obj-$(CONFIG_TARGET_MT7987) += clk-mt7987.o 13 14 obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o 14 15 obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o 15 16 obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
+848
drivers/clk/mediatek/clk-mt7987.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * MediaTek clock driver for MT7987 SoC 4 + * 5 + * Copyright (C) 2024 MediaTek Inc. 6 + * Author: Sam Shih <sam.shih@mediatek.com> 7 + */ 8 + 9 + #include <dm.h> 10 + #include <log.h> 11 + #include <asm/arch-mediatek/reset.h> 12 + #include <asm/io.h> 13 + #include <dt-bindings/clock/mediatek,mt7987-clk.h> 14 + #include <linux/bitops.h> 15 + 16 + #include "clk-mtk.h" 17 + 18 + #define MT7987_XTAL_RATE (40 * MHZ) 19 + #define MT7987_CLK_PDN 0x250 20 + #define MT7987_CLK_PDN_EN_WRITE BIT(31) 21 + 22 + #define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ 23 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) 24 + 25 + #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ 26 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) 27 + 28 + #define TOP_FACTOR(_id, _name, _parent, _mult, _div) \ 29 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) 30 + 31 + #define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \ 32 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS) 33 + 34 + /* FIXED PLLS */ 35 + static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = { 36 + FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000), 37 + FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000), 38 + FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), 39 + FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000), 40 + FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), 41 + FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000), 42 + FIXED_CLK(CLK_APMIXED_ARM_LL, CLK_XTAL, 2000000000), 43 + FIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 384000000), 44 + }; 45 + 46 + static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = { 47 + .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), 48 + .fclks = apmixedsys_mtk_plls, 49 + .flags = CLK_APMIXED, 50 + .xtal_rate = 40 * MHZ, 51 + }; 52 + 53 + static const struct udevice_id mt7987_fixed_pll_compat[] = { 54 + { .compatible = "mediatek,mt7987-fixed-plls" }, 55 + { .compatible = "mediatek,mt7987-apmixedsys" }, 56 + {} 57 + }; 58 + 59 + static int mt7987_fixed_pll_probe(struct udevice *dev) 60 + { 61 + return mtk_common_clk_init(dev, &mt7987_fixed_pll_clk_tree); 62 + } 63 + 64 + U_BOOT_DRIVER(mtk_clk_apmixedsys) = { 65 + .name = "mt7987-clock-fixed-pll", 66 + .id = UCLASS_CLK, 67 + .of_match = mt7987_fixed_pll_compat, 68 + .probe = mt7987_fixed_pll_probe, 69 + .priv_auto = sizeof(struct mtk_clk_priv), 70 + .ops = &mtk_clk_topckgen_ops, 71 + .flags = DM_FLAG_PRE_RELOC, 72 + }; 73 + 74 + /* TOPCKGEN FIXED DIV */ 75 + static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = { 76 + PLL_FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", CLK_APMIXED_MPLL, 1, 2), 77 + PLL_FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", CLK_APMIXED_MPLL, 1, 3), 78 + PLL_FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", CLK_APMIXED_MPLL, 1, 6), 79 + PLL_FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", CLK_APMIXED_MPLL, 1, 4), 80 + PLL_FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", CLK_APMIXED_MPLL, 1, 8), 81 + PLL_FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", CLK_APMIXED_MPLL, 1, 16), 82 + PLL_FACTOR(CLK_TOP_CB_APLL2_D4, "cb_apll2_d4", CLK_APMIXED_APLL2, 1, 4), 83 + PLL_FACTOR(CLK_TOP_CB_NET1_D3, "cb_net1_d3", CLK_APMIXED_NET1PLL, 1, 3), 84 + PLL_FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", CLK_APMIXED_NET1PLL, 1, 4), 85 + PLL_FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", CLK_APMIXED_NET1PLL, 1, 5), 86 + PLL_FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", CLK_APMIXED_NET1PLL, 1, 10), 87 + PLL_FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", CLK_APMIXED_NET1PLL, 1, 20), 88 + PLL_FACTOR(CLK_TOP_CB_NET1_D7, "cb_net1_d7", CLK_APMIXED_NET1PLL, 1, 7), 89 + PLL_FACTOR(CLK_TOP_NET1_D7_D2, "net1_d7_d2", CLK_APMIXED_NET1PLL, 1, 14), 90 + PLL_FACTOR(CLK_TOP_NET1_D7_D4, "net1_d7_d4", CLK_APMIXED_NET1PLL, 1, 28), 91 + PLL_FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", CLK_APMIXED_NET1PLL, 1, 16), 92 + PLL_FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", CLK_APMIXED_NET1PLL, 1, 32), 93 + PLL_FACTOR(CLK_TOP_NET1_D8_D8, "net1_d8_d8", CLK_APMIXED_NET1PLL, 1, 64), 94 + PLL_FACTOR(CLK_TOP_NET1_D8_D16, "net1_d8_d16", CLK_APMIXED_NET1PLL, 1, 128), 95 + PLL_FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", CLK_APMIXED_NET2PLL, 1, 2), 96 + PLL_FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", CLK_APMIXED_NET2PLL, 1, 4), 97 + PLL_FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", CLK_APMIXED_NET2PLL, 1, 16), 98 + PLL_FACTOR(CLK_TOP_NET2_D4_D8, "net2_d4_d8", CLK_APMIXED_NET2PLL, 1, 32), 99 + PLL_FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", CLK_APMIXED_NET2PLL, 1, 6), 100 + PLL_FACTOR(CLK_TOP_NET2_D7_D2, "net2_d7_d2", CLK_APMIXED_NET2PLL, 1, 14), 101 + PLL_FACTOR(CLK_TOP_CB_NET2_D8, "cb_net2_d8", CLK_APMIXED_NET2PLL, 1, 8), 102 + PLL_FACTOR(CLK_TOP_MSDC_D2, "msdc_d2", CLK_APMIXED_MSDCPLL, 1, 2), 103 + XTAL_FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1), 104 + TOP_FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CLK_TOP_CB_CKSQ_40M, 1, 2), 105 + TOP_FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", CLK_TOP_CB_CKSQ_40M, 1, 1250), 106 + TOP_FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CLK_TOP_CB_CKSQ_40M, 1, 1221), 107 + }; 108 + 109 + /* TOPCKGEN MUX PARENTS */ 110 + #define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) 111 + #define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) 112 + 113 + /* CLK_TOP_NETSYS_SEL (netsys_sel) in topckgen */ 114 + static const struct mtk_parent netsys_parents[] = { 115 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 116 + TOP_PARENT(CLK_TOP_CB_NET2_D2) 117 + }; 118 + 119 + /* CLK_TOP_NETSYS_500M_SEL (netsys_500m_sel) in topckgen */ 120 + static const struct mtk_parent netsys_500m_parents[] = { 121 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 122 + TOP_PARENT(CLK_TOP_CB_NET1_D5), 123 + TOP_PARENT(CLK_TOP_NET1_D5_D2) 124 + }; 125 + 126 + /* CLK_TOP_NETSYS_2X_SEL (netsys_2x_sel) in topckgen */ 127 + static const struct mtk_parent netsys_2x_parents[] = { 128 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 129 + APMIXED_PARENT(CLK_APMIXED_NET2PLL) 130 + }; 131 + 132 + /* CLK_TOP_ETH_GMII_SEL (eth_gmii_sel) in topckgen */ 133 + static const struct mtk_parent eth_gmii_parents[] = { 134 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 135 + TOP_PARENT(CLK_TOP_NET1_D5_D4) 136 + }; 137 + 138 + /* CLK_TOP_EIP_SEL (eip_sel) in topckgen */ 139 + static const struct mtk_parent eip_parents[] = { 140 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 141 + TOP_PARENT(CLK_TOP_CB_NET1_D3), 142 + APMIXED_PARENT(CLK_APMIXED_NET2PLL), 143 + TOP_PARENT(CLK_TOP_CB_NET1_D4), 144 + TOP_PARENT(CLK_TOP_CB_NET1_D5) 145 + }; 146 + 147 + /* CLK_TOP_AXI_INFRA_SEL (axi_infra_sel) in topckgen */ 148 + static const struct mtk_parent axi_infra_parents[] = { 149 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 150 + TOP_PARENT(CLK_TOP_NET1_D8_D2) 151 + }; 152 + 153 + /* CLK_TOP_UART_SEL (uart_sel) in topckgen */ 154 + static const struct mtk_parent uart_parents[] = { 155 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 156 + TOP_PARENT(CLK_TOP_CB_M_D8), 157 + TOP_PARENT(CLK_TOP_M_D8_D2) 158 + }; 159 + 160 + /* CLK_TOP_EMMC_250M_SEL (emmc_250m_sel) in topckgen */ 161 + static const struct mtk_parent emmc_250m_parents[] = { 162 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 163 + TOP_PARENT(CLK_TOP_NET1_D5_D2), 164 + TOP_PARENT(CLK_TOP_NET1_D7_D2) 165 + }; 166 + 167 + /* CLK_TOP_EMMC_400M_SEL (emmc_400m_sel) in topckgen */ 168 + static const struct mtk_parent emmc_400m_parents[] = { 169 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 170 + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), 171 + TOP_PARENT(CLK_TOP_CB_NET1_D7), 172 + TOP_PARENT(CLK_TOP_CB_M_D2), 173 + TOP_PARENT(CLK_TOP_NET1_D7_D2), 174 + TOP_PARENT(CLK_TOP_CB_NET2_D6) 175 + }; 176 + 177 + /* CLK_TOP_SPI_SEL (spi_sel) in topckgen */ 178 + static const struct mtk_parent spi_parents[] = { 179 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 180 + TOP_PARENT(CLK_TOP_CB_M_D2), 181 + TOP_PARENT(CLK_TOP_NET1_D7_D2), 182 + TOP_PARENT(CLK_TOP_NET1_D8_D2), 183 + TOP_PARENT(CLK_TOP_CB_NET2_D6), 184 + TOP_PARENT(CLK_TOP_NET1_D5_D4), 185 + TOP_PARENT(CLK_TOP_CB_M_D4), 186 + TOP_PARENT(CLK_TOP_NET1_D8_D4) 187 + }; 188 + 189 + /* CLK_TOP_NFI_SEL (nfi_sel) in topckgen */ 190 + static const struct mtk_parent nfi_parents[] = { 191 + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), 192 + TOP_PARENT(CLK_TOP_NET1_D8_D2), 193 + TOP_PARENT(CLK_TOP_CB_M_D3), 194 + TOP_PARENT(CLK_TOP_NET1_D5_D4), 195 + TOP_PARENT(CLK_TOP_CB_M_D4), 196 + TOP_PARENT(CLK_TOP_NET1_D7_D4), 197 + TOP_PARENT(CLK_TOP_NET1_D8_D4), 198 + TOP_PARENT(CLK_TOP_M_D3_D2), 199 + TOP_PARENT(CLK_TOP_NET2_D7_D2), 200 + TOP_PARENT(CLK_TOP_CB_M_D8) 201 + }; 202 + 203 + /* CLK_TOP_PWM_SEL (pwm_sel) in topckgen */ 204 + static const struct mtk_parent pwm_parents[] = { 205 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 206 + TOP_PARENT(CLK_TOP_NET1_D8_D2), 207 + TOP_PARENT(CLK_TOP_NET1_D5_D4), 208 + TOP_PARENT(CLK_TOP_CB_M_D4), 209 + TOP_PARENT(CLK_TOP_M_D8_D2), 210 + TOP_PARENT(CLK_TOP_CB_RTC_32K) 211 + }; 212 + 213 + /* CLK_TOP_I2C_SEL (i2c_sel) in topckgen */ 214 + static const struct mtk_parent i2c_parents[] = { 215 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 216 + TOP_PARENT(CLK_TOP_NET1_D5_D4), 217 + TOP_PARENT(CLK_TOP_CB_M_D4), 218 + TOP_PARENT(CLK_TOP_NET1_D8_D4) 219 + }; 220 + 221 + /* CLK_TOP_PCIE_MBIST_250M_SEL (pcie_mbist_250m_sel) in topckgen */ 222 + static const struct mtk_parent pcie_mbist_250m_parents[] = { 223 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 224 + TOP_PARENT(CLK_TOP_NET1_D5_D2) 225 + }; 226 + 227 + /* CLK_TOP_PEXTP_TL_SEL (pextp_tl_ck_sel) in topckgen */ 228 + static const struct mtk_parent pextp_tl_ck_parents[] = { 229 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 230 + TOP_PARENT(CLK_TOP_CB_NET2_D6), 231 + TOP_PARENT(CLK_TOP_NET1_D7_D4), 232 + TOP_PARENT(CLK_TOP_M_D8_D2), 233 + TOP_PARENT(CLK_TOP_CB_RTC_32K) 234 + }; 235 + 236 + /* CLK_TOP_AUD_SEL (aud_sel) in topckgen */ 237 + static const struct mtk_parent aud_parents[] = { 238 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 239 + APMIXED_PARENT(CLK_APMIXED_APLL2) 240 + }; 241 + 242 + /* CLK_TOP_A1SYS_SEL (a1sys_sel) in topckgen */ 243 + static const struct mtk_parent a1sys_parents[] = { 244 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 245 + TOP_PARENT(CLK_TOP_CB_APLL2_D4) 246 + }; 247 + 248 + /* CLK_TOP_AUD_L_SEL (aud_l_sel) in topckgen */ 249 + static const struct mtk_parent aud_l_parents[] = { 250 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 251 + APMIXED_PARENT(CLK_APMIXED_APLL2), 252 + TOP_PARENT(CLK_TOP_M_D8_D2) 253 + }; 254 + 255 + /* CLK_TOP_USB_PHY_SEL (usb_phy_sel) in topckgen */ 256 + static const struct mtk_parent usb_phy_parents[] = { 257 + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), 258 + TOP_PARENT(CLK_TOP_M_D8_D2) 259 + }; 260 + 261 + /* CLK_TOP_SGM_0_SEL (sgm_0_sel) in topckgen */ 262 + static const struct mtk_parent sgm_0_parents[] = { 263 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 264 + APMIXED_PARENT(CLK_APMIXED_SGMPLL) 265 + }; 266 + 267 + /* CLK_TOP_SGM_SBUS_0_SEL (sgm_sbus_0_sel) in topckgen */ 268 + static const struct mtk_parent sgm_sbus_0_parents[] = { 269 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 270 + TOP_PARENT(CLK_TOP_NET1_D8_D4) 271 + }; 272 + 273 + /* CLK_TOP_SYSAPB_SEL (sysapb_sel) in topckgen */ 274 + static const struct mtk_parent sysapb_parents[] = { 275 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 276 + TOP_PARENT(CLK_TOP_M_D3_D2) 277 + }; 278 + 279 + /* CLK_TOP_ETH_REFCK_50M_SEL (eth_refck_50m_sel) in topckgen */ 280 + static const struct mtk_parent eth_refck_50m_parents[] = { 281 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 282 + TOP_PARENT(CLK_TOP_NET2_D4_D4) 283 + }; 284 + 285 + /* CLK_TOP_ETH_SYS_200M_SEL (eth_sys_200m_sel) in topckgen */ 286 + static const struct mtk_parent eth_sys_200m_parents[] = { 287 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 288 + TOP_PARENT(CLK_TOP_CB_NET2_D4) 289 + }; 290 + 291 + /* CLK_TOP_ETH_XGMII_SEL (eth_xgmii_sel) in topckgen */ 292 + static const struct mtk_parent eth_xgmii_parents[] = { 293 + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), 294 + TOP_PARENT(CLK_TOP_NET1_D8_D8), 295 + TOP_PARENT(CLK_TOP_NET1_D8_D16) 296 + }; 297 + 298 + /* CLK_TOP_DRAMC_MD32_SEL (dramc_md32_sel) in topckgen */ 299 + static const struct mtk_parent dramc_md32_parents[] = { 300 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 301 + TOP_PARENT(CLK_TOP_CB_M_D2), 302 + APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL) 303 + }; 304 + 305 + /* CLK_TOP_DA_XTP_GLB_P0_SEL (da_xtp_glb_p0_sel) in topckgen */ 306 + static const struct mtk_parent da_xtp_glb_p0_parents[] = { 307 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 308 + TOP_PARENT(CLK_TOP_CB_NET2_D8) 309 + }; 310 + 311 + /* CLK_TOP_DA_CKM_XTAL_SEL (da_ckm_xtal_sel) in topckgen */ 312 + static const struct mtk_parent da_ckm_xtal_parents[] = { 313 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 314 + TOP_PARENT(CLK_TOP_M_D8_D2) 315 + }; 316 + 317 + /* CLK_TOP_ETH_MII_SEL (eth_mii_sel) in topckgen */ 318 + static const struct mtk_parent eth_mii_parents[] = { 319 + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), 320 + TOP_PARENT(CLK_TOP_NET2_D4_D8) 321 + }; 322 + 323 + /* CLK_TOP_EMMC_200M_SEL (emmc_200m_sel) in topckgen */ 324 + static const struct mtk_parent emmc_200m_parents[] = { 325 + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), 326 + TOP_PARENT(CLK_TOP_MSDC_D2), 327 + TOP_PARENT(CLK_TOP_NET1_D7_D2), 328 + TOP_PARENT(CLK_TOP_CB_NET2_D6), 329 + TOP_PARENT(CLK_TOP_NET1_D7_D4) 330 + }; 331 + 332 + #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ 333 + _shift, _width, _gate, _upd_ofs, _upd) \ 334 + { \ 335 + .id = (_id), .mux_reg = (_mux_ofs), \ 336 + .mux_set_reg = (_mux_set_ofs), .mux_clr_reg = (_mux_clr_ofs), \ 337 + .upd_reg = (_upd_ofs), .upd_shift = (_upd), \ 338 + .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \ 339 + .gate_reg = (_mux_ofs), .gate_shift = (_gate), \ 340 + .parent_flags = (_parents), \ 341 + .num_parents = ARRAY_SIZE(_parents), \ 342 + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ 343 + } 344 + 345 + /* TOPCKGEN MUX_GATE */ 346 + static const struct mtk_composite topckgen_mtk_muxes[] = { 347 + TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 348 + 0x000, 0x004, 0x008, 0, 1, 7, 0x1C0, 0), 349 + TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", 350 + netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2, 15, 0x1C0, 1), 351 + TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 352 + 0x000, 0x004, 0x008, 16, 1, 23, 0x1C0, 2), 353 + TOP_MUX(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 354 + 0x000, 0x004, 0x008, 24, 1, 31, 0x1C0, 3), 355 + TOP_MUX(CLK_TOP_EIP_SEL, "eip_sel", eip_parents, 356 + 0x010, 0x014, 0x018, 0, 3, 7, 0x1C0, 4), 357 + TOP_MUX(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 358 + 0x010, 0x014, 0x018, 8, 1, 15, 0x1C0, 5), 359 + TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 360 + 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), 361 + TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 362 + 0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7), 363 + TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 364 + 0x020, 0x024, 0x028, 0, 3, 7, 0x1C0, 8), 365 + TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 366 + 0x020, 0x024, 0x028, 8, 3, 15, 0x1C0, 9), 367 + TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 368 + 0x020, 0x024, 0x028, 16, 3, 23, 0x1C0, 10), 369 + TOP_MUX(CLK_TOP_NFI_SEL, "nfi_sel", nfi_parents, 370 + 0x020, 0x024, 0x028, 24, 4, 31, 0x1C0, 11), 371 + TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 372 + 0x030, 0x034, 0x038, 0, 3, 7, 0x1C0, 12), 373 + TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 374 + 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), 375 + TOP_MUX(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel", 376 + pcie_mbist_250m_parents, 0x030, 0x034, 0x038, 16, 1, 23, 0x1C0, 14), 377 + TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, 378 + 0x030, 0x034, 0x038, 24, 3, 31, 0x1C0, 15), 379 + TOP_MUX(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel", 380 + pextp_tl_ck_parents, 0x040, 0x044, 0x048, 0, 3, 7, 0x1C0, 16), 381 + TOP_MUX(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 382 + 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), 383 + TOP_MUX(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 384 + 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), 385 + TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 386 + 0x040, 0x044, 0x048, 24, 1, 31, 0x1C0, 19), 387 + TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 388 + 0x050, 0x054, 0x058, 0, 1, 7, 0x1C0, 20), 389 + TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 390 + 0x050, 0x054, 0x058, 8, 2, 15, 0x1C0, 21), 391 + TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 392 + 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), 393 + TOP_MUX(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", usb_phy_parents, 394 + 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), 395 + TOP_MUX(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 396 + 0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24), 397 + TOP_MUX(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", sgm_sbus_0_parents, 398 + 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25), 399 + TOP_MUX(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 400 + 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), 401 + TOP_MUX(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", sgm_sbus_0_parents, 402 + 0x060, 0x064, 0x068, 24, 1, 31, 0x1C0, 27), 403 + TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 404 + 0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28), 405 + TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 406 + 0x070, 0x074, 0x078, 8, 1, 15, 0x1C0, 29), 407 + TOP_MUX(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", 408 + eth_refck_50m_parents, 0x070, 0x074, 0x078, 16, 1, 23, 0x1C0, 30), 409 + TOP_MUX(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", 410 + eth_sys_200m_parents, 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0), 411 + TOP_MUX(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 412 + 0x080, 0x084, 0x088, 0, 1, 7, 0x1C4, 1), 413 + TOP_MUX(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 414 + 0x080, 0x084, 0x088, 8, 2, 15, 0x1C4, 2), 415 + TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", usb_phy_parents, 416 + 0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3), 417 + TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, 418 + 0x080, 0x084, 0x088, 24, 2, 31, 0x1C4, 4), 419 + TOP_MUX(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", 420 + usb_phy_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5), 421 + TOP_MUX(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", usb_phy_parents, 422 + 0x090, 0x094, 0x098, 8, 1, 15, 0x1C4, 6), 423 + TOP_MUX(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", usb_phy_parents, 424 + 0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7), 425 + TOP_MUX(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", 426 + da_xtp_glb_p0_parents, 0x090, 0x094, 0x098, 24, 1, 31, 0x1C4, 8), 427 + TOP_MUX(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", 428 + da_xtp_glb_p0_parents, 0x0A0, 0x0A4, 0x0A8, 0, 1, 7, 0x1C4, 9), 429 + TOP_MUX(CLK_TOP_CKM_SEL, "ckm_sel", usb_phy_parents, 430 + 0x0A0, 0x0A4, 0x0A8, 8, 1, 15, 0x1C4, 10), 431 + TOP_MUX(CLK_TOP_DA_CKM_XTAL_SEL, "da_ckm_xtal_sel", 432 + da_ckm_xtal_parents, 0x0A0, 0x0A4, 0x0A8, 16, 1, 23, 0x1C4, 11), 433 + TOP_MUX(CLK_TOP_PEXTP_SEL, "pextp_sel", usb_phy_parents, 434 + 0x0A0, 0x0A4, 0x0A8, 24, 1, 31, 0x1C4, 12), 435 + TOP_MUX(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 436 + 0x0B0, 0x0B4, 0x0B8, 0, 1, 7, 0x1C4, 13), 437 + TOP_MUX(CLK_TOP_EMMC_200M_SEL, "emmc_200m_sel", emmc_200m_parents, 438 + 0x0B0, 0x0B4, 0x0B8, 8, 3, 15, 0x1C4, 14), 439 + }; 440 + 441 + static const struct mtk_clk_tree mt7987_topckgen_clk_tree = { 442 + .muxes_offs = CLK_TOP_NETSYS_SEL, 443 + .fdivs = topckgen_mtk_fixed_factors, 444 + .muxes = topckgen_mtk_muxes, 445 + .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN, 446 + .xtal_rate = MT7987_XTAL_RATE, 447 + }; 448 + 449 + static const struct udevice_id mt7987_topckgen_compat[] = { 450 + { .compatible = "mediatek,mt7987-topckgen" }, 451 + {} 452 + }; 453 + 454 + static int mt7987_topckgen_probe(struct udevice *dev) 455 + { 456 + struct mtk_clk_priv *priv = dev_get_priv(dev); 457 + 458 + priv->base = dev_read_addr_ptr(dev); 459 + if (!priv->base) 460 + return -ENOENT; 461 + 462 + writel(MT7987_CLK_PDN_EN_WRITE, priv->base + MT7987_CLK_PDN); 463 + return mtk_common_clk_init(dev, &mt7987_topckgen_clk_tree); 464 + } 465 + 466 + U_BOOT_DRIVER(mtk_clk_topckgen) = { 467 + .name = "mt7987-clock-topckgen", 468 + .id = UCLASS_CLK, 469 + .of_match = mt7987_topckgen_compat, 470 + .probe = mt7987_topckgen_probe, 471 + .priv_auto = sizeof(struct mtk_clk_priv), 472 + .ops = &mtk_clk_topckgen_ops, 473 + .flags = DM_FLAG_PRE_RELOC, 474 + }; 475 + 476 + /* INFRASYS MUX PARENTS */ 477 + 478 + /* CLK_INFRA_MUX_UART0_SEL (infra_mux_uart0_sel) in infracfg */ 479 + static const int infra_mux_uart0_parents[] = { 480 + CLK_TOP_INFRA_F26M_SEL, 481 + CLK_TOP_UART_SEL 482 + }; 483 + 484 + /* CLK_INFRA_MUX_UART1_SEL (infra_mux_uart1_sel) in infracfg */ 485 + static const int infra_mux_uart1_parents[] = { 486 + CLK_TOP_INFRA_F26M_SEL, 487 + CLK_TOP_UART_SEL 488 + }; 489 + 490 + /* CLK_INFRA_MUX_UART2_SEL (infra_mux_uart2_sel) in infracfg */ 491 + static const int infra_mux_uart2_parents[] = { 492 + CLK_TOP_INFRA_F26M_SEL, 493 + CLK_TOP_UART_SEL 494 + }; 495 + 496 + /* CLK_INFRA_MUX_SPI0_SEL (infra_mux_spi0_sel) in infracfg */ 497 + static const int infra_mux_spi0_parents[] = { 498 + CLK_TOP_I2C_SEL, 499 + CLK_TOP_SPI_SEL 500 + }; 501 + 502 + /* CLK_INFRA_MUX_SPI1_SEL (infra_mux_spi1_sel) in infracfg */ 503 + static const int infra_mux_spi1_parents[] = { 504 + CLK_TOP_I2C_SEL, 505 + CLK_TOP_SPIM_MST_SEL 506 + }; 507 + 508 + /* CLK_INFRA_MUX_SPI2_BCK_SEL (infra_mux_spi2_bck_sel) in infracfg */ 509 + static const int infra_mux_spi2_bck_parents[] = { 510 + CLK_TOP_I2C_SEL, 511 + CLK_TOP_SPI_SEL 512 + }; 513 + 514 + /* CLK_INFRA_PWM_BCK_SEL (infra_pwm_bck_sel) in infracfg */ 515 + static const int infra_pwm_bck_parents[] = { 516 + CLK_TOP_CB_RTC_32P7K, 517 + CLK_TOP_INFRA_F26M_SEL, 518 + CLK_TOP_SYSAXI_SEL, 519 + CLK_TOP_PWM_SEL 520 + }; 521 + 522 + /* CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL (infra_pcie_gfmux_tl_ck_o_p0_sel) in infracfg */ 523 + static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = { 524 + CLK_TOP_CB_RTC_32P7K, 525 + CLK_TOP_INFRA_F26M_SEL, 526 + CLK_TOP_INFRA_F26M_SEL, 527 + CLK_TOP_PEXTP_TL_SEL 528 + }; 529 + 530 + /* CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL (infra_pcie_gfmux_tl_ck_o_p1_sel) in infracfg */ 531 + static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { 532 + CLK_TOP_CB_RTC_32P7K, 533 + CLK_TOP_INFRA_F26M_SEL, 534 + CLK_TOP_INFRA_F26M_SEL, 535 + CLK_TOP_PEXTP_TL_P1_SEL 536 + }; 537 + 538 + #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ 539 + { \ 540 + .id = (_id), .mux_reg = (_reg) + 0x8, \ 541 + .mux_clr_reg = (_reg) + 0x4, .mux_set_reg = (_reg) + 0x0, \ 542 + .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \ 543 + .gate_shift = -1, .upd_shift = -1, \ 544 + .parent = (_parents), .num_parents = ARRAY_SIZE(_parents), \ 545 + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ 546 + } 547 + 548 + /* INFRA MUX */ 549 + static const struct mtk_composite infracfg_mtk_mux[] = { 550 + INFRA_MUX(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", 551 + infra_mux_uart0_parents, 0x0010, 0, 1), 552 + INFRA_MUX(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", 553 + infra_mux_uart1_parents, 0x0010, 1, 1), 554 + INFRA_MUX(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", 555 + infra_mux_uart2_parents, 0x0010, 2, 1), 556 + INFRA_MUX(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", 557 + infra_mux_spi0_parents, 0x0010, 4, 1), 558 + INFRA_MUX(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", 559 + infra_mux_spi1_parents, 0x0010, 5, 1), 560 + INFRA_MUX(CLK_INFRA_MUX_SPI2_BCK_SEL, "infra_mux_spi2_bck_sel", 561 + infra_mux_spi2_bck_parents, 0x0010, 6, 1), 562 + INFRA_MUX(CLK_INFRA_PWM_BCK_SEL, "infra_pwm_bck_sel", 563 + infra_pwm_bck_parents, 0x0010, 14, 2), 564 + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_ck_o_p0_sel", 565 + infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0020, 0, 2), 566 + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_ck_o_p1_sel", 567 + infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0020, 2, 2), 568 + }; 569 + 570 + static const struct mtk_gate_regs infra_0_cg_regs = { 571 + .set_ofs = 0x10, 572 + .clr_ofs = 0x14, 573 + .sta_ofs = 0x18, 574 + }; 575 + 576 + static const struct mtk_gate_regs infra_1_cg_regs = { 577 + .set_ofs = 0x40, 578 + .clr_ofs = 0x44, 579 + .sta_ofs = 0x48, 580 + }; 581 + 582 + static const struct mtk_gate_regs infra_2_cg_regs = { 583 + .set_ofs = 0x50, 584 + .clr_ofs = 0x54, 585 + .sta_ofs = 0x58, 586 + }; 587 + 588 + static const struct mtk_gate_regs infra_3_cg_regs = { 589 + .set_ofs = 0x60, 590 + .clr_ofs = 0x64, 591 + .sta_ofs = 0x68, 592 + }; 593 + 594 + #define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \ 595 + { \ 596 + .id = (_id), .parent = (_parent), .regs = &infra_0_cg_regs, \ 597 + .shift = (_shift), \ 598 + .flags = (_flags), \ 599 + } 600 + #define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ 601 + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) 602 + #define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ 603 + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) 604 + 605 + #define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \ 606 + { \ 607 + .id = (_id), .parent = (_parent), .regs = &infra_1_cg_regs, \ 608 + .shift = (_shift), \ 609 + .flags = (_flags), \ 610 + } 611 + #define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ 612 + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) 613 + #define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ 614 + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) 615 + 616 + #define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \ 617 + { \ 618 + .id = (_id), .parent = (_parent), .regs = &infra_2_cg_regs, \ 619 + .shift = (_shift), \ 620 + .flags = (_flags), \ 621 + } 622 + #define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ 623 + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) 624 + #define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \ 625 + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) 626 + 627 + #define GATE_INFRA3(_id, _name, _parent, _shift, _flags) \ 628 + { \ 629 + .id = (_id), .parent = (_parent), .regs = &infra_3_cg_regs, \ 630 + .shift = (_shift), \ 631 + .flags = (_flags), \ 632 + } 633 + #define GATE_INFRA3_INFRA(_id, _name, _parent, _shift) \ 634 + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) 635 + #define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ 636 + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) 637 + #define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \ 638 + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) 639 + 640 + /* INFRA GATE */ 641 + static const struct mtk_gate infracfg_mtk_gates[] = { 642 + GATE_INFRA1_TOP(CLK_INFRA_66M_GPT_BCK, 643 + "infra_hf_66m_gpt_bck", CLK_TOP_SYSAXI_SEL, 0), 644 + GATE_INFRA1_TOP(CLK_INFRA_66M_PWM_HCK, 645 + "infra_hf_66m_pwm_hck", CLK_TOP_SYSAXI_SEL, 1), 646 + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_BCK, 647 + "infra_hf_66m_pwm_bck", CLK_INFRA_PWM_BCK_SEL, 2), 648 + GATE_INFRA1_TOP(CLK_INFRA_133M_CQDMA_BCK, 649 + "infra_hf_133m_cqdma_bck", CLK_TOP_SYSAXI_SEL, 12), 650 + GATE_INFRA1_TOP(CLK_INFRA_66M_AUD_SLV_BCK, 651 + "infra_66m_aud_slv_bck", CLK_TOP_SYSAXI_SEL, 13), 652 + GATE_INFRA1_TOP(CLK_INFRA_AUD_26M, "infra_f_faud_26m", 653 + CLK_TOP_INFRA_F26M_SEL, 14), 654 + GATE_INFRA1_TOP(CLK_INFRA_AUD_L, "infra_f_faud_l", CLK_TOP_AUD_L_SEL, 15), 655 + GATE_INFRA1_TOP(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", CLK_TOP_A1SYS_SEL, 16), 656 + GATE_INFRA1_TOP(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", 657 + CLK_TOP_A_TUNER_SEL, 18), 658 + GATE_INFRA1_TOP(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", 659 + CLK_TOP_INFRA_F26M_SEL, 19), 660 + GATE_INFRA1_TOP(CLK_INFRA_133M_DBG_ACKM, 661 + "infra_hf_133m_dbg_ackm", CLK_TOP_SYSAXI_SEL, 20), 662 + GATE_INFRA1_TOP(CLK_INFRA_66M_AP_DMA_BCK, 663 + "infra_66m_ap_dma_bck", CLK_TOP_SYSAXI_SEL, 21), 664 + GATE_INFRA1_TOP(CLK_INFRA_MSDC200_SRC, "infra_f_fmsdc200_src", 665 + CLK_TOP_EMMC_200M_SEL, 28), 666 + GATE_INFRA1_TOP(CLK_INFRA_66M_SEJ_BCK, 667 + "infra_hf_66m_sej_bck", CLK_TOP_SYSAXI_SEL, 29), 668 + GATE_INFRA1_TOP(CLK_INFRA_PRE_CK_SEJ_F13M, 669 + "infra_pre_ck_sej_f13m", CLK_TOP_INFRA_F26M_SEL, 30), 670 + GATE_INFRA1_TOP(CLK_INFRA_66M_TRNG, "infra_hf_66m_trng", 671 + CLK_TOP_SYSAXI_SEL, 31), 672 + GATE_INFRA2_TOP(CLK_INFRA_26M_THERM_SYSTEM, 673 + "infra_hf_26m_therm_system", CLK_TOP_INFRA_F26M_SEL, 0), 674 + GATE_INFRA2_TOP(CLK_INFRA_I2C_BCK, "infra_i2c_bck", CLK_TOP_I2C_SEL, 1), 675 + GATE_INFRA2_TOP(CLK_INFRA_66M_UART0_PCK, 676 + "infra_hf_66m_uart0_pck", CLK_TOP_SYSAXI_SEL, 3), 677 + GATE_INFRA2_TOP(CLK_INFRA_66M_UART1_PCK, 678 + "infra_hf_66m_uart1_pck", CLK_TOP_SYSAXI_SEL, 4), 679 + GATE_INFRA2_TOP(CLK_INFRA_66M_UART2_PCK, 680 + "infra_hf_66m_uart2_pck", CLK_TOP_SYSAXI_SEL, 5), 681 + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART0_CK, 682 + "infra_f_52m_uart0", CLK_INFRA_MUX_UART0_SEL, 3), 683 + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART1_CK, 684 + "infra_f_52m_uart1", CLK_INFRA_MUX_UART1_SEL, 4), 685 + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART2_CK, 686 + "infra_f_52m_uart2", CLK_INFRA_MUX_UART2_SEL, 5), 687 + GATE_INFRA2_TOP(CLK_INFRA_NFI, "infra_f_fnfi", CLK_TOP_NFI_SEL, 9), 688 + GATE_INFRA2_TOP(CLK_INFRA_66M_NFI_HCK, 689 + "infra_hf_66m_nfi_hck", CLK_TOP_SYSAXI_SEL, 11), 690 + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", 691 + CLK_INFRA_MUX_SPI0_SEL, 12), 692 + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", 693 + CLK_INFRA_MUX_SPI1_SEL, 13), 694 + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI2_BCK, 695 + "infra_hf_104m_spi2_bck", CLK_INFRA_MUX_SPI2_BCK_SEL, 14), 696 + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI0_HCK, 697 + "infra_hf_66m_spi0_hck", CLK_TOP_SYSAXI_SEL, 15), 698 + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI1_HCK, 699 + "infra_hf_66m_spi1_hck", CLK_TOP_SYSAXI_SEL, 16), 700 + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI2_HCK, 701 + "infra_hf_66m_spi2_hck", CLK_TOP_SYSAXI_SEL, 17), 702 + GATE_INFRA2_TOP(CLK_INFRA_66M_FLASHIF_AXI, 703 + "infra_hf_66m_flashif_axi", CLK_TOP_SYSAXI_SEL, 18), 704 + GATE_INFRA2_TOP(CLK_INFRA_RTC, "infra_f_frtc", CLK_TOP_CB_RTC_32K, 19), 705 + GATE_INFRA2_TOP(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", 706 + CLK_TOP_INFRA_F26M_SEL, 20), 707 + GATE_INFRA2_INFRA(CLK_INFRA_RC_ADC, "infra_f_frc_adc", 708 + CLK_INFRA_26M_ADC_BCK, 21), 709 + GATE_INFRA2_TOP(CLK_INFRA_MSDC400, "infra_f_fmsdc400", 710 + CLK_TOP_EMMC_400M_SEL, 22), 711 + GATE_INFRA2_TOP(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", 712 + CLK_TOP_EMMC_250M_SEL, 23), 713 + GATE_INFRA2_TOP(CLK_INFRA_133M_MSDC_0_HCK, 714 + "infra_hf_133m_msdc_0_hck", CLK_TOP_SYSAXI_SEL, 24), 715 + GATE_INFRA2_TOP(CLK_INFRA_66M_MSDC_0_HCK, 716 + "infra_66m_msdc_0_hck", CLK_TOP_SYSAXI_SEL, 25), 717 + GATE_INFRA2_TOP(CLK_INFRA_133M_CPUM_BCK, 718 + "infra_hf_133m_cpum_bck", CLK_TOP_SYSAXI_SEL, 26), 719 + GATE_INFRA2_TOP(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", 720 + CLK_TOP_NFI_SEL, 27), 721 + GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_MCK_CK_P1, 722 + "infra_hf_i2c_x16w_mck_ck_p1", CLK_TOP_SYSAXI_SEL, 29), 723 + GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_PCK_CK_P1, 724 + "infra_hf_i2c_x16w_pck_ck_p1", CLK_TOP_SYSAXI_SEL, 31), 725 + GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK, 726 + "infra_133m_usb_hck", CLK_TOP_SYSAXI_SEL, 0), 727 + GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK_CK_P1, 728 + "infra_133m_usb_hck_ck_p1", CLK_TOP_SYSAXI_SEL, 1), 729 + GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", 730 + CLK_TOP_SYSAXI_SEL, 2), 731 + GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK_CK_P1, 732 + "infra_66m_usb_hck_ck_p1", CLK_TOP_SYSAXI_SEL, 3), 733 + GATE_INFRA3_TOP(CLK_INFRA_USB_SYS_CK_P1, 734 + "infra_usb_sys_ck_p1", CLK_TOP_USB_SYS_P1_SEL, 5), 735 + GATE_INFRA3_TOP(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", 736 + CLK_TOP_CB_CKSQ_40M, 7), 737 + GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, 738 + "infra_usb_frmcnt_ck_p1", CLK_TOP_CKSQ_40M_D2, 9), 739 + GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, 740 + "infra_usb_pipe_ck_p1", CLK_XTAL, 11), 741 + GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, 742 + "infra_usb_utmi_ck_p1", CLK_XTAL, 13), 743 + GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, 744 + "infra_usb_xhci_ck_p1", CLK_TOP_USB_XHCI_P1_SEL, 15), 745 + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P0, 746 + "infra_pcie_gfmux_tl_ck_p0", CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20), 747 + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P1, 748 + "infra_pcie_gfmux_tl_ck_p1", CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21), 749 + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, 750 + "infra_pcie_pipe_ck_p0", CLK_XTAL, 24), 751 + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, 752 + "infra_pcie_pipe_ck_p1", CLK_XTAL, 25), 753 + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, 754 + "infra_133m_pcie_ck_p0", CLK_TOP_SYSAXI_SEL, 28), 755 + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, 756 + "infra_133m_pcie_ck_p1", CLK_TOP_SYSAXI_SEL, 29), 757 + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P0, 758 + "infra_pcie_peri_ck_26m_ck_p0", CLK_TOP_INFRA_F26M_SEL, 7), 759 + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P1, 760 + "infra_pcie_peri_ck_26m_ck_p1", CLK_TOP_INFRA_F26M_SEL, 8), 761 + }; 762 + 763 + static const struct mtk_clk_tree mt7987_infracfg_clk_tree = { 764 + .muxes_offs = CLK_INFRA_MUX_UART0_SEL, 765 + .gates_offs = CLK_INFRA_66M_GPT_BCK, 766 + .muxes = infracfg_mtk_mux, 767 + .gates = infracfg_mtk_gates, 768 + .flags = CLK_BYPASS_XTAL, 769 + .xtal_rate = MT7987_XTAL_RATE, 770 + }; 771 + 772 + static const struct udevice_id mt7987_infracfg_compat[] = { 773 + { .compatible = "mediatek,mt7987-infracfg_ao" }, 774 + { .compatible = "mediatek,mt7987-infracfg" }, 775 + {} 776 + }; 777 + 778 + static int mt7987_infracfg_probe(struct udevice *dev) 779 + { 780 + return mtk_common_clk_infrasys_init(dev, &mt7987_infracfg_clk_tree); 781 + } 782 + 783 + U_BOOT_DRIVER(mtk_clk_infracfg) = { 784 + .name = "mt7987-clock-infracfg", 785 + .id = UCLASS_CLK, 786 + .of_match = mt7987_infracfg_compat, 787 + .probe = mt7987_infracfg_probe, 788 + .priv_auto = sizeof(struct mtk_clk_priv), 789 + .ops = &mtk_clk_infrasys_ops, 790 + .flags = DM_FLAG_PRE_RELOC, 791 + }; 792 + 793 + /* ethsys */ 794 + static const struct mtk_gate_regs eth_cg_regs = { 795 + .set_ofs = 0x30, 796 + .clr_ofs = 0x30, 797 + .sta_ofs = 0x30, 798 + }; 799 + 800 + #define GATE_ETH_TOP(_id, _name, _parent, _shift) \ 801 + { \ 802 + .id = (_id), .parent = (_parent), .regs = &eth_cg_regs, \ 803 + .shift = (_shift), \ 804 + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ 805 + } 806 + 807 + static const struct mtk_gate eth_cgs[] = { 808 + GATE_ETH_TOP(CLK_ETHDMA_FE_EN, "ethdma_fe_en", CLK_TOP_NETSYS_2X_SEL, 6), 809 + GATE_ETH_TOP(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", CLK_TOP_NETSYS_500M_SEL, 7), 810 + GATE_ETH_TOP(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", CLK_TOP_NETSYS_500M_SEL, 8), 811 + GATE_ETH_TOP(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", CLK_TOP_NETSYS_500M_SEL, 10), 812 + }; 813 + 814 + static int mt7987_ethsys_probe(struct udevice *dev) 815 + { 816 + return mtk_common_clk_gate_init(dev, &mt7987_topckgen_clk_tree, 817 + eth_cgs); 818 + } 819 + 820 + static int mt7987_ethsys_bind(struct udevice *dev) 821 + { 822 + int ret = 0; 823 + 824 + if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) { 825 + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); 826 + if (ret) 827 + debug("Warning: failed to bind reset controller\n"); 828 + } 829 + 830 + return ret; 831 + } 832 + 833 + static const struct udevice_id mt7987_ethsys_compat[] = { 834 + { 835 + .compatible = "mediatek,mt7987-ethsys", 836 + }, 837 + {} 838 + }; 839 + 840 + U_BOOT_DRIVER(mtk_clk_ethsys) = { 841 + .name = "mt7987-clock-ethsys", 842 + .id = UCLASS_CLK, 843 + .of_match = mt7987_ethsys_compat, 844 + .probe = mt7987_ethsys_probe, 845 + .bind = mt7987_ethsys_bind, 846 + .priv_auto = sizeof(struct mtk_cg_priv), 847 + .ops = &mtk_clk_gate_ops, 848 + };
+206
include/dt-bindings/clock/mediatek,mt7987-clk.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2024 MediaTek Inc. 4 + * Author: Lu Tang <Lu.Tang@mediatek.com> 5 + * Author: Sam Shih <sam.shih@mediatek.com> 6 + */ 7 + 8 + #ifndef _DT_BINDINGS_CLK_MT7987_H 9 + #define _DT_BINDINGS_CLK_MT7987_H 10 + 11 + /* INFRACFG */ 12 + 13 + #define CLK_INFRA_MUX_UART0_SEL 0 14 + #define CLK_INFRA_MUX_UART1_SEL 1 15 + #define CLK_INFRA_MUX_UART2_SEL 2 16 + #define CLK_INFRA_MUX_SPI0_SEL 3 17 + #define CLK_INFRA_MUX_SPI1_SEL 4 18 + #define CLK_INFRA_MUX_SPI2_BCK_SEL 5 19 + #define CLK_INFRA_PWM_BCK_SEL 6 20 + #define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 7 21 + #define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 8 22 + #define CLK_INFRA_66M_GPT_BCK 9 23 + #define CLK_INFRA_66M_PWM_HCK 10 24 + #define CLK_INFRA_66M_PWM_BCK 11 25 + #define CLK_INFRA_133M_CQDMA_BCK 12 26 + #define CLK_INFRA_66M_AUD_SLV_BCK 13 27 + #define CLK_INFRA_AUD_26M 14 28 + #define CLK_INFRA_AUD_L 15 29 + #define CLK_INFRA_AUD_AUD 16 30 + #define CLK_INFRA_AUD_EG2 17 31 + #define CLK_INFRA_DRAMC_F26M 18 32 + #define CLK_INFRA_133M_DBG_ACKM 19 33 + #define CLK_INFRA_66M_AP_DMA_BCK 20 34 + #define CLK_INFRA_MSDC200_SRC 21 35 + #define CLK_INFRA_66M_SEJ_BCK 22 36 + #define CLK_INFRA_PRE_CK_SEJ_F13M 23 37 + #define CLK_INFRA_66M_TRNG 24 38 + #define CLK_INFRA_26M_THERM_SYSTEM 25 39 + #define CLK_INFRA_I2C_BCK 26 40 + #define CLK_INFRA_66M_UART0_PCK 27 41 + #define CLK_INFRA_66M_UART1_PCK 28 42 + #define CLK_INFRA_66M_UART2_PCK 29 43 + #define CLK_INFRA_52M_UART0_CK 30 44 + #define CLK_INFRA_52M_UART1_CK 31 45 + #define CLK_INFRA_52M_UART2_CK 32 46 + #define CLK_INFRA_NFI 33 47 + #define CLK_INFRA_66M_NFI_HCK 34 48 + #define CLK_INFRA_104M_SPI0 35 49 + #define CLK_INFRA_104M_SPI1 36 50 + #define CLK_INFRA_104M_SPI2_BCK 37 51 + #define CLK_INFRA_66M_SPI0_HCK 38 52 + #define CLK_INFRA_66M_SPI1_HCK 39 53 + #define CLK_INFRA_66M_SPI2_HCK 40 54 + #define CLK_INFRA_66M_FLASHIF_AXI 41 55 + #define CLK_INFRA_RTC 42 56 + #define CLK_INFRA_26M_ADC_BCK 43 57 + #define CLK_INFRA_RC_ADC 44 58 + #define CLK_INFRA_MSDC400 45 59 + #define CLK_INFRA_MSDC2_HCK 46 60 + #define CLK_INFRA_133M_MSDC_0_HCK 47 61 + #define CLK_INFRA_66M_MSDC_0_HCK 48 62 + #define CLK_INFRA_133M_CPUM_BCK 49 63 + #define CLK_INFRA_BIST2FPC 50 64 + #define CLK_INFRA_I2C_X16W_MCK_CK_P1 51 65 + #define CLK_INFRA_I2C_X16W_PCK_CK_P1 52 66 + #define CLK_INFRA_133M_USB_HCK 53 67 + #define CLK_INFRA_133M_USB_HCK_CK_P1 54 68 + #define CLK_INFRA_66M_USB_HCK 55 69 + #define CLK_INFRA_66M_USB_HCK_CK_P1 56 70 + #define CLK_INFRA_USB_SYS_CK_P1 57 71 + #define CLK_INFRA_USB_CK_P1 58 72 + #define CLK_INFRA_USB_FRMCNT_CK_P1 59 73 + #define CLK_INFRA_USB_PIPE_CK_P1 60 74 + #define CLK_INFRA_USB_UTMI_CK_P1 61 75 + #define CLK_INFRA_USB_XHCI_CK_P1 62 76 + #define CLK_INFRA_PCIE_GFMUX_TL_P0 63 77 + #define CLK_INFRA_PCIE_GFMUX_TL_P1 64 78 + #define CLK_INFRA_PCIE_PIPE_P0 65 79 + #define CLK_INFRA_PCIE_PIPE_P1 66 80 + #define CLK_INFRA_133M_PCIE_CK_P0 67 81 + #define CLK_INFRA_133M_PCIE_CK_P1 68 82 + #define CLK_INFRA_PCIE_PERI_26M_CK_P0 69 83 + #define CLK_INFRA_PCIE_PERI_26M_CK_P1 70 84 + #define CLK_INFRA_NR_CLK 71 85 + 86 + /* TOPCKGEN */ 87 + 88 + #define CLK_TOP_CB_M_D2 0 89 + #define CLK_TOP_CB_M_D3 1 90 + #define CLK_TOP_M_D3_D2 2 91 + #define CLK_TOP_CB_M_D4 3 92 + #define CLK_TOP_CB_M_D8 4 93 + #define CLK_TOP_M_D8_D2 5 94 + #define CLK_TOP_CB_APLL2_D4 6 95 + #define CLK_TOP_CB_NET1_D3 7 96 + #define CLK_TOP_CB_NET1_D4 8 97 + #define CLK_TOP_CB_NET1_D5 9 98 + #define CLK_TOP_NET1_D5_D2 10 99 + #define CLK_TOP_NET1_D5_D4 11 100 + #define CLK_TOP_CB_NET1_D7 12 101 + #define CLK_TOP_NET1_D7_D2 13 102 + #define CLK_TOP_NET1_D7_D4 14 103 + #define CLK_TOP_NET1_D8_D2 15 104 + #define CLK_TOP_NET1_D8_D4 16 105 + #define CLK_TOP_NET1_D8_D8 17 106 + #define CLK_TOP_NET1_D8_D16 18 107 + #define CLK_TOP_CB_NET2_D2 19 108 + #define CLK_TOP_CB_NET2_D4 20 109 + #define CLK_TOP_NET2_D4_D4 21 110 + #define CLK_TOP_NET2_D4_D8 22 111 + #define CLK_TOP_CB_NET2_D6 23 112 + #define CLK_TOP_NET2_D7_D2 24 113 + #define CLK_TOP_CB_NET2_D8 25 114 + #define CLK_TOP_MSDC_D2 26 115 + #define CLK_TOP_CB_CKSQ_40M 27 116 + #define CLK_TOP_CKSQ_40M_D2 28 117 + #define CLK_TOP_CB_RTC_32K 29 118 + #define CLK_TOP_CB_RTC_32P7K 30 119 + #define CLK_TOP_NETSYS_SEL 31 120 + #define CLK_TOP_NETSYS_500M_SEL 32 121 + #define CLK_TOP_NETSYS_2X_SEL 33 122 + #define CLK_TOP_ETH_GMII_SEL 34 123 + #define CLK_TOP_EIP_SEL 35 124 + #define CLK_TOP_AXI_INFRA_SEL 36 125 + #define CLK_TOP_UART_SEL 37 126 + #define CLK_TOP_EMMC_250M_SEL 38 127 + #define CLK_TOP_EMMC_400M_SEL 39 128 + #define CLK_TOP_SPI_SEL 40 129 + #define CLK_TOP_SPIM_MST_SEL 41 130 + #define CLK_TOP_NFI_SEL 42 131 + #define CLK_TOP_PWM_SEL 43 132 + #define CLK_TOP_I2C_SEL 44 133 + #define CLK_TOP_PCIE_MBIST_250M_SEL 45 134 + #define CLK_TOP_PEXTP_TL_SEL 46 135 + #define CLK_TOP_PEXTP_TL_P1_SEL 47 136 + #define CLK_TOP_USB_SYS_P1_SEL 48 137 + #define CLK_TOP_USB_XHCI_P1_SEL 49 138 + #define CLK_TOP_AUD_SEL 50 139 + #define CLK_TOP_A1SYS_SEL 51 140 + #define CLK_TOP_AUD_L_SEL 52 141 + #define CLK_TOP_A_TUNER_SEL 53 142 + #define CLK_TOP_USB_PHY_SEL 54 143 + #define CLK_TOP_SGM_0_SEL 55 144 + #define CLK_TOP_SGM_SBUS_0_SEL 56 145 + #define CLK_TOP_SGM_1_SEL 57 146 + #define CLK_TOP_SGM_SBUS_1_SEL 58 147 + #define CLK_TOP_SYSAXI_SEL 59 148 + #define CLK_TOP_SYSAPB_SEL 60 149 + #define CLK_TOP_ETH_REFCK_50M_SEL 61 150 + #define CLK_TOP_ETH_SYS_200M_SEL 62 151 + #define CLK_TOP_ETH_SYS_SEL 63 152 + #define CLK_TOP_ETH_XGMII_SEL 64 153 + #define CLK_TOP_DRAMC_SEL 65 154 + #define CLK_TOP_DRAMC_MD32_SEL 66 155 + #define CLK_TOP_INFRA_F26M_SEL 67 156 + #define CLK_TOP_PEXTP_P0_SEL 68 157 + #define CLK_TOP_PEXTP_P1_SEL 69 158 + #define CLK_TOP_DA_XTP_GLB_P0_SEL 70 159 + #define CLK_TOP_DA_XTP_GLB_P1_SEL 71 160 + #define CLK_TOP_CKM_SEL 72 161 + #define CLK_TOP_DA_CKM_XTAL_SEL 73 162 + #define CLK_TOP_PEXTP_SEL 74 163 + #define CLK_TOP_ETH_MII_SEL 75 164 + #define CLK_TOP_EMMC_200M_SEL 76 165 + #define CLK_TOP_AUD_I2S_M 77 166 + #define CLK_TOP_NR_CLK 78 167 + 168 + /* APMIXEDSYS */ 169 + 170 + #define CLK_APMIXED_MPLL 0 171 + #define CLK_APMIXED_APLL2 1 172 + #define CLK_APMIXED_NET1PLL 2 173 + #define CLK_APMIXED_NET2PLL 3 174 + #define CLK_APMIXED_WEDMCUPLL 4 175 + #define CLK_APMIXED_SGMPLL 5 176 + #define CLK_APMIXED_ARM_LL 6 177 + #define CLK_APMIXED_MSDCPLL 7 178 + #define CLK_APMIXED_NR_CLK 8 179 + 180 + /* MCUSYS */ 181 + 182 + #define CLK_MCU_BUS_DIV_SEL 0 183 + #define CLK_MCU_NR_CLK 1 184 + 185 + /* SGMIISYS_0 */ 186 + 187 + #define CLK_SGM0_TX_EN 0 188 + #define CLK_SGM0_RX_EN 1 189 + #define CLK_SGMII0_NR_CLK 2 190 + 191 + /* SGMIISYS_1 */ 192 + 193 + #define CLK_SGM1_TX_EN 0 194 + #define CLK_SGM1_RX_EN 1 195 + #define CLK_SGMII1_NR_CLK 2 196 + 197 + /* ETHDMA */ 198 + 199 + #define CLK_ETHDMA_FE_EN 0 200 + #define CLK_ETHDMA_GP2_EN 1 201 + #define CLK_ETHDMA_GP1_EN 2 202 + #define CLK_ETHDMA_GP3_EN 3 203 + #define CLK_ETHDMA_NR_CLK 4 204 + 205 + #endif /* _DT_BINDINGS_CLK_MT7987_H */ 206 +