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"Das U-Boot" Source Tree
rockhip: rk3128: Add basic SoC init file
In order to prepare the switch to TPL/SPL for RK3128 provide basic Soc
init, which currently supports getting the boot device, initialization of
all 3 uart channels pins or usb uart, and disable forcing to JTAG mode of
the sdmmc/uart2 pins.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
+149
+1
arch/arm/mach-rockchip/rk3128/Makefile
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arch/arm/mach-rockchip/rk3128/Makefile
+148
arch/arm/mach-rockchip/rk3128/rk3128.c
+148
arch/arm/mach-rockchip/rk3128/rk3128.c
···
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// SPDX-License-Identifier: GPL-2.0+
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#include <init.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/grf_rk3128.h>
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#include <asm/arch-rockchip/hardware.h>
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#define GRF_BASE 0x20008000
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/mmc@1021c000",
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[BROM_BOOTSOURCE_SPINOR] = "/spi@1020c000/flash@0",
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[BROM_BOOTSOURCE_SPINAND] = "/spi@1020c000/flash@0",
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[BROM_BOOTSOURCE_SD] = "/mmc@10214000",
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};
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#if IS_ENABLED(CONFIG_DEBUG_UART_BOARD_INIT) && defined(CONFIG_DEBUG_UART_BASE)
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void board_debug_uart_init(void)
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{
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struct rk3128_grf * const grf = (void *)GRF_BASE;
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#if CONFIG_DEBUG_UART_BASE == 0x20060000
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enum {
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GPIO2D2_SHIFT = 4,
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GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
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GPIO2D2_UART0_SOUT = 2,
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GPIO2D3_SHIFT = 6,
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GPIO2D3_MASK = 3 << GPIO2D3_SHIFT,
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GPIO2D3_UART0_SIN = 2,
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};
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rk_clrsetreg(&grf->gpio1b_iomux,
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GPIO2D2_MASK | GPIO2D3_MASK,
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GPIO2D2_UART0_SOUT << GPIO2D2_SHIFT |
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GPIO2D3_UART0_SIN << GPIO2D3_SHIFT);
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#elif CONFIG_DEBUG_UART_BASE == 0x20064000
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enum {
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GPIO1B1_SHIFT = 2,
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GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
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GPIO1B1_UART1_SOUT = 2,
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GPIO1B2_SHIFT = 4,
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GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
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GPIO1B2_UART1_SIN = 2,
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};
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rk_clrsetreg(&grf->gpio1b_iomux,
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GPIO1B1_MASK | GPIO1B2_MASK,
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GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT |
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GPIO1B2_UART1_SIN << GPIO1B2_SHIFT);
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#elif CONFIG_DEBUG_UART_BASE == 0x20068000
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#if IS_ENABLED(CONFIG_ROCKCHIP_USB_UART)
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enum {
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UTMI_TERMSELECT_SHIFT = 6,
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UTMI_TERMSELECT_MASK = 1 << UTMI_TERMSELECT_SHIFT,
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UTMI_TERM_HS = 0,
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UTMI_TERM_FS,
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UTMI_XCVRSELECT_SHIFT = 4,
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UTMI_XCVRSELECT_MASK = 3 << UTMI_XCVRSELECT_SHIFT,
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UTMI_XCVR_HS = 0,
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UTMI_XCVR_FS,
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UTMI_XCVR_LS,
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UTMI_OPMODE_SHIFT = 2,
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UTMI_OPMODE_MASK = 3 << UTMI_OPMODE_SHIFT,
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UTMI_OPMODE_NORMAL = 0,
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UTMI_OPMODE_NON_DRIVING,
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UTMI_OPMODE_NORMAL_WO_SYNC,
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UTMI_SUSPEND_N_SHIFT = 1,
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UTMI_SUSPEND_N_MASK = 1 << UTMI_SUSPEND_N_SHIFT,
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UTMI_SUSPEND_ENABLE = 0,
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UTMI_SUSPEND_DISABLE,
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USBPHY_SOFT_CON_SEL_SHIFT = 0,
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USBPHY_SOFT_CON_SEL_MASK = 1 << USBPHY_SOFT_CON_SEL_SHIFT,
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USBPHY_SOFT_CON_DISABLE = 1,
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USBPHY_SOFT_CON_ENABLE,
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};
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rk_clrsetreg(&grf->uoc0_con0,
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UTMI_TERMSELECT_MASK | UTMI_OPMODE_MASK |
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UTMI_SUSPEND_N_MASK | USBPHY_SOFT_CON_SEL_MASK,
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UTMI_TERM_FS << UTMI_TERMSELECT_SHIFT |
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UTMI_XCVR_FS << UTMI_XCVRSELECT_SHIFT |
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UTMI_OPMODE_NON_DRIVING << UTMI_OPMODE_SHIFT |
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UTMI_SUSPEND_ENABLE << UTMI_SUSPEND_N_SHIFT |
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USBPHY_SOFT_CON_ENABLE << USBPHY_SOFT_CON_SEL_SHIFT);
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enum {
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BYPASSSEL0_SHIFT = 13,
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BYPASSSEL0_MASK = 1 << BYPASSSEL0_SHIFT,
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BYPASSSEL0_DISABLE = 0,
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BYPASSSEL0_ENABLE = 1,
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BYPASSDMEN0_SHIFT = 12,
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BYPASSDMEN0_MASK = 1 << BYPASSDMEN0_SHIFT,
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BYPASSDMEN0_DISABLE = 0,
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BYPASSDMEN0_ENABLE,
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OTGPHYDISABLE_SHIFT = 10,
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OTGPHYDISABLE_MASK = 1 << OTGPHYDISABLE_SHIFT,
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OTGPHY_ENABLE = 0,
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OTGPHY_DISABLE,
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};
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rk_clrsetreg(&grf->uoc1_con4,
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BYPASSSEL0_MASK | BYPASSDMEN0_MASK |
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OTGPHYDISABLE_MASK,
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BYPASSSEL0_ENABLE << BYPASSSEL0_SHIFT |
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BYPASSDMEN0_ENABLE << BYPASSDMEN0_SHIFT |
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OTGPHY_DISABLE << OTGPHYDISABLE_SHIFT);
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#else
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enum {
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GPIO1C2_SHIFT = 4,
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GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
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GPIO1C2_UART2_TX = 2,
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GPIO1C3_SHIFT = 6,
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GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
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GPIO1C3_UART2_RX = 2,
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};
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rk_clrsetreg(&grf->gpio1c_iomux,
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GPIO1C3_MASK | GPIO1C2_MASK,
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GPIO1C2_UART2_TX << GPIO1C2_SHIFT |
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GPIO1C3_UART2_RX << GPIO1C3_SHIFT);
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#endif //IS_ENABLED(CONFIG_ROCKCHIP_USB_UART)
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#endif
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}
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#endif //IS_ENABLED(CONFIG_DEBUG_UART_BOARD_INIT) && defined(CONFIG_DEBUG_UART_BASE)
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#if !IS_ENABLED(CONFIG_TPL_BUILD)
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int arch_cpu_init(void)
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{
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#if IS_ENABLED(CONFIG_SPL_BUILD)
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#if IS_ENABLED(CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG)
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struct rk3128_grf * const grf = (void *)GRF_BASE;
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/* don't force jtag on sdmmc/uart2 iomux */
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rk_clrreg(&grf->soc_con0, BIT(8));
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#endif
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#endif
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return 0;
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}
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#endif