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Merge tag 'xilinx-for-v2025.01-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

AMD/Xilinx changes for v2025.01-rc1 v2

.mailmap:
- Switch Padmarao's email to AMD one

zynq_spi:
- Make update_stripe static

xilinx:
- Update DT description for EMMCs

zynqmp:
- Update logic around RPUs and tcm handling
- Update bootmenu selection for Kria
- Add description for SC vm-p-b1369
- Fix comment about file location in zynqmp-p-a2197-00-revA.dts

versal:
- Fix logic around USB boot

versal2:
- Disable useless features for Mini configurations

versal-net:
- Get rid of current-speed DT property from mini configuration

microblaze:
- Fix scriptaddr location

# -----BEGIN PGP SIGNATURE-----
#
# iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCZxuweAAKCRDKSWXLKUoM
# IY1iAKCH/GKJHEXFfLvr0OGuO6c1SX9+ZQCfTjRAHrL186X6LUgjOpmtmsrVK1c=
# =4gY0
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 25 Oct 2024 08:51:36 AM CST
# gpg: using DSA key 1B3CD4CCBD79989413D1C31ECA4965CB294A0C21
# gpg: Good signature from "Michal Simek <monstr@monstr.eu>" [full]
# gpg: aka "Michal Simek (Xilinx) <michals@xilinx.com>" [full]
# gpg: aka "Michal Simek (Xilinx) <michal.simek@xilinx.com>" [full]
# gpg: aka "Michal Simek (AMD) <michal.simek@amd.com>" [unknown]

Tom Rini 3fbc6576 e8a45b50

+551 -45
+1
.mailmap
··· 89 89 Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de> 90 90 This contributor prefers not to receive mails <noreply@example.com> <pali@kernel.org> 91 91 This contributor prefers not to receive mails <noreply@example.com> <pali.rohar@gmail.com> 92 + Padmarao Begari <padmarao.begari@amd.com> <padmarao.begari@microchip.com> 92 93 Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com> 93 94 Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com> 94 95 Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
+2
arch/arm/dts/Makefile
··· 327 327 zynqmp-sc-vpk180-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revA.dtbo 328 328 zynqmp-sc-vpk180-revB-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revB.dtbo 329 329 zynqmp-sc-vn-p-b2197-00-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vn-p-b2197-00-revA.dtbo 330 + zynqmp-sc-vm-p-b1369-00-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vm-p-m1369-00-revA.dtbo 330 331 331 332 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revA.dtb 332 333 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revB.dtb ··· 335 336 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revA.dtb 336 337 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revB.dtb 337 338 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vn-p-b2197-00-revA.dtb 339 + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vm-p-b1369-00-revA.dtb 338 340 339 341 zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo 340 342 zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
+3
arch/arm/dts/versal-mini-emmc0.dts
··· 40 40 status = "okay"; 41 41 non-removable; 42 42 disable-wp; 43 + no-sd; 44 + no-sdio; 45 + cap-mmc-hw-reset; 43 46 bus-width = <8>; 44 47 reg = <0x0 0xf1040000 0x0 0x10000>; 45 48 clock-names = "clk_xin", "clk_ahb";
+3
arch/arm/dts/versal-mini-emmc1.dts
··· 40 40 status = "okay"; 41 41 non-removable; 42 42 disable-wp; 43 + no-sd; 44 + no-sdio; 45 + cap-mmc-hw-reset; 43 46 bus-width = <8>; 44 47 reg = <0x0 0xf1050000 0x0 0x10000>; 45 48 clock-names = "clk_xin", "clk_ahb";
+3
arch/arm/dts/versal-net-mini-emmc.dts
··· 54 54 status = "okay"; 55 55 non-removable; 56 56 disable-wp; 57 + no-sd; 58 + no-sdio; 59 + cap-mmc-hw-reset; 57 60 bus-width = <8>; 58 61 reg = <0 0xf1050000 0 0x10000>; 59 62 clock-names = "clk_xin", "clk_ahb";
-1
arch/arm/dts/versal-net-mini.dts
··· 60 60 clock-names = "uartclk", "apb_pclk"; 61 61 clocks = <&clk1>, <&clk1>; 62 62 clock = <1000000>; 63 - current-speed = <115200>; 64 63 skip-init; 65 64 }; 66 65 };
+3
arch/arm/dts/zynq-dlc20-rev1.0.dts
··· 83 83 bootph-all; 84 84 status = "okay"; /* EMMC MTFC4GACAJCN - MIO40-MIO45 */ 85 85 non-removable; 86 + no-sd; 87 + no-sdio; 88 + cap-mmc-hw-reset; 86 89 bus-width = <4>; 87 90 }; 88 91
+3
arch/arm/dts/zynq-minized.dts
··· 92 92 &sdhci1 { 93 93 status = "okay"; 94 94 non-removable; 95 + no-sd; 96 + no-sdio; 97 + cap-mmc-hw-reset; 95 98 bus-width = <4>; 96 99 max-frequency = <12000000>; 97 100
+3
arch/arm/dts/zynqmp-dlc21-revA.dts
··· 60 60 status = "okay"; 61 61 non-removable; 62 62 disable-wp; 63 + no-sd; 64 + no-sdio; 65 + cap-mmc-hw-reset; 63 66 bus-width = <8>; 64 67 xlnx,mio-bank = <0>; 65 68 };
+3
arch/arm/dts/zynqmp-g-a2197-00-revA.dts
··· 68 68 status = "okay"; 69 69 non-removable; 70 70 disable-wp; 71 + no-sd; 72 + no-sdio; 73 + cap-mmc-hw-reset; 71 74 bus-width = <8>; 72 75 xlnx,mio-bank = <0>; 73 76 };
+3
arch/arm/dts/zynqmp-m-a2197-01-revA.dts
··· 88 88 status = "okay"; 89 89 non-removable; 90 90 disable-wp; 91 + no-sd; 92 + no-sdio; 93 + cap-mmc-hw-reset; 91 94 bus-width = <8>; 92 95 xlnx,mio-bank = <0>; /* FIXME tap delay */ 93 96 };
+3
arch/arm/dts/zynqmp-m-a2197-02-revA.dts
··· 84 84 status = "okay"; 85 85 non-removable; 86 86 disable-wp; 87 + no-sd; 88 + no-sdio; 89 + cap-mmc-hw-reset; 87 90 bus-width = <8>; 88 91 xlnx,mio-bank = <0>; /* FIXME tap delay */ 89 92 };
+3
arch/arm/dts/zynqmp-m-a2197-03-revA.dts
··· 84 84 status = "okay"; 85 85 non-removable; 86 86 disable-wp; 87 + no-sd; 88 + no-sdio; 89 + cap-mmc-hw-reset; 87 90 bus-width = <8>; 88 91 xlnx,mio-bank = <0>; /* FIXME tap delay */ 89 92 };
+3
arch/arm/dts/zynqmp-mini-emmc0.dts
··· 52 52 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 53 53 status = "disabled"; 54 54 non-removable; 55 + no-sd; 56 + no-sdio; 57 + cap-mmc-hw-reset; 55 58 bus-width = <8>; 56 59 reg = <0x0 0xff160000 0x0 0x1000>; 57 60 clock-names = "clk_xin", "clk_ahb";
+3
arch/arm/dts/zynqmp-mini-emmc1.dts
··· 52 52 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 53 53 status = "disabled"; 54 54 non-removable; 55 + no-sd; 56 + no-sdio; 57 + cap-mmc-hw-reset; 55 58 bus-width = <8>; 56 59 reg = <0x0 0xff170000 0x0 0x1000>; 57 60 clock-names = "clk_xin", "clk_ahb";
+25 -22
arch/arm/dts/zynqmp-p-a2197-00-revA.dts
··· 60 60 status = "okay"; 61 61 non-removable; 62 62 disable-wp; 63 + no-sd; 64 + no-sdio; 65 + cap-mmc-hw-reset; 63 66 bus-width = <8>; 64 67 xlnx,mio-bank = <0>; 65 68 }; ··· 155 158 reg = <0>; 156 159 /* On connector J98 */ 157 160 reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ 158 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 161 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 159 162 reg = <0x7>; 160 163 regulator-name = "reg_vcc_fmc"; 161 164 regulator-min-microvolt = <1800000>; ··· 163 166 /* enable-gpio = <&gpio0 23 0x4>; optional */ 164 167 }; 165 168 reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ 166 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 169 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 167 170 reg = <0x8>; 168 171 }; 169 172 reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ 170 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 173 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 171 174 reg = <0x9>; 172 175 }; 173 176 reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ 174 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 177 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 175 178 reg = <0xa>; 176 179 }; 177 180 reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ ··· 212 215 reg = <2>; 213 216 /* On connector J104 */ 214 217 reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ 215 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 218 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 216 219 reg = <0xd>; 217 220 }; 218 221 reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ 219 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 222 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 220 223 reg = <0xe>; 221 224 }; 222 225 reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ 223 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 226 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 224 227 reg = <0xf>; 225 228 }; 226 229 reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ 227 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 230 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 228 231 reg = <0x10>; 229 232 }; 230 233 reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ 231 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 234 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 232 235 reg = <0x11>; 233 236 }; 234 237 reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ 235 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 238 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 236 239 reg = <0x12>; 237 240 }; 238 241 reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ 239 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 242 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 240 243 reg = <0x13>; 241 244 }; 242 245 reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ 243 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 246 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 244 247 reg = <0x14>; 245 248 }; 246 249 reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ 247 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 250 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 248 251 reg = <0x15>; 249 252 }; 250 253 reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ 251 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 254 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 252 255 reg = <0x16>; 253 256 }; 254 257 reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ 255 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 258 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 256 259 reg = <0x17>; 257 260 }; 258 261 reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ 259 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 262 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 260 263 reg = <0x19>; 261 264 }; 262 265 reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ 263 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 266 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 264 267 reg = <0x1a>; 265 268 }; 266 269 reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ 267 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 270 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 268 271 reg = <0x1b>; 269 272 }; 270 273 reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ 271 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 274 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 272 275 reg = <0x1c>; 273 276 }; 274 277 reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ 275 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 278 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 276 279 reg = <0x1d>; 277 280 }; 278 281 reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ 279 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 282 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 280 283 reg = <0x1e>; 281 284 }; 282 285 reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ 283 - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ 286 + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ 284 287 reg = <0x1f>; 285 288 }; 286 289 };
+3
arch/arm/dts/zynqmp-sc-revB.dts
··· 288 288 status = "okay"; 289 289 non-removable; 290 290 disable-wp; 291 + no-sd; 292 + no-sdio; 293 + cap-mmc-hw-reset; 291 294 bus-width = <8>; 292 295 xlnx,mio-bank = <0>; 293 296 };
+400
arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * dts file for Xilinx ZynqMP VM-P-M1369-00 4 + * 5 + * Copyright (C) 2024, Advanced Micro Devices, Inc. 6 + * 7 + * Michal Simek <michal.simek@amd.com> 8 + */ 9 + 10 + #include <dt-bindings/gpio/gpio.h> 11 + 12 + /dts-v1/; 13 + /plugin/; 14 + 15 + &{/} { 16 + compatible = "xlnx,zynqmp-sc-vm-p-m1369-revA", 17 + "xlnx,zynqmp-sc-vm-p-m1369", "xlnx,zynqmp"; 18 + 19 + ina226-u19 { 20 + compatible = "iio-hwmon"; 21 + io-channels = <&vcc_soc_ina 0>, <&vcc_soc_ina 1>, <&vcc_soc_ina 2>; 22 + }; 23 + ina226-u287 { 24 + compatible = "iio-hwmon"; 25 + io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>; 26 + }; 27 + ina226-u288 { 28 + compatible = "iio-hwmon"; 29 + io-channels = <&vcc_pslp_ina 0>, <&vcc_pslp_ina 1>, <&vcc_pslp_ina 2>; 30 + }; 31 + ina226-u289 { 32 + compatible = "iio-hwmon"; 33 + io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>; 34 + }; 35 + ina226-u290 { 36 + compatible = "iio-hwmon"; 37 + io-channels = <&vccaux_pmc_ina 0>, <&vccaux_pmc_ina 1>, <&vccaux_pmc_ina 2>; 38 + }; 39 + ina226-u291 { 40 + compatible = "iio-hwmon"; 41 + io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>; 42 + }; 43 + ina226-u292 { 44 + compatible = "iio-hwmon"; 45 + io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>; 46 + }; 47 + ina226-u293 { 48 + compatible = "iio-hwmon"; 49 + io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>; 50 + }; 51 + ina226-u294 { 52 + compatible = "iio-hwmon"; 53 + io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>; 54 + }; 55 + ina226-u295 { 56 + compatible = "iio-hwmon"; 57 + io-channels = <&vcc_ddr5_rdimm_ina 0>, <&vcc_ddr5_rdimm_ina 1>, <&vcc_ddr5_rdimm_ina 2>; 58 + }; 59 + ina226-u298 { 60 + compatible = "iio-hwmon"; 61 + io-channels = <&lp5_1v0_ina 0>, <&lp5_1v0_ina 1>, <&lp5_1v0_ina 2>; 62 + }; 63 + ina226-u296 { 64 + compatible = "iio-hwmon"; 65 + io-channels = <&vcc_fmc_ina 0>, <&vcc_fmc_ina 1>, <&vcc_fmc_ina 2>; 66 + }; 67 + ina226-u299 { 68 + compatible = "iio-hwmon"; 69 + io-channels = <&gtm_avcc_ina 0>, <&gtm_avcc_ina 1>, <&gtm_avcc_ina 2>; 70 + }; 71 + ina226-u300 { 72 + compatible = "iio-hwmon"; 73 + io-channels = <&gtm_avtt_ina 0>, <&gtm_avtt_ina 1>, <&gtm_avtt_ina 2>; 74 + }; 75 + ina226-u301 { 76 + compatible = "iio-hwmon"; 77 + io-channels = <&gtm_avccaux_ina 0>, <&gtm_avccaux_ina 1>, <&gtm_avccaux_ina 2>; 78 + }; 79 + ina226-u297 { 80 + compatible = "iio-hwmon"; 81 + io-channels = <&vcc_mipi_ina 0>, <&vcc_mipi_ina 1>, <&vcc_mipi_ina 2>; 82 + }; 83 + }; 84 + 85 + &i2c1 { /* i2c_main bus */ 86 + #address-cells = <1>; 87 + #size-cells = <0>; 88 + 89 + /* u97 eeprom at 0x54 described in sc-revB - WP protection via BOARD_EEPROM_WP - J1801 */ 90 + 91 + /* i2c_main_1 - u72 - j108 - disable translation, add 8 */ 92 + /* J133 - OE for u91@55 + 8 - 161,132813MHz - QSFP56G_0 */ 93 + qsfp56g_0_clk: clock-controller@5d { 94 + compatible = "renesas,proxo-xp"; 95 + reg = <0x5d>; 96 + #clock-cells = <0>; 97 + clock-output-names = "qsfp56g_0_clk"; 98 + }; 99 + 100 + /* J134 - OE for u92@57 + 8 - 322,265625MHz - QSFP56G_1 */ 101 + qsfp56g_1_clk: clock-controller@5f { 102 + compatible = "renesas,proxo-xp"; 103 + reg = <0x5f>; 104 + #clock-cells = <0>; 105 + clock-output-names = "qsfp56g_1_clk"; 106 + }; 107 + 108 + /* i2c_main_2 - u74 - j110 - disable translation, add 9 */ 109 + /* J210 - OE for u164@50 + 9 - 320MHz - CH2_LP5 */ 110 + ch2_lpddr5_refclk: clock-controller@59 { 111 + compatible = "renesas,proxo-xp"; 112 + reg = <0x59>; 113 + #clock-cells = <0>; 114 + clock-output-names = "ch2_lpddr5_refclk"; 115 + }; 116 + 117 + /* i2c_main_3 - u76 - j112 - disable translation, add 6 */ 118 + /* J231 - OE for u165@50 + 6 - 320MHz - _RDIMM */ 119 + ddr5_dimm1_refclk: clock-controller@56 { 120 + compatible = "renesas,proxo-xp"; 121 + reg = <0x56>; 122 + #clock-cells = <0>; 123 + clock-output-names = "ddr5_udimm_refclk"; 124 + }; 125 + 126 + /* i2c_main_4 - u73 - j109 - disable translation, add 5 */ 127 + /* J117 - OE for u82@50 + 5 - 33,3333MHz - PS_REFCLK */ 128 + ps_refclk: clock-controller@55 { 129 + compatible = "renesas,proxo-xp"; 130 + reg = <0x55>; 131 + #clock-cells = <0>; 132 + clock-output-names = "ps_refclk"; 133 + }; 134 + 135 + /* J71 - selection to LP_I2C_SCL_J or LP_I2C_PMC_SCL_J */ 136 + /* J70 - selection to LP_I2C_SDA_J or LP_I2C_PMC_SDA_J */ 137 + /* this should be SW controlable too */ 138 + }; 139 + 140 + &i2c0 { 141 + #address-cells = <1>; 142 + #size-cells = <0>; 143 + 144 + /* u134 tps544b25 but connected to J178 connector */ 145 + /* u48/IMx3112/0x77 - 1:2 multiplexer - also accessed from Versal NET */ 146 + /* Connection DDR5_UDIMM - SPD can be from 0x50-0x57 */ 147 + /* FIXME gpio should handle SYSCTLR_PMBUS_ALERT and also INA226_PMBUS_ALERT */ 148 + /* Access to i2c_pmc bus via u49 with OE j100 or via SYSCTLR_I2C_PMC_EN */ 149 + 150 + /* ina226_pmbus - J103 - disable INA226_PMBUS */ 151 + vcc_soc_ina: power-monitor@40 { /* u19 */ 152 + compatible = "ti,ina226"; 153 + #io-channel-cells = <1>; 154 + reg = <0x40>; 155 + shunt-resistor = <1000>; /* R222 */ 156 + }; 157 + 158 + vcc_ram_ina: power-monitor@41 { /* u287 */ 159 + compatible = "ti,ina226"; 160 + #io-channel-cells = <1>; 161 + reg = <0x41>; 162 + shunt-resistor = <1000>; /* R32981 */ 163 + }; 164 + 165 + vcc_pslp_ina: power-monitor@42 { /* u288 */ 166 + compatible = "ti,ina226"; 167 + #io-channel-cells = <1>; 168 + reg = <0x42>; 169 + shunt-resistor = <1000>; /* R32984 */ 170 + }; 171 + 172 + vccaux_ina: power-monitor@43 { /* u289 */ 173 + compatible = "ti,ina226"; 174 + #io-channel-cells = <1>; 175 + reg = <0x43>; 176 + shunt-resistor = <1000>; /* R32987 */ 177 + }; 178 + 179 + vccaux_pmc_ina: power-monitor@44 { /* u290 */ 180 + compatible = "ti,ina226"; 181 + #io-channel-cells = <1>; 182 + reg = <0x44>; 183 + shunt-resistor = <1000>; /* R32990 */ 184 + }; 185 + 186 + vcco_500_ina: power-monitor@45 { /* u291 */ 187 + compatible = "ti,ina226"; 188 + #io-channel-cells = <1>; 189 + reg = <0x45>; 190 + shunt-resistor = <1000>; /* R32993 */ 191 + }; 192 + 193 + vcco_501_ina: power-monitor@46 { /* u292 */ 194 + compatible = "ti,ina226"; 195 + #io-channel-cells = <1>; 196 + reg = <0x46>; 197 + shunt-resistor = <1000>; /* R32996 */ 198 + }; 199 + 200 + vcco_502_ina: power-monitor@47 { /* u293 */ 201 + compatible = "ti,ina226"; 202 + #io-channel-cells = <1>; 203 + reg = <0x47>; 204 + shunt-resistor = <1000>; /* R32999 */ 205 + }; 206 + 207 + vcco_503_ina: power-monitor@48 { /* u294 */ 208 + compatible = "ti,ina226"; 209 + #io-channel-cells = <1>; 210 + reg = <0x48>; 211 + shunt-resistor = <1000>; /* R33002 */ 212 + }; 213 + 214 + vcc_ddr5_rdimm_ina: power-monitor@49 { /* u295 */ 215 + compatible = "ti,ina226"; 216 + #io-channel-cells = <1>; 217 + reg = <0x49>; 218 + shunt-resistor = <1000>; /* R33005 */ 219 + }; 220 + 221 + lp5_1v0_ina: power-monitor@4a { /* u298 */ 222 + compatible = "ti,ina226"; 223 + #io-channel-cells = <1>; 224 + reg = <0x4a>; 225 + shunt-resistor = <1000>; /* R33014 */ 226 + }; 227 + 228 + vcc_fmc_ina: power-monitor@4b { /* u296 */ 229 + compatible = "ti,ina226"; 230 + #io-channel-cells = <1>; 231 + reg = <0x4b>; 232 + shunt-resistor = <1000>; /* R33008 */ 233 + }; 234 + 235 + gtm_avcc_ina: power-monitor@4c { /* u299 */ 236 + compatible = "ti,ina226"; 237 + #io-channel-cells = <1>; 238 + reg = <0x4c>; 239 + shunt-resistor = <1000>; /* R33017 */ 240 + }; 241 + 242 + gtm_avtt_ina: power-monitor@4d { /* u300 */ 243 + compatible = "ti,ina226"; 244 + #io-channel-cells = <1>; 245 + reg = <0x4d>; 246 + shunt-resistor = <1000>; /* R33020 */ 247 + }; 248 + 249 + gtm_avccaux_ina: power-monitor@4e { /* u301 */ 250 + compatible = "ti,ina226"; 251 + #io-channel-cells = <1>; 252 + reg = <0x4e>; 253 + shunt-resistor = <1000>; /* R33023 */ 254 + }; 255 + 256 + vcc_mipi_ina: power-monitor@4f { /* u297 */ 257 + compatible = "ti,ina226"; 258 + #io-channel-cells = <1>; 259 + reg = <0x4f>; 260 + shunt-resistor = <1000>; /* R33011 */ 261 + }; 262 + 263 + /* pmbus - j105 - disable main PMBUS - also going to j102 connector */ 264 + vcc_pslp: regulator@15 { /* u24 */ 265 + compatible = "ti,tps546b24a"; 266 + reg = <0x15>; 267 + }; 268 + 269 + vccaux_pmc: regulator@17 { /* u26 */ 270 + compatible = "ti,tps546b24a"; 271 + reg = <0x17>; 272 + }; 273 + 274 + vcco_500: regulator@18 { /* u27 */ 275 + compatible = "ti,tps546b24a"; 276 + reg = <0x18>; 277 + }; 278 + 279 + vcco_501: regulator@19 { /* u28 */ 280 + compatible = "ti,tps546b24a"; 281 + reg = <0x19>; 282 + }; 283 + 284 + vcco_502: regulator@1a { /* u29 */ 285 + compatible = "ti,tps546b24a"; 286 + reg = <0x1a>; 287 + }; 288 + 289 + vcco_503: regulator@1b { /* u30 */ 290 + compatible = "ti,tps546b24a"; 291 + reg = <0x1b>; 292 + }; 293 + 294 + vcc_ddr5_rdimm: regulator@1c { /* u31 */ 295 + compatible = "ti,tps546b24a"; 296 + reg = <0x1c>; 297 + }; 298 + 299 + gtm_avcc: regulator@22 { /* u37 */ 300 + compatible = "ti,tps546b24a"; 301 + reg = <0x22>; 302 + }; 303 + 304 + gtm_avtt: regulator@20 { /* u38 */ 305 + compatible = "ti,tps546b24a"; 306 + reg = <0x20>; 307 + }; 308 + 309 + gtm_avccaux: regulator@21 { /* u39 */ 310 + compatible = "ti,tps546b24a"; 311 + reg = <0x21>; 312 + }; 313 + 314 + vccint_gt: regulator@2a { /* u44 */ 315 + compatible = "ti,tps546b24a"; 316 + reg = <0x2a>; 317 + }; 318 + 319 + util_1v8: regulator@2b { /* u1839 */ 320 + compatible = "ti,tps546b24a"; 321 + reg = <0x2b>; 322 + }; 323 + 324 + vcc_pmc: regulator@2c { /* u46 */ 325 + compatible = "ti,tps546b24a"; 326 + reg = <0x2c>; 327 + }; 328 + 329 + /* pmbus via U62 as ext_pmbus - disable via j104 */ 330 + vccint: regulator@10 { /* u18 */ 331 + compatible = "ti,tps546b24"; 332 + reg = <0x10>; 333 + }; 334 + 335 + vccsoc: regulator@11 { /* u20 */ 336 + compatible = "ti,tps546b24"; 337 + reg = <0x11>; 338 + }; 339 + 340 + vcc_io: regulator@12 { /* u21 */ 341 + compatible = "ti,tps546b24"; 342 + reg = <0x12>; 343 + }; 344 + 345 + vcc_psfp: regulator@13 { /* u22 */ 346 + compatible = "ti,tps546b24"; 347 + reg = <0x13>; 348 + }; 349 + 350 + vcc_ram: regulator@14 { /* u23 */ 351 + compatible = "ti,tps546b24"; 352 + reg = <0x14>; 353 + }; 354 + 355 + vccaux: regulator@16 { /* u25 */ 356 + compatible = "ti,tps546b24"; 357 + reg = <0x16>; 358 + }; 359 + 360 + lp5_1v0: regulator@1d { /* u32 */ 361 + compatible = "ti,tps546b24"; 362 + reg = <0x1d>; 363 + }; 364 + 365 + vcc_fmc: regulator@1e { /* u33 */ 366 + compatible = "ti,tps546b24"; 367 + reg = <0x1e>; 368 + }; 369 + 370 + lp5_vdd1: regulator@25 { /* u40 */ 371 + compatible = "ti,tps546b24"; 372 + reg = <0x25>; 373 + }; 374 + 375 + lp5_vdd2: regulator@26 { /* u41 */ 376 + compatible = "ti,tps546b24"; 377 + reg = <0x26>; 378 + }; 379 + 380 + lp5_vddq: regulator@27 { /* u42 */ 381 + compatible = "ti,tps546b24"; 382 + reg = <0x27>; 383 + }; 384 + 385 + vcco_hdio: regulator@29 { /* u43 */ 386 + compatible = "ti,tps546b24"; 387 + reg = <0x29>; 388 + }; 389 + 390 + vcc_mipi: regulator@1f { /* u47 */ 391 + compatible = "ti,tps546b24"; 392 + reg = <0x1f>; 393 + }; 394 + 395 + /* connected via J425 connector 396 + ucd90320: power-sequencer@73 { // u16 397 + compatible = "ti,ucd90320"; 398 + reg = <0x73>; 399 + };*/ 400 + };
+3
arch/arm/dts/zynqmp-sm-k26-revA.dts
··· 247 247 pinctrl-0 = <&pinctrl_sdhci0_default>; 248 248 non-removable; 249 249 disable-wp; 250 + no-sd; 251 + no-sdio; 252 + cap-mmc-hw-reset; 250 253 bus-width = <8>; 251 254 xlnx,mio-bank = <0>; 252 255 assigned-clock-rates = <187498123>;
+3
arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
··· 93 93 status = "okay"; 94 94 non-removable; 95 95 disable-wp; /* We don't have a write-protect detection */ 96 + no-sd; 97 + no-sdio; 98 + cap-mmc-hw-reset; 96 99 bus-width = <8>; 97 100 xlnx,mio-bank = <0>; 98 101 };
+3
arch/arm/dts/zynqmp-vpk120-revA.dts
··· 105 105 status = "okay"; 106 106 non-removable; 107 107 disable-wp; 108 + no-sd; 109 + no-sdio; 110 + cap-mmc-hw-reset; 108 111 bus-width = <8>; 109 112 xlnx,mio-bank = <0>; 110 113 };
+3
arch/arm/dts/zynqmp-zcu100-revC.dts
··· 509 509 xlnx,mio-bank = <0>; 510 510 non-removable; 511 511 disable-wp; 512 + no-sd; 513 + no-sdio; 514 + cap-mmc-hw-reset; 512 515 cap-power-off-card; 513 516 mmc-pwrseq = <&sdio_pwrseq>; 514 517 vqmmc-supply = <&wmmcsdio_fixed>;
+18 -5
arch/arm/mach-zynqmp/cpu.c
··· 112 112 return 0x14000; 113 113 } 114 114 115 - #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) 115 + #if defined(CONFIG_DEFINE_TCM_OCM_MMAP) 116 116 void tcm_init(u8 mode) 117 117 { 118 - puts("WARNING: Initializing TCM overwrites TCM content\n"); 119 - initialize_tcm(mode); 120 - memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); 118 + int ret; 119 + 120 + ret = check_tcm_mode(mode); 121 + if (!ret) { 122 + puts("WARNING: Initializing TCM overwrites TCM content\n"); 123 + initialize_tcm(mode); 124 + memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); 125 + } 126 + 127 + if (ret == -EACCES) 128 + printf("ERROR: Split to lockstep mode required reset/disable cpu\n"); 129 + 130 + /* Ignore if ret is -EAGAIN, trying to initialize same mode again */ 121 131 } 122 132 #endif 123 133 124 134 #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU 125 135 int arm_reserve_mmu(void) 126 136 { 127 - tcm_init(TCM_LOCK); 137 + puts("WARNING: Initializing TCM overwrites TCM content\n"); 138 + initialize_tcm(TCM_LOCK); 139 + memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); 140 + 128 141 gd->arch.tlb_size = PGTABLE_SIZE; 129 142 gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR; 130 143
+2 -1
arch/arm/mach-zynqmp/include/mach/sys_proto.h
··· 48 48 49 49 unsigned int zynqmp_get_silicon_version(void); 50 50 51 + int check_tcm_mode(bool mode); 51 52 void initialize_tcm(bool mode); 52 53 void mem_map_fill(void); 53 - #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) 54 + #if defined(CONFIG_DEFINE_TCM_OCM_MMAP) 54 55 void tcm_init(u8 mode); 55 56 #endif 56 57
+24
arch/arm/mach-zynqmp/mp.c
··· 12 12 #include <asm/arch/hardware.h> 13 13 #include <asm/arch/sys_proto.h> 14 14 #include <asm/io.h> 15 + #include <linux/bitfield.h> 15 16 #include <linux/delay.h> 17 + #include <linux/errno.h> 16 18 #include <linux/string.h> 17 19 18 20 #define LOCK 0 ··· 262 264 release_r5_reset(ZYNQMP_CORE_RPU0, SPLIT); 263 265 release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT); 264 266 } 267 + } 268 + 269 + int check_tcm_mode(bool mode) 270 + { 271 + u32 tmp, cpu_state; 272 + bool mode_prev; 273 + 274 + tmp = readl(&rpu_base->rpu_glbl_ctrl); 275 + mode_prev = FIELD_GET(ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK, tmp); 276 + 277 + tmp = readl(&crlapb_base->rst_lpd_top); 278 + cpu_state = FIELD_GET(ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK | 279 + ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK, tmp); 280 + cpu_state = cpu_state ? false : true; 281 + 282 + if ((mode_prev == SPLIT && mode == LOCK) && cpu_state) 283 + return -EACCES; 284 + 285 + if (mode_prev == mode) 286 + return -EAGAIN; 287 + 288 + return 0; 265 289 } 266 290 267 291 static void mark_r5_used(u32 nr, u8 mode)
+7 -9
arch/arm/mach-zynqmp/zynqmp.c
··· 151 151 if (argc != cmdtp->maxargs) 152 152 return CMD_RET_USAGE; 153 153 154 - if (strcmp(argv[2], "lockstep") && strcmp(argv[2], "split")) { 155 - printf("mode param should be lockstep or split\n"); 156 - return CMD_RET_FAILURE; 157 - } 158 - 159 - mode = hextoul(argv[2], NULL); 160 - if (mode != TCM_LOCK && mode != TCM_SPLIT) { 161 - printf("Mode should be either 0(lock)/1(split)\n"); 154 + if (!strcmp(argv[2], "lockstep") || !strcmp(argv[2], "0")) { 155 + mode = TCM_LOCK; 156 + } else if (!strcmp(argv[2], "split") || !strcmp(argv[2], "1")) { 157 + mode = TCM_SPLIT; 158 + } else { 159 + printf("Mode should be either lockstep/split\n"); 162 160 return CMD_RET_FAILURE; 163 161 } 164 162 ··· 429 427 " initialized before accessing to avoid ECC\n" 430 428 " errors. mode specifies in which mode TCM has\n" 431 429 " to be initialized. Supported modes will be\n" 432 - " lock(0)/split(1)\n" 430 + " lockstep(0)/split(1)\n" 433 431 #endif 434 432 "zynqmp pmufw address size - load PMU FW configuration object\n" 435 433 "zynqmp pmufw node <id> - load PMU FW configuration object, <id> in dec\n"
+1 -1
board/xilinx/microblaze-generic/microblaze-generic.c
··· 57 57 max_size = gd->start_addr_sp - CONFIG_STACK_SIZE; 58 58 max_size = round_down(max_size, SZ_16M); 59 59 60 - status |= env_set_hex("scriptaddr", max_size + SZ_2M); 60 + status |= env_set_hex("scriptaddr", (max_size - gd->ram_base) + SZ_2M); 61 61 62 62 status |= env_set_hex("pxefile_addr_r", max_size + SZ_1M); 63 63
+1 -2
board/xilinx/zynqmp/zynqmp_kria.env
··· 51 51 52 52 # To disable bootmenu set enable_bootmenu=0 53 53 enable_bootmenu=1 54 - check_cc_for_default_boot=if test ${card1_name} = SCK-KV-G || test ${card1_name} = SCK-KR-G || test ${card1_name} = SCK-KD-G; then setenv bootmenu_default 1; else setenv bootmenu_default 0; fi 55 - som_bootmenu=if test ${enable_bootmenu} = 1; then run check_cc_for_default_boot; bootmenu; else run som_mmc_boot; fi 54 + som_bootmenu=if test ${enable_bootmenu} = 1; then bootmenu; else run som_mmc_boot; fi 56 55 57 56 k26_starter=SMK-K26-XCL2G 58 57 k24_starter=SMK-K24-XCL2G
+3
configs/amd_versal2_mini_defconfig
··· 22 22 CONFIG_SYS_MEMTEST_END=0x00001000 23 23 # CONFIG_EXPERT is not set 24 24 CONFIG_REMAKE_ELF=y 25 + # CONFIG_EFI_LOADER is not set 25 26 # CONFIG_LEGACY_IMAGE_FORMAT is not set 26 27 # CONFIG_AUTOBOOT is not set 27 28 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set ··· 35 36 CONFIG_SYS_PROMPT="versal2> " 36 37 # CONFIG_CMD_CONSOLE is not set 37 38 # CONFIG_CMD_BOOTD is not set 39 + # CONFIG_CMD_BOOTM is not set 38 40 # CONFIG_CMD_BOOTI is not set 39 41 # CONFIG_CMD_ELF is not set 40 42 # CONFIG_CMD_FDT is not set ··· 75 77 CONFIG_ARM_DCC=y 76 78 CONFIG_PL01X_SERIAL=y 77 79 # CONFIG_GZIP is not set 80 + # CONFIG_LMB is not set
+3
configs/amd_versal2_mini_ospi_defconfig
··· 20 20 CONFIG_DEBUG_UART=y 21 21 # CONFIG_EXPERT is not set 22 22 CONFIG_REMAKE_ELF=y 23 + # CONFIG_EFI_LOADER is not set 23 24 # CONFIG_LEGACY_IMAGE_FORMAT is not set 24 25 # CONFIG_AUTOBOOT is not set 25 26 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set ··· 33 34 CONFIG_SYS_PROMPT="versal2> " 34 35 # CONFIG_CMD_CONSOLE is not set 35 36 # CONFIG_CMD_BOOTD is not set 37 + # CONFIG_CMD_BOOTM is not set 36 38 # CONFIG_CMD_BOOTI is not set 37 39 # CONFIG_CMD_ELF is not set 38 40 # CONFIG_CMD_FDT is not set ··· 82 84 CONFIG_CQSPI_REF_CLK=200000000 83 85 CONFIG_CADENCE_OSPI_VERSAL=y 84 86 # CONFIG_GZIP is not set 87 + # CONFIG_LMB is not set
+3 -1
configs/amd_versal2_mini_qspi_defconfig
··· 20 20 CONFIG_DEBUG_UART=y 21 21 # CONFIG_EXPERT is not set 22 22 CONFIG_REMAKE_ELF=y 23 + # CONFIG_EFI_LOADER is not set 23 24 # CONFIG_LEGACY_IMAGE_FORMAT is not set 24 25 # CONFIG_AUTOBOOT is not set 25 26 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set ··· 33 34 CONFIG_SYS_PROMPT="versal2> " 34 35 # CONFIG_CMD_CONSOLE is not set 35 36 # CONFIG_CMD_BOOTD is not set 37 + # CONFIG_CMD_BOOTM is not set 36 38 # CONFIG_CMD_BOOTI is not set 37 39 # CONFIG_CMD_ELF is not set 38 40 # CONFIG_CMD_FDT is not set ··· 62 64 # CONFIG_I2C is not set 63 65 # CONFIG_INPUT is not set 64 66 # CONFIG_MMC is not set 65 - CONFIG_MTD=y 66 67 CONFIG_DM_SPI_FLASH=y 67 68 # CONFIG_SPI_FLASH_LOCK is not set 68 69 CONFIG_SPI_FLASH_STMICRO=y ··· 77 78 CONFIG_DM_SPI=y 78 79 CONFIG_ZYNQMP_GQSPI=y 79 80 # CONFIG_GZIP is not set 81 + # CONFIG_LMB is not set
+1 -1
drivers/spi/zynq_qspi.c
··· 734 734 return 0; 735 735 } 736 736 737 - bool update_stripe(const struct spi_mem_op *op) 737 + static bool update_stripe(const struct spi_mem_op *op) 738 738 { 739 739 if (op->cmd.opcode == SPINOR_OP_BE_4K || 740 740 op->cmd.opcode == SPINOR_OP_CHIP_ERASE ||
+9 -2
include/configs/xilinx_versal.h
··· 48 48 # define BOOT_TARGET_DEVICES_MMC(func) 49 49 #endif 50 50 51 + #if defined(CONFIG_USB_STORAGE) 52 + # define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) 53 + #else 54 + # define BOOT_TARGET_DEVICES_USB(func) 55 + #endif 56 + 51 57 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) 52 58 # define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 53 59 #else ··· 85 91 "jtag " 86 92 87 93 #define BOOT_TARGET_DEVICES_USB_DFU(func) \ 88 - func(USB_DFU, usb_dfu, 0) func(USB_DFU, usb_dfu, 1) 94 + func(USB_DFU, usb_dfu, 0) 89 95 90 96 #define BOOTENV_DEV_USB_DFU(devtypeu, devtypel, instance) \ 91 97 "bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \ ··· 99 105 "" 100 106 101 107 #define BOOT_TARGET_DEVICES_USB_THOR(func) \ 102 - func(USB_THOR, usb_thor, 0) func(USB_THOR, usb_thor, 1) 108 + func(USB_THOR, usb_thor, 0) 103 109 104 110 #define BOOTENV_DEV_USB_THOR(devtypeu, devtypel, instance) \ 105 111 "bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \ ··· 118 124 BOOT_TARGET_DEVICES_XSPI(func) \ 119 125 BOOT_TARGET_DEVICES_USB_DFU(func) \ 120 126 BOOT_TARGET_DEVICES_USB_THOR(func) \ 127 + BOOT_TARGET_DEVICES_USB(func) \ 121 128 BOOT_TARGET_DEVICES_PXE(func) \ 122 129 BOOT_TARGET_DEVICES_DHCP(func) 123 130