jcs.org
"Das U-Boot" Source Tree
andes: Unify naming policy for Andes related source
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
+40
-40
+2
-2
arch/riscv/Kconfig
+2
-2
arch/riscv/Kconfig
···
80
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Sifive core devices that uses L2 cache to store SPL.
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# board-specific options below
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-
source "board/AndesTech/ae350/Kconfig"
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+
source "board/andestech/ae350/Kconfig"
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source "board/emulation/qemu-riscv/Kconfig"
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source "board/microchip/mpfs_icicle/Kconfig"
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source "board/openpiton/riscv64/Kconfig"
···
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source "board/xilinx/mbv/Kconfig"
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# platform-specific options below
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-
source "arch/riscv/cpu/andesv5/Kconfig"
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+
source "arch/riscv/cpu/andes/Kconfig"
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source "arch/riscv/cpu/cv1800b/Kconfig"
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source "arch/riscv/cpu/fu540/Kconfig"
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source "arch/riscv/cpu/fu740/Kconfig"
+2
-2
arch/riscv/cpu/andesv5/Kconfig
arch/riscv/cpu/andes/Kconfig
+2
-2
arch/riscv/cpu/andesv5/Kconfig
arch/riscv/cpu/andes/Kconfig
···
1
-
config RISCV_NDS
1
+
config RISCV_ANDES
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bool
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select ARCH_EARLY_INIT_R
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select SYS_CACHE_SHIFT_6
···
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imply ANDES_PLMT_TIMER
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imply SPL_ANDES_PLMT_TIMER
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imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
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-
imply V5L2_CACHE
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+
imply ANDES_L2_CACHE
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imply SPL_CPU
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imply SPL_OPENSBI
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imply SPL_LOAD_FIT
arch/riscv/cpu/andesv5/Makefile
arch/riscv/cpu/andes/Makefile
arch/riscv/cpu/andesv5/Makefile
arch/riscv/cpu/andes/Makefile
+6
-6
arch/riscv/cpu/andesv5/cache.c
arch/riscv/cpu/andes/cache.c
+6
-6
arch/riscv/cpu/andesv5/cache.c
arch/riscv/cpu/andes/cache.c
···
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#include <dm/uclass-internal.h>
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#include <asm/arch-andes/csr.h>
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#ifdef CONFIG_V5L2_CACHE
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#ifdef CONFIG_ANDES_L2_CACHE
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void enable_caches(void)
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{
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struct udevice *dev;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_CACHE,
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DM_DRIVER_GET(v5l2_cache),
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DM_DRIVER_GET(andes_l2_cache),
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&dev);
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if (ret) {
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log_debug("Cannot enable v5l2 cache\n");
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log_debug("Cannot enable Andes L2 cache\n");
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} else {
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ret = cache_enable(dev);
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if (ret)
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log_debug("v5l2 cache enable failed\n");
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log_debug("Failed to enable Andes L2 cache\n");
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}
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}
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···
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asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL));
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#endif
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-
#ifdef CONFIG_V5L2_CACHE
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#ifdef CONFIG_ANDES_L2_CACHE
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cache_ops(cache_enable);
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#endif
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}
···
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asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL));
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#endif
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-
#ifdef CONFIG_V5L2_CACHE
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#ifdef CONFIG_ANDES_L2_CACHE
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cache_ops(cache_disable);
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#endif
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}
arch/riscv/cpu/andesv5/cpu.c
arch/riscv/cpu/andes/cpu.c
arch/riscv/cpu/andesv5/cpu.c
arch/riscv/cpu/andes/cpu.c
arch/riscv/cpu/andesv5/spl.c
arch/riscv/cpu/andes/spl.c
arch/riscv/cpu/andesv5/spl.c
arch/riscv/cpu/andes/spl.c
+3
-3
board/AndesTech/ae350/Kconfig
board/andestech/ae350/Kconfig
+3
-3
board/AndesTech/ae350/Kconfig
board/andestech/ae350/Kconfig
···
1
1
if TARGET_ANDES_AE350
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config SYS_CPU
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default "andesv5"
4
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default "andes"
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config SYS_BOARD
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default "ae350"
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config SYS_VENDOR
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default "AndesTech"
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default "andestech"
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config SYS_SOC
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default "ae350"
···
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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-
select RISCV_NDS
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+
select RISCV_ANDES
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select SUPPORT_SPL
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select BINMAN if SPL
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imply SMP
+1
-1
board/AndesTech/ae350/MAINTAINERS
board/andestech/ae350/MAINTAINERS
+1
-1
board/AndesTech/ae350/MAINTAINERS
board/andestech/ae350/MAINTAINERS
board/AndesTech/ae350/Makefile
board/andestech/ae350/Makefile
board/AndesTech/ae350/Makefile
board/andestech/ae350/Makefile
+1
-1
board/AndesTech/ae350/ae350.c
board/andestech/ae350/ae350.c
+1
-1
board/AndesTech/ae350/ae350.c
board/andestech/ae350/ae350.c
doc/board/AndesTech/adp-ag101p.rst
doc/board/andestech/adp-ag101p.rst
doc/board/AndesTech/adp-ag101p.rst
doc/board/andestech/adp-ag101p.rst
doc/board/AndesTech/ae350.rst
doc/board/andestech/ae350.rst
doc/board/AndesTech/ae350.rst
doc/board/andestech/ae350.rst
doc/board/AndesTech/index.rst
doc/board/andestech/index.rst
doc/board/AndesTech/index.rst
doc/board/andestech/index.rst
+1
-1
doc/board/index.rst
+1
-1
doc/board/index.rst
+3
-3
drivers/cache/Kconfig
+3
-3
drivers/cache/Kconfig
···
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ARMv7(32-bit) devices. The driver configures the cache settings
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found in the device tree.
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-
config V5L2_CACHE
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bool "Andes V5L2 cache driver"
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+
config ANDES_L2_CACHE
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bool "Andes L2 cache driver"
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select CACHE
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help
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Support Andes V5L2 cache controller in AE350 platform.
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Support Andes L2 cache controller in AE350 platform.
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It will configure tag and data ram timing control from the
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device tree and enable L2 cache.
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+1
-1
drivers/cache/Makefile
+1
-1
drivers/cache/Makefile
···
3
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obj-$(CONFIG_SANDBOX) += sandbox_cache.o
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obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
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5
obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
6
-
obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
6
+
obj-$(CONFIG_ANDES_L2_CACHE) += cache-andes-l2.o
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obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
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obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o
+20
-20
drivers/cache/cache-v5l2.c
drivers/cache/cache-andes-l2.c
+20
-20
drivers/cache/cache-v5l2.c
drivers/cache/cache-andes-l2.c
···
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DECLARE_GLOBAL_DATA_PTR;
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-
struct v5l2_plat {
75
+
struct andes_l2_plat {
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struct l2cache *regs;
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u32 iprefetch;
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u32 dprefetch;
···
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u32 dram_ctl[2];
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};
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-
static int v5l2_enable(struct udevice *dev)
83
+
static int andes_l2_enable(struct udevice *dev)
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{
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struct v5l2_plat *plat = dev_get_plat(dev);
85
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struct andes_l2_plat *plat = dev_get_plat(dev);
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volatile struct l2cache *regs = plat->regs;
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if (regs)
···
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return 0;
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}
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-
static int v5l2_disable(struct udevice *dev)
94
+
static int andes_l2_disable(struct udevice *dev)
95
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{
96
-
struct v5l2_plat *plat = dev_get_plat(dev);
96
+
struct andes_l2_plat *plat = dev_get_plat(dev);
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volatile struct l2cache *regs = plat->regs;
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u8 hart = gd->arch.boot_hart;
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void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
···
113
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return 0;
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}
115
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116
-
static int v5l2_of_to_plat(struct udevice *dev)
116
+
static int andes_l2_of_to_plat(struct udevice *dev)
117
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{
118
-
struct v5l2_plat *plat = dev_get_plat(dev);
118
+
struct andes_l2_plat *plat = dev_get_plat(dev);
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struct l2cache *regs;
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regs = dev_read_addr_ptr(dev);
···
137
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return 0;
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}
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-
static int v5l2_probe(struct udevice *dev)
140
+
static int andes_l2_probe(struct udevice *dev)
141
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{
142
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struct v5l2_plat *plat = dev_get_plat(dev);
142
+
struct andes_l2_plat *plat = dev_get_plat(dev);
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struct l2cache *regs = plat->regs;
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u32 cfg_val, ctl_val;
145
145
···
182
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return 0;
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}
184
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-
static const struct udevice_id v5l2_cache_ids[] = {
185
+
static const struct udevice_id andes_l2_cache_ids[] = {
186
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{ .compatible = "cache" },
187
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{}
188
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};
189
189
190
-
static const struct cache_ops v5l2_cache_ops = {
191
-
.enable = v5l2_enable,
192
-
.disable = v5l2_disable,
190
+
static const struct cache_ops andes_l2_cache_ops = {
191
+
.enable = andes_l2_enable,
192
+
.disable = andes_l2_disable,
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};
194
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195
-
U_BOOT_DRIVER(v5l2_cache) = {
196
-
.name = "v5l2_cache",
195
+
U_BOOT_DRIVER(andes_l2_cache) = {
196
+
.name = "andes_l2_cache",
197
197
.id = UCLASS_CACHE,
198
-
.of_match = v5l2_cache_ids,
199
-
.of_to_plat = v5l2_of_to_plat,
200
-
.probe = v5l2_probe,
201
-
.plat_auto = sizeof(struct v5l2_plat),
202
-
.ops = &v5l2_cache_ops,
198
+
.of_match = andes_l2_cache_ids,
199
+
.of_to_plat = andes_l2_of_to_plat,
200
+
.probe = andes_l2_probe,
201
+
.plat_auto = sizeof(struct andes_l2_plat),
202
+
.ops = &andes_l2_cache_ops,
203
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.flags = DM_FLAG_PRE_RELOC,
204
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};