"Das U-Boot" Source Tree

andes: Unify naming policy for Andes related source

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>

+40 -40
+2 -2
arch/riscv/Kconfig
··· 80 80 Sifive core devices that uses L2 cache to store SPL. 81 81 82 82 # board-specific options below 83 - source "board/AndesTech/ae350/Kconfig" 83 + source "board/andestech/ae350/Kconfig" 84 84 source "board/emulation/qemu-riscv/Kconfig" 85 85 source "board/microchip/mpfs_icicle/Kconfig" 86 86 source "board/openpiton/riscv64/Kconfig" ··· 93 93 source "board/xilinx/mbv/Kconfig" 94 94 95 95 # platform-specific options below 96 - source "arch/riscv/cpu/andesv5/Kconfig" 96 + source "arch/riscv/cpu/andes/Kconfig" 97 97 source "arch/riscv/cpu/cv1800b/Kconfig" 98 98 source "arch/riscv/cpu/fu540/Kconfig" 99 99 source "arch/riscv/cpu/fu740/Kconfig"
+2 -2
arch/riscv/cpu/andesv5/Kconfig arch/riscv/cpu/andes/Kconfig
··· 1 - config RISCV_NDS 1 + config RISCV_ANDES 2 2 bool 3 3 select ARCH_EARLY_INIT_R 4 4 select SYS_CACHE_SHIFT_6 ··· 8 8 imply ANDES_PLMT_TIMER 9 9 imply SPL_ANDES_PLMT_TIMER 10 10 imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) 11 - imply V5L2_CACHE 11 + imply ANDES_L2_CACHE 12 12 imply SPL_CPU 13 13 imply SPL_OPENSBI 14 14 imply SPL_LOAD_FIT
arch/riscv/cpu/andesv5/Makefile arch/riscv/cpu/andes/Makefile
+6 -6
arch/riscv/cpu/andesv5/cache.c arch/riscv/cpu/andes/cache.c
··· 12 12 #include <dm/uclass-internal.h> 13 13 #include <asm/arch-andes/csr.h> 14 14 15 - #ifdef CONFIG_V5L2_CACHE 15 + #ifdef CONFIG_ANDES_L2_CACHE 16 16 void enable_caches(void) 17 17 { 18 18 struct udevice *dev; 19 19 int ret; 20 20 21 21 ret = uclass_get_device_by_driver(UCLASS_CACHE, 22 - DM_DRIVER_GET(v5l2_cache), 22 + DM_DRIVER_GET(andes_l2_cache), 23 23 &dev); 24 24 if (ret) { 25 - log_debug("Cannot enable v5l2 cache\n"); 25 + log_debug("Cannot enable Andes L2 cache\n"); 26 26 } else { 27 27 ret = cache_enable(dev); 28 28 if (ret) 29 - log_debug("v5l2 cache enable failed\n"); 29 + log_debug("Failed to enable Andes L2 cache\n"); 30 30 } 31 31 } 32 32 ··· 78 78 asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL)); 79 79 #endif 80 80 81 - #ifdef CONFIG_V5L2_CACHE 81 + #ifdef CONFIG_ANDES_L2_CACHE 82 82 cache_ops(cache_enable); 83 83 #endif 84 84 } ··· 89 89 asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL)); 90 90 #endif 91 91 92 - #ifdef CONFIG_V5L2_CACHE 92 + #ifdef CONFIG_ANDES_L2_CACHE 93 93 cache_ops(cache_disable); 94 94 #endif 95 95 }
arch/riscv/cpu/andesv5/cpu.c arch/riscv/cpu/andes/cpu.c
arch/riscv/cpu/andesv5/spl.c arch/riscv/cpu/andes/spl.c
+3 -3
board/AndesTech/ae350/Kconfig board/andestech/ae350/Kconfig
··· 1 1 if TARGET_ANDES_AE350 2 2 3 3 config SYS_CPU 4 - default "andesv5" 4 + default "andes" 5 5 6 6 config SYS_BOARD 7 7 default "ae350" 8 8 9 9 config SYS_VENDOR 10 - default "AndesTech" 10 + default "andestech" 11 11 12 12 config SYS_SOC 13 13 default "ae350" ··· 33 33 34 34 config BOARD_SPECIFIC_OPTIONS # dummy 35 35 def_bool y 36 - select RISCV_NDS 36 + select RISCV_ANDES 37 37 select SUPPORT_SPL 38 38 select BINMAN if SPL 39 39 imply SMP
+1 -1
board/AndesTech/ae350/MAINTAINERS board/andestech/ae350/MAINTAINERS
··· 1 1 AE350 BOARD 2 2 M: Rick Chen <rick@andestech.com> 3 3 S: Maintained 4 - F: board/AndesTech/ae350/ 4 + F: board/andestech/ae350/ 5 5 F: include/configs/ae350.h 6 6 F: configs/ae350_rv32_defconfig 7 7 F: configs/ae350_rv32_falcon_defconfig
board/AndesTech/ae350/Makefile board/andestech/ae350/Makefile
+1 -1
board/AndesTech/ae350/ae350.c board/andestech/ae350/ae350.c
··· 99 99 #ifdef CONFIG_SPL_BOARD_INIT 100 100 void spl_board_init() 101 101 { 102 - /* enable v5l2 cache */ 102 + /* enable andes-l2 cache */ 103 103 if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) 104 104 enable_caches(); 105 105 }
doc/board/AndesTech/adp-ag101p.rst doc/board/andestech/adp-ag101p.rst
doc/board/AndesTech/ae350.rst doc/board/andestech/ae350.rst
doc/board/AndesTech/index.rst doc/board/andestech/index.rst
+1 -1
doc/board/index.rst
··· 8 8 9 9 actions/index 10 10 advantech/index 11 - AndesTech/index 11 + andestech/index 12 12 allwinner/index 13 13 amlogic/index 14 14 anbernic/index
+3 -3
drivers/cache/Kconfig
··· 22 22 ARMv7(32-bit) devices. The driver configures the cache settings 23 23 found in the device tree. 24 24 25 - config V5L2_CACHE 26 - bool "Andes V5L2 cache driver" 25 + config ANDES_L2_CACHE 26 + bool "Andes L2 cache driver" 27 27 select CACHE 28 28 help 29 - Support Andes V5L2 cache controller in AE350 platform. 29 + Support Andes L2 cache controller in AE350 platform. 30 30 It will configure tag and data ram timing control from the 31 31 device tree and enable L2 cache. 32 32
+1 -1
drivers/cache/Makefile
··· 3 3 obj-$(CONFIG_SANDBOX) += sandbox_cache.o 4 4 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o 5 5 obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o 6 - obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o 6 + obj-$(CONFIG_ANDES_L2_CACHE) += cache-andes-l2.o 7 7 obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o 8 8 obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o
+20 -20
drivers/cache/cache-v5l2.c drivers/cache/cache-andes-l2.c
··· 72 72 73 73 DECLARE_GLOBAL_DATA_PTR; 74 74 75 - struct v5l2_plat { 75 + struct andes_l2_plat { 76 76 struct l2cache *regs; 77 77 u32 iprefetch; 78 78 u32 dprefetch; ··· 80 80 u32 dram_ctl[2]; 81 81 }; 82 82 83 - static int v5l2_enable(struct udevice *dev) 83 + static int andes_l2_enable(struct udevice *dev) 84 84 { 85 - struct v5l2_plat *plat = dev_get_plat(dev); 85 + struct andes_l2_plat *plat = dev_get_plat(dev); 86 86 volatile struct l2cache *regs = plat->regs; 87 87 88 88 if (regs) ··· 91 91 return 0; 92 92 } 93 93 94 - static int v5l2_disable(struct udevice *dev) 94 + static int andes_l2_disable(struct udevice *dev) 95 95 { 96 - struct v5l2_plat *plat = dev_get_plat(dev); 96 + struct andes_l2_plat *plat = dev_get_plat(dev); 97 97 volatile struct l2cache *regs = plat->regs; 98 98 u8 hart = gd->arch.boot_hart; 99 99 void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart); ··· 113 113 return 0; 114 114 } 115 115 116 - static int v5l2_of_to_plat(struct udevice *dev) 116 + static int andes_l2_of_to_plat(struct udevice *dev) 117 117 { 118 - struct v5l2_plat *plat = dev_get_plat(dev); 118 + struct andes_l2_plat *plat = dev_get_plat(dev); 119 119 struct l2cache *regs; 120 120 121 121 regs = dev_read_addr_ptr(dev); ··· 137 137 return 0; 138 138 } 139 139 140 - static int v5l2_probe(struct udevice *dev) 140 + static int andes_l2_probe(struct udevice *dev) 141 141 { 142 - struct v5l2_plat *plat = dev_get_plat(dev); 142 + struct andes_l2_plat *plat = dev_get_plat(dev); 143 143 struct l2cache *regs = plat->regs; 144 144 u32 cfg_val, ctl_val; 145 145 ··· 182 182 return 0; 183 183 } 184 184 185 - static const struct udevice_id v5l2_cache_ids[] = { 185 + static const struct udevice_id andes_l2_cache_ids[] = { 186 186 { .compatible = "cache" }, 187 187 {} 188 188 }; 189 189 190 - static const struct cache_ops v5l2_cache_ops = { 191 - .enable = v5l2_enable, 192 - .disable = v5l2_disable, 190 + static const struct cache_ops andes_l2_cache_ops = { 191 + .enable = andes_l2_enable, 192 + .disable = andes_l2_disable, 193 193 }; 194 194 195 - U_BOOT_DRIVER(v5l2_cache) = { 196 - .name = "v5l2_cache", 195 + U_BOOT_DRIVER(andes_l2_cache) = { 196 + .name = "andes_l2_cache", 197 197 .id = UCLASS_CACHE, 198 - .of_match = v5l2_cache_ids, 199 - .of_to_plat = v5l2_of_to_plat, 200 - .probe = v5l2_probe, 201 - .plat_auto = sizeof(struct v5l2_plat), 202 - .ops = &v5l2_cache_ops, 198 + .of_match = andes_l2_cache_ids, 199 + .of_to_plat = andes_l2_of_to_plat, 200 + .probe = andes_l2_probe, 201 + .plat_auto = sizeof(struct andes_l2_plat), 202 + .ops = &andes_l2_cache_ops, 203 203 .flags = DM_FLAG_PRE_RELOC, 204 204 };