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"Das U-Boot" Source Tree
m68k: Remove CONFIG_FSLDMAFEC
There are no platforms which enable this feature, so remove it.
Signed-off-by: Tom Rini <trini@konsulko.com>
+2
-4841
-151
arch/m68k/include/asm/fsl_mcdmafec.h
-151
arch/m68k/include/asm/fsl_mcdmafec.h
···
1
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/* SPDX-License-Identifier: GPL-2.0+ */
2
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/*
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* fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions
4
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*
5
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7
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*/
8
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9
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#ifndef fsl_mcdmafec_h
10
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#define fsl_mcdmafec_h
11
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12
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/* Re-use of the definitions */
13
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#include <asm/fec.h>
14
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15
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typedef struct fecdma {
16
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u32 rsvd0; /* 0x000 */
17
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u32 eir; /* 0x004 */
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u32 eimr; /* 0x008 */
19
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u32 rsvd1[6]; /* 0x00C - 0x023 */
20
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u32 ecr; /* 0x024 */
21
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u32 rsvd2[6]; /* 0x028 - 0x03F */
22
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u32 mmfr; /* 0x040 */
23
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u32 mscr; /* 0x044 */
24
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u32 rsvd3[7]; /* 0x048 - 0x063 */
25
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u32 mibc; /* 0x064 */
26
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u32 rsvd4[7]; /* 0x068 - 0x083 */
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u32 rcr; /* 0x084 */
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u32 rhr; /* 0x088 */
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u32 rsvd5[14]; /* 0x08C - 0x0C3 */
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u32 tcr; /* 0x0C4 */
31
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u32 rsvd6[7]; /* 0x0C8 - 0x0E3 */
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u32 palr; /* 0x0E4 */
33
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u32 paur; /* 0x0E8 */
34
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u32 opd; /* 0x0EC */
35
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u32 rsvd7[10]; /* 0x0F0 - 0x117 */
36
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u32 iaur; /* 0x118 */
37
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u32 ialr; /* 0x11C */
38
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u32 gaur; /* 0x120 */
39
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u32 galr; /* 0x124 */
40
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u32 rsvd8[7]; /* 0x128 - 0x143 */
41
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u32 tfwr; /* 0x144 */
42
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u32 rsvd9[14]; /* 0x148 - 0x17F */
43
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u32 fmc; /* 0x180 */
44
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u32 rfdr; /* 0x184 */
45
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u32 rfsr; /* 0x188 */
46
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u32 rfcr; /* 0x18C */
47
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u32 rlrfp; /* 0x190 */
48
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u32 rlwfp; /* 0x194 */
49
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u32 rfar; /* 0x198 */
50
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u32 rfrp; /* 0x19C */
51
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u32 rfwp; /* 0x1A0 */
52
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u32 tfdr; /* 0x1A4 */
53
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u32 tfsr; /* 0x1A8 */
54
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u32 tfcr; /* 0x1AC */
55
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u32 tlrfp; /* 0x1B0 */
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u32 tlwfp; /* 0x1B4 */
57
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u32 tfar; /* 0x1B8 */
58
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u32 tfrp; /* 0x1BC */
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u32 tfwp; /* 0x1C0 */
60
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u32 frst; /* 0x1C4 */
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u32 ctcwr; /* 0x1C8 */
62
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} fecdma_t;
63
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64
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struct fec_info_dma {
65
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int index;
66
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u32 iobase;
67
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u32 pinmux;
68
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u32 miibase;
69
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int phy_addr;
70
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int dup_spd;
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char *phy_name;
72
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int phyname_init;
73
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cbd_t *rxbd; /* Rx BD */
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cbd_t *txbd; /* Tx BD */
75
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uint rx_idx;
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uint tx_idx;
77
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char *txbuf;
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int initialized;
79
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struct fec_info_dma *next;
80
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u16 rx_task; /* DMA receive Task Number */
81
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u16 tx_task; /* DMA Transmit Task Number */
82
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u16 rx_pri; /* DMA Receive Priority */
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u16 tx_pri; /* DMA Transmit Priority */
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u16 rx_init; /* DMA Receive Initiator */
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u16 tx_init; /* DMA Transmit Initiator */
86
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u16 used_tbd_idx; /* next transmit BD to clean */
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u16 clean_tbd_num; /* the number of available transmit BDs */
88
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int to_loop;
89
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struct mii_dev *bus;
90
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};
91
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92
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/* Bit definitions and macros for IEVENT */
93
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#define FEC_EIR_TXERR (0x00040000)
94
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#define FEC_EIR_RXERR (0x00020000)
95
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#undef FEC_EIR_CLEAR_ALL
96
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#define FEC_EIR_CLEAR_ALL (0xFFFE0000)
97
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98
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/* Bit definitions and macros for R_HASH */
99
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#define FEC_RHASH_FCE_DC (0x80000000)
100
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#define FEC_RHASH_MULTCAST (0x40000000)
101
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#define FEC_RHASH_HASH(x) (((x)&0x0000003F)<<24)
102
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103
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/* Bit definitions and macros for FEC_TFWR */
104
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#undef FEC_TFWR_X_WMRK
105
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#undef FEC_TFWR_X_WMRK_64
106
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#undef FEC_TFWR_X_WMRK_128
107
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#undef FEC_TFWR_X_WMRK_192
108
-
109
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#define FEC_TFWR_X_WMRK(x) ((x)&0x0F)
110
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#define FEC_TFWR_X_WMRK_64 (0x00)
111
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#define FEC_TFWR_X_WMRK_128 (0x01)
112
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#define FEC_TFWR_X_WMRK_192 (0x02)
113
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#define FEC_TFWR_X_WMRK_256 (0x03)
114
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#define FEC_TFWR_X_WMRK_320 (0x04)
115
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#define FEC_TFWR_X_WMRK_384 (0x05)
116
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#define FEC_TFWR_X_WMRK_448 (0x06)
117
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#define FEC_TFWR_X_WMRK_512 (0x07)
118
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#define FEC_TFWR_X_WMRK_576 (0x08)
119
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#define FEC_TFWR_X_WMRK_640 (0x09)
120
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#define FEC_TFWR_X_WMRK_704 (0x0A)
121
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#define FEC_TFWR_X_WMRK_768 (0x0B)
122
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#define FEC_TFWR_X_WMRK_832 (0x0C)
123
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#define FEC_TFWR_X_WMRK_896 (0x0D)
124
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#define FEC_TFWR_X_WMRK_960 (0x0E)
125
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#define FEC_TFWR_X_WMRK_1024 (0x0F)
126
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127
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/* FIFO definitions */
128
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/* Bit definitions and macros for FSTAT */
129
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#define FIFO_STAT_IP (0x80000000)
130
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#define FIFO_STAT_FRAME(x) (((x)&0x0000000F)<<24)
131
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#define FIFO_STAT_FAE (0x00800000)
132
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#define FIFO_STAT_RXW (0x00400000)
133
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#define FIFO_STAT_UF (0x00200000)
134
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#define FIFO_STAT_OF (0x00100000)
135
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#define FIFO_STAT_FR (0x00080000)
136
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#define FIFO_STAT_FULL (0x00040000)
137
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#define FIFO_STAT_ALARM (0x00020000)
138
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#define FIFO_STAT_EMPTY (0x00010000)
139
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140
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/* Bit definitions and macros for FCTRL */
141
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#define FIFO_CTRL_WCTL (0x40000000)
142
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#define FIFO_CTRL_WFR (0x20000000)
143
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#define FIFO_CTRL_FRAME (0x08000000)
144
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#define FIFO_CTRL_GR(x) (((x)&0x00000007)<<24)
145
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#define FIFO_CTRL_IPMASK (0x00800000)
146
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#define FIFO_CTRL_FAEMASK (0x00400000)
147
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#define FIFO_CTRL_RXWMASK (0x00200000)
148
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#define FIFO_CTRL_UFMASK (0x00100000)
149
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#define FIFO_CTRL_OFMASK (0x00080000)
150
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151
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#endif /* fsl_mcdmafec_h */
-15
arch/m68k/include/asm/immap.h
-15
arch/m68k/include/asm/immap.h
···
314
314
#include <asm/immap_547x_8x.h>
315
315
#include <asm/m547x_8x.h>
316
316
317
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#ifdef CONFIG_FSLDMAFEC
318
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#define FEC0_RX_TASK 0
319
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#define FEC0_TX_TASK 1
320
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#define FEC0_RX_PRIORITY 6
321
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#define FEC0_TX_PRIORITY 7
322
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#define FEC0_RX_INIT 16
323
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#define FEC0_TX_INIT 17
324
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#define FEC1_RX_TASK 2
325
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#define FEC1_TX_TASK 3
326
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#define FEC1_RX_PRIORITY 6
327
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#define FEC1_TX_PRIORITY 7
328
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#define FEC1_RX_INIT 30
329
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#define FEC1_TX_INIT 31
330
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#endif
331
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332
317
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
333
318
334
319
#ifdef CONFIG_SLTTMR
+2
-2
arch/m68k/lib/fec.c
+2
-2
arch/m68k/lib/fec.c
···
10
10
11
11
DECLARE_GLOBAL_DATA_PTR;
12
12
13
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#if defined(CONFIG_MCFFEC) || defined(CONFIG_FSLDMAFEC)
13
+
#if defined(CONFIG_MCFFEC)
14
14
static int fec_get_node(int fec_idx)
15
15
{
16
16
char fec_alias[5] = {"fec"};
···
77
77
return fec_get_fdt_prop(fec_idx, "mii-base", mii_base);
78
78
}
79
79
80
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#endif //CONFIG_MCFFEC || CONFIG_FSLDMAFEC
80
+
#endif //CONFIG_MCFFEC
-1
drivers/dma/Kconfig
-1
drivers/dma/Kconfig
-1010
drivers/dma/MCD_dmaApi.c
-1010
drivers/dma/MCD_dmaApi.c
···
1
-
// SPDX-License-Identifier: GPL-2.0+
2
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/*
3
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4
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*/
5
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6
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/*Main C file for multi-channel DMA API. */
7
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8
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#include <common.h>
9
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10
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#include <MCD_dma.h>
11
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#include <MCD_tasksInit.h>
12
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#include <MCD_progCheck.h>
13
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14
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/********************************************************************/
15
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/* This is an API-internal pointer to the DMA's registers */
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dmaRegs *MCD_dmaBar;
17
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18
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/*
19
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* These are the real and model task tables as generated by the
20
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* build process
21
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*/
22
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extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS];
23
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extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS];
24
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25
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/*
26
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* However, this (usually) gets relocated to on-chip SRAM, at which
27
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* point we access them as these tables
28
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*/
29
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volatile TaskTableEntry *MCD_taskTable;
30
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TaskTableEntry *MCD_modelTaskTable;
31
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32
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/*
33
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* MCD_chStatus[] is an array of status indicators for remembering
34
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* whether a DMA has ever been attempted on each channel, pausing
35
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* status, etc.
36
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*/
37
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static int MCD_chStatus[NCHANNELS] = {
38
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MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
39
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MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
40
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MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
41
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MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA
42
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};
43
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44
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/* Prototypes for local functions */
45
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static void MCD_memcpy(int *dest, int *src, u32 size);
46
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static void MCD_resmActions(int channel);
47
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48
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/*
49
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* Buffer descriptors used for storage of progress info for single Dmas
50
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* Also used as storage for the DMA for CRCs for single DMAs
51
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* Otherwise, the DMA does not parse these buffer descriptors
52
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*/
53
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#ifdef MCD_INCLUDE_EU
54
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extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
55
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#else
56
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MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
57
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#endif
58
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MCD_bufDesc *MCD_relocBuffDesc;
59
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60
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/* Defines for the debug control register's functions */
61
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#define DBG_CTL_COMP1_TASK (0x00002000)
62
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#define DBG_CTL_ENABLE (DBG_CTL_AUTO_ARM | \
63
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DBG_CTL_BREAK | \
64
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DBG_CTL_INT_BREAK | \
65
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DBG_CTL_COMP1_TASK)
66
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#define DBG_CTL_DISABLE (DBG_CTL_AUTO_ARM | \
67
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DBG_CTL_INT_BREAK | \
68
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DBG_CTL_COMP1_TASK)
69
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#define DBG_KILL_ALL_STAT (0xFFFFFFFF)
70
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71
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/* Offset to context save area where progress info is stored */
72
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#define CSAVE_OFFSET 10
73
-
74
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/* Defines for Byte Swapping */
75
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#define MCD_BYTE_SWAP_KILLER 0xFFF8888F
76
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#define MCD_NO_BYTE_SWAP_ATALL 0x00040000
77
-
78
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/* Execution Unit Identifiers */
79
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#define MAC 0 /* legacy - not used */
80
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#define LUAC 1 /* legacy - not used */
81
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#define CRC 2 /* legacy - not used */
82
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#define LURC 3 /* Logic Unit with CRC */
83
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84
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/* Task Identifiers */
85
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#define TASK_CHAINNOEU 0
86
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#define TASK_SINGLENOEU 1
87
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#ifdef MCD_INCLUDE_EU
88
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#define TASK_CHAINEU 2
89
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#define TASK_SINGLEEU 3
90
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#define TASK_FECRX 4
91
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#define TASK_FECTX 5
92
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#else
93
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#define TASK_CHAINEU 0
94
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#define TASK_SINGLEEU 1
95
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#define TASK_FECRX 2
96
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#define TASK_FECTX 3
97
-
#endif
98
-
99
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/*
100
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* Structure to remember which variant is on which channel
101
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* TBD- need this?
102
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*/
103
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typedef struct MCD_remVariants_struct MCD_remVariant;
104
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struct MCD_remVariants_struct {
105
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int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */
106
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int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */
107
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s16 remDestIncr[NCHANNELS]; /* DestIncr */
108
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s16 remSrcIncr[NCHANNELS]; /* srcIncr */
109
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u32 remXferSize[NCHANNELS]; /* xferSize */
110
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};
111
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112
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/* Structure to remember the startDma parameters for each channel */
113
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MCD_remVariant MCD_remVariants;
114
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/********************************************************************/
115
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/* Function: MCD_initDma
116
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* Purpose: Initializes the DMA API by setting up a pointer to the DMA
117
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* registers, relocating and creating the appropriate task
118
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* structures, and setting up some global settings
119
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* Arguments:
120
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* dmaBarAddr - pointer to the multichannel DMA registers
121
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* taskTableDest - location to move DMA task code and structs to
122
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* flags - operational parameters
123
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* Return Value:
124
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* MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned
125
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* MCD_OK otherwise
126
-
*/
127
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extern u32 MCD_funcDescTab0[];
128
-
129
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int MCD_initDma(dmaRegs * dmaBarAddr, void *taskTableDest, u32 flags)
130
-
{
131
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int i;
132
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TaskTableEntry *entryPtr;
133
-
134
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/* setup the local pointer to register set */
135
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MCD_dmaBar = dmaBarAddr;
136
-
137
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/* do we need to move/create a task table */
138
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if ((flags & MCD_RELOC_TASKS) != 0) {
139
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int fixedSize;
140
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u32 *fixedPtr;
141
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/*int *tablePtr = taskTableDest;TBD */
142
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int varTabsOffset, funcDescTabsOffset, contextSavesOffset;
143
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int taskDescTabsOffset;
144
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int taskTableSize, varTabsSize, funcDescTabsSize,
145
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contextSavesSize;
146
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int taskDescTabSize;
147
-
148
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int i;
149
-
150
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/* check if physical address is aligned on 512 byte boundary */
151
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if (((u32) taskTableDest & 0x000001ff) != 0)
152
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return (MCD_TABLE_UNALIGNED);
153
-
154
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/* set up local pointer to task Table */
155
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MCD_taskTable = taskTableDest;
156
-
157
-
/*
158
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* Create a task table:
159
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* - compute aligned base offsets for variable tables and
160
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* function descriptor tables, then
161
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* - loop through the task table and setup the pointers
162
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* - copy over model task table with the the actual task
163
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* descriptor tables
164
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*/
165
-
166
-
taskTableSize = NCHANNELS * sizeof(TaskTableEntry);
167
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/* align variable tables to size */
168
-
varTabsOffset = taskTableSize + (u32) taskTableDest;
169
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if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0)
170
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varTabsOffset =
171
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(varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE);
172
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/* align function descriptor tables */
173
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varTabsSize = NCHANNELS * VAR_TAB_SIZE;
174
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funcDescTabsOffset = varTabsOffset + varTabsSize;
175
-
176
-
if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0)
177
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funcDescTabsOffset =
178
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(funcDescTabsOffset +
179
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FUNCDESC_TAB_SIZE) & (~FUNCDESC_TAB_SIZE);
180
-
181
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funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE;
182
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contextSavesOffset = funcDescTabsOffset + funcDescTabsSize;
183
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contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE);
184
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fixedSize =
185
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taskTableSize + varTabsSize + funcDescTabsSize +
186
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contextSavesSize;
187
-
188
-
/* zero the thing out */
189
-
fixedPtr = (u32 *) taskTableDest;
190
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for (i = 0; i < (fixedSize / 4); i++)
191
-
fixedPtr[i] = 0;
192
-
193
-
entryPtr = (TaskTableEntry *) MCD_taskTable;
194
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/* set up fixed pointers */
195
-
for (i = 0; i < NCHANNELS; i++) {
196
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/* update ptr to local value */
197
-
entryPtr[i].varTab = (u32) varTabsOffset;
198
-
entryPtr[i].FDTandFlags =
199
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(u32) funcDescTabsOffset | MCD_TT_FLAGS_DEF;
200
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entryPtr[i].contextSaveSpace = (u32) contextSavesOffset;
201
-
varTabsOffset += VAR_TAB_SIZE;
202
-
#ifdef MCD_INCLUDE_EU
203
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/* if not there is only one, just point to the
204
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same one */
205
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funcDescTabsOffset += FUNCDESC_TAB_SIZE;
206
-
#endif
207
-
contextSavesOffset += CONTEXT_SAVE_SIZE;
208
-
}
209
-
/* copy over the function descriptor table */
210
-
for (i = 0; i < FUNCDESC_TAB_NUM; i++) {
211
-
MCD_memcpy((void *)(entryPtr[i].
212
-
FDTandFlags & ~MCD_TT_FLAGS_MASK),
213
-
(void *)MCD_funcDescTab0, FUNCDESC_TAB_SIZE);
214
-
}
215
-
216
-
/* copy model task table to where the context saves stuff
217
-
leaves off */
218
-
MCD_modelTaskTable = (TaskTableEntry *) contextSavesOffset;
219
-
220
-
MCD_memcpy((void *)MCD_modelTaskTable,
221
-
(void *)MCD_modelTaskTableSrc,
222
-
NUMOFVARIANTS * sizeof(TaskTableEntry));
223
-
224
-
/* point to local version of model task table */
225
-
entryPtr = MCD_modelTaskTable;
226
-
taskDescTabsOffset = (u32) MCD_modelTaskTable +
227
-
(NUMOFVARIANTS * sizeof(TaskTableEntry));
228
-
229
-
/* copy actual task code and update TDT ptrs in local
230
-
model task table */
231
-
for (i = 0; i < NUMOFVARIANTS; i++) {
232
-
taskDescTabSize =
233
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entryPtr[i].TDTend - entryPtr[i].TDTstart + 4;
234
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MCD_memcpy((void *)taskDescTabsOffset,
235
-
(void *)entryPtr[i].TDTstart,
236
-
taskDescTabSize);
237
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entryPtr[i].TDTstart = (u32) taskDescTabsOffset;
238
-
taskDescTabsOffset += taskDescTabSize;
239
-
entryPtr[i].TDTend = (u32) taskDescTabsOffset - 4;
240
-
}
241
-
#ifdef MCD_INCLUDE_EU
242
-
/* Tack single DMA BDs onto end of code so API controls
243
-
where they are since DMA might write to them */
244
-
MCD_relocBuffDesc =
245
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(MCD_bufDesc *) (entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
246
-
#else
247
-
/* DMA does not touch them so they can be wherever and we
248
-
don't need to waste SRAM on them */
249
-
MCD_relocBuffDesc = MCD_singleBufDescs;
250
-
#endif
251
-
} else {
252
-
/* point the would-be relocated task tables and the
253
-
buffer descriptors to the ones the linker generated */
254
-
255
-
if (((u32) MCD_realTaskTableSrc & 0x000001ff) != 0)
256
-
return (MCD_TABLE_UNALIGNED);
257
-
258
-
/* need to add code to make sure that every thing else is
259
-
aligned properly TBD. this is problematic if we init
260
-
more than once or after running tasks, need to add
261
-
variable to see if we have aleady init'd */
262
-
entryPtr = MCD_realTaskTableSrc;
263
-
for (i = 0; i < NCHANNELS; i++) {
264
-
if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0) ||
265
-
((entryPtr[i].
266
-
FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0))
267
-
return (MCD_TABLE_UNALIGNED);
268
-
}
269
-
270
-
MCD_taskTable = MCD_realTaskTableSrc;
271
-
MCD_modelTaskTable = MCD_modelTaskTableSrc;
272
-
MCD_relocBuffDesc = MCD_singleBufDescs;
273
-
}
274
-
275
-
/* Make all channels as totally inactive, and remember them as such: */
276
-
277
-
MCD_dmaBar->taskbar = (u32) MCD_taskTable;
278
-
for (i = 0; i < NCHANNELS; i++) {
279
-
MCD_dmaBar->taskControl[i] = 0x0;
280
-
MCD_chStatus[i] = MCD_NO_DMA;
281
-
}
282
-
283
-
/* Set up pausing mechanism to inactive state: */
284
-
/* no particular values yet for either comparator registers */
285
-
MCD_dmaBar->debugComp1 = 0;
286
-
MCD_dmaBar->debugComp2 = 0;
287
-
MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
288
-
MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT;
289
-
290
-
/* enable or disable commbus prefetch, really need an ifdef or
291
-
something to keep from trying to set this in the 8220 */
292
-
if ((flags & MCD_COMM_PREFETCH_EN) != 0)
293
-
MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH;
294
-
else
295
-
MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH;
296
-
297
-
return (MCD_OK);
298
-
}
299
-
300
-
/*********************** End of MCD_initDma() ***********************/
301
-
302
-
/********************************************************************/
303
-
/* Function: MCD_dmaStatus
304
-
* Purpose: Returns the status of the DMA on the requested channel
305
-
* Arguments: channel - channel number
306
-
* Returns: Predefined status indicators
307
-
*/
308
-
int MCD_dmaStatus(int channel)
309
-
{
310
-
u16 tcrValue;
311
-
312
-
if ((channel < 0) || (channel >= NCHANNELS))
313
-
return (MCD_CHANNEL_INVALID);
314
-
315
-
tcrValue = MCD_dmaBar->taskControl[channel];
316
-
if ((tcrValue & TASK_CTL_EN) == 0) { /* nothing running */
317
-
/* if last reported with task enabled */
318
-
if (MCD_chStatus[channel] == MCD_RUNNING
319
-
|| MCD_chStatus[channel] == MCD_IDLE)
320
-
MCD_chStatus[channel] = MCD_DONE;
321
-
} else { /* something is running */
322
-
323
-
/* There are three possibilities: paused, running or idle. */
324
-
if (MCD_chStatus[channel] == MCD_RUNNING
325
-
|| MCD_chStatus[channel] == MCD_IDLE) {
326
-
MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
327
-
/* This register is selected to know which initiator is
328
-
actually asserted. */
329
-
if ((MCD_dmaBar->ptdDebug >> channel) & 0x1)
330
-
MCD_chStatus[channel] = MCD_RUNNING;
331
-
else
332
-
MCD_chStatus[channel] = MCD_IDLE;
333
-
/* do not change the status if it is already paused. */
334
-
}
335
-
}
336
-
return MCD_chStatus[channel];
337
-
}
338
-
339
-
/******************** End of MCD_dmaStatus() ************************/
340
-
341
-
/********************************************************************/
342
-
/* Function: MCD_startDma
343
-
* Ppurpose: Starts a particular kind of DMA
344
-
* Arguments:
345
-
* srcAddr - the channel on which to run the DMA
346
-
* srcIncr - the address to move data from, or buffer-descriptor address
347
-
* destAddr - the amount to increment the source address per transfer
348
-
* destIncr - the address to move data to
349
-
* dmaSize - the amount to increment the destination address per transfer
350
-
* xferSize - the number bytes in of each data movement (1, 2, or 4)
351
-
* initiator - what device initiates the DMA
352
-
* priority - priority of the DMA
353
-
* flags - flags describing the DMA
354
-
* funcDesc - description of byte swapping, bit swapping, and CRC actions
355
-
* srcAddrVirt - virtual buffer descriptor address TBD
356
-
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
357
-
*/
358
-
359
-
int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
360
-
s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
361
-
int priority, u32 flags, u32 funcDesc
362
-
#ifdef MCD_NEED_ADDR_TRANS
363
-
s8 * srcAddrVirt
364
-
#endif
365
-
)
366
-
{
367
-
int srcRsdIncr, destRsdIncr;
368
-
int *cSave;
369
-
short xferSizeIncr;
370
-
int tcrCount = 0;
371
-
#ifdef MCD_INCLUDE_EU
372
-
u32 *realFuncArray;
373
-
#endif
374
-
375
-
if ((channel < 0) || (channel >= NCHANNELS))
376
-
return (MCD_CHANNEL_INVALID);
377
-
378
-
/* tbd - need to determine the proper response to a bad funcDesc when
379
-
not including EU functions, for now, assign a benign funcDesc, but
380
-
maybe should return an error */
381
-
#ifndef MCD_INCLUDE_EU
382
-
funcDesc = MCD_FUNC_NOEU1;
383
-
#endif
384
-
385
-
#ifdef MCD_DEBUG
386
-
printf("startDma:Setting up params\n");
387
-
#endif
388
-
/* Set us up for task-wise priority. We don't technically need to do
389
-
this on every start, but since the register involved is in the same
390
-
longword as other registers that users are in control of, setting
391
-
it more than once is probably preferable. That since the
392
-
documentation doesn't seem to be completely consistent about the
393
-
nature of the PTD control register. */
394
-
MCD_dmaBar->ptdControl |= (u16) 0x8000;
395
-
396
-
/* Not sure what we need to keep here rtm TBD */
397
-
#if 1
398
-
/* Calculate additional parameters to the regular DMA calls. */
399
-
srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0);
400
-
destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0);
401
-
402
-
xferSizeIncr = (xferSize & 0xffff) | 0x20000000;
403
-
404
-
/* Remember for each channel which variant is running. */
405
-
MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr;
406
-
MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr;
407
-
MCD_remVariants.remDestIncr[channel] = destIncr;
408
-
MCD_remVariants.remSrcIncr[channel] = srcIncr;
409
-
MCD_remVariants.remXferSize[channel] = xferSize;
410
-
#endif
411
-
412
-
cSave =
413
-
(int *)(MCD_taskTable[channel].contextSaveSpace) + CSAVE_OFFSET +
414
-
CURRBD;
415
-
416
-
#ifdef MCD_INCLUDE_EU
417
-
/* may move this to EU specific calls */
418
-
realFuncArray =
419
-
(u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00);
420
-
/* Modify the LURC's normal and byte-residue-loop functions according
421
-
to parameter. */
422
-
realFuncArray[(LURC * 16)] = xferSize == 4 ?
423
-
funcDesc : xferSize == 2 ?
424
-
funcDesc & 0xfffff00f : funcDesc & 0xffff000f;
425
-
realFuncArray[(LURC * 16 + 1)] =
426
-
(funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL;
427
-
#endif
428
-
/* Write the initiator field in the TCR, and also set the
429
-
initiator-hold bit. Note that,due to a hardware quirk, this could
430
-
collide with an MDE access to the initiator-register file, so we
431
-
have to verify that the write reads back correctly. */
432
-
433
-
MCD_dmaBar->taskControl[channel] =
434
-
(initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
435
-
436
-
while (((MCD_dmaBar->taskControl[channel] & 0x1fff) !=
437
-
((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM))
438
-
&& (tcrCount < 1000)) {
439
-
tcrCount++;
440
-
/*MCD_dmaBar->ptd_tcr[channel] = (initiator << 8) | 0x0020; */
441
-
MCD_dmaBar->taskControl[channel] =
442
-
(initiator << 8) | TASK_CTL_HIPRITSKEN |
443
-
TASK_CTL_HLDINITNUM;
444
-
}
445
-
446
-
MCD_dmaBar->priority[channel] = (u8) priority & PRIORITY_PRI_MASK;
447
-
/* should be albe to handle this stuff with only one write to ts reg
448
-
- tbd */
449
-
if (channel < 8 && channel >= 0) {
450
-
MCD_dmaBar->taskSize0 &= ~(0xf << (7 - channel) * 4);
451
-
MCD_dmaBar->taskSize0 |=
452
-
(xferSize & 3) << (((7 - channel) * 4) + 2);
453
-
MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel) * 4);
454
-
} else {
455
-
MCD_dmaBar->taskSize1 &= ~(0xf << (15 - channel) * 4);
456
-
MCD_dmaBar->taskSize1 |=
457
-
(xferSize & 3) << (((15 - channel) * 4) + 2);
458
-
MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel) * 4);
459
-
}
460
-
461
-
/* setup task table flags/options which mostly control the line
462
-
buffers */
463
-
MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK;
464
-
MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags);
465
-
466
-
if (flags & MCD_FECTX_DMA) {
467
-
/* TDTStart and TDTEnd */
468
-
MCD_taskTable[channel].TDTstart =
469
-
MCD_modelTaskTable[TASK_FECTX].TDTstart;
470
-
MCD_taskTable[channel].TDTend =
471
-
MCD_modelTaskTable[TASK_FECTX].TDTend;
472
-
MCD_startDmaENetXmit((char *)srcAddr, (char *)srcAddr,
473
-
(char *)destAddr, MCD_taskTable,
474
-
channel);
475
-
} else if (flags & MCD_FECRX_DMA) {
476
-
/* TDTStart and TDTEnd */
477
-
MCD_taskTable[channel].TDTstart =
478
-
MCD_modelTaskTable[TASK_FECRX].TDTstart;
479
-
MCD_taskTable[channel].TDTend =
480
-
MCD_modelTaskTable[TASK_FECRX].TDTend;
481
-
MCD_startDmaENetRcv((char *)srcAddr, (char *)srcAddr,
482
-
(char *)destAddr, MCD_taskTable,
483
-
channel);
484
-
} else if (flags & MCD_SINGLE_DMA) {
485
-
/* this buffer descriptor is used for storing off initial
486
-
parameters for later progress query calculation and for the
487
-
DMA to write the resulting checksum. The DMA does not use
488
-
this to determine how to operate, that info is passed with
489
-
the init routine */
490
-
MCD_relocBuffDesc[channel].srcAddr = srcAddr;
491
-
MCD_relocBuffDesc[channel].destAddr = destAddr;
492
-
493
-
/* definitely not its final value */
494
-
MCD_relocBuffDesc[channel].lastDestAddr = destAddr;
495
-
496
-
MCD_relocBuffDesc[channel].dmaSize = dmaSize;
497
-
MCD_relocBuffDesc[channel].flags = 0; /* not used */
498
-
MCD_relocBuffDesc[channel].csumResult = 0; /* not used */
499
-
MCD_relocBuffDesc[channel].next = 0; /* not used */
500
-
501
-
/* Initialize the progress-querying stuff to show no
502
-
progress: */
503
-
((volatile int *)MCD_taskTable[channel].
504
-
contextSaveSpace)[SRCPTR + CSAVE_OFFSET] = (int)srcAddr;
505
-
((volatile int *)MCD_taskTable[channel].
506
-
contextSaveSpace)[DESTPTR + CSAVE_OFFSET] = (int)destAddr;
507
-
((volatile int *)MCD_taskTable[channel].
508
-
contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
509
-
((volatile int *)MCD_taskTable[channel].
510
-
contextSaveSpace)[CURRBD + CSAVE_OFFSET] =
511
-
(u32) & (MCD_relocBuffDesc[channel]);
512
-
/* tbd - need to keep the user from trying to call the EU
513
-
routine when MCD_INCLUDE_EU is not defined */
514
-
if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) {
515
-
/* TDTStart and TDTEnd */
516
-
MCD_taskTable[channel].TDTstart =
517
-
MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart;
518
-
MCD_taskTable[channel].TDTend =
519
-
MCD_modelTaskTable[TASK_SINGLENOEU].TDTend;
520
-
MCD_startDmaSingleNoEu((char *)srcAddr, srcIncr,
521
-
(char *)destAddr, destIncr,
522
-
(int)dmaSize, xferSizeIncr,
523
-
flags, (int *)
524
-
&(MCD_relocBuffDesc[channel]),
525
-
cSave, MCD_taskTable, channel);
526
-
} else {
527
-
/* TDTStart and TDTEnd */
528
-
MCD_taskTable[channel].TDTstart =
529
-
MCD_modelTaskTable[TASK_SINGLEEU].TDTstart;
530
-
MCD_taskTable[channel].TDTend =
531
-
MCD_modelTaskTable[TASK_SINGLEEU].TDTend;
532
-
MCD_startDmaSingleEu((char *)srcAddr, srcIncr,
533
-
(char *)destAddr, destIncr,
534
-
(int)dmaSize, xferSizeIncr,
535
-
flags, (int *)
536
-
&(MCD_relocBuffDesc[channel]),
537
-
cSave, MCD_taskTable, channel);
538
-
}
539
-
} else { /* chained DMAS */
540
-
/* Initialize the progress-querying stuff to show no
541
-
progress: */
542
-
#if 1
543
-
/* (!defined(MCD_NEED_ADDR_TRANS)) */
544
-
((volatile int *)MCD_taskTable[channel].
545
-
contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
546
-
= (int)((MCD_bufDesc *) srcAddr)->srcAddr;
547
-
((volatile int *)MCD_taskTable[channel].
548
-
contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
549
-
= (int)((MCD_bufDesc *) srcAddr)->destAddr;
550
-
#else
551
-
/* if using address translation, need the virtual addr of the
552
-
first buffdesc */
553
-
((volatile int *)MCD_taskTable[channel].
554
-
contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
555
-
= (int)((MCD_bufDesc *) srcAddrVirt)->srcAddr;
556
-
((volatile int *)MCD_taskTable[channel].
557
-
contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
558
-
= (int)((MCD_bufDesc *) srcAddrVirt)->destAddr;
559
-
#endif
560
-
((volatile int *)MCD_taskTable[channel].
561
-
contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
562
-
((volatile int *)MCD_taskTable[channel].
563
-
contextSaveSpace)[CURRBD + CSAVE_OFFSET] = (u32) srcAddr;
564
-
565
-
if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) {
566
-
/*TDTStart and TDTEnd */
567
-
MCD_taskTable[channel].TDTstart =
568
-
MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart;
569
-
MCD_taskTable[channel].TDTend =
570
-
MCD_modelTaskTable[TASK_CHAINNOEU].TDTend;
571
-
MCD_startDmaChainNoEu((int *)srcAddr, srcIncr,
572
-
destIncr, xferSize,
573
-
xferSizeIncr, cSave,
574
-
MCD_taskTable, channel);
575
-
} else {
576
-
/*TDTStart and TDTEnd */
577
-
MCD_taskTable[channel].TDTstart =
578
-
MCD_modelTaskTable[TASK_CHAINEU].TDTstart;
579
-
MCD_taskTable[channel].TDTend =
580
-
MCD_modelTaskTable[TASK_CHAINEU].TDTend;
581
-
MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr,
582
-
xferSize, xferSizeIncr, cSave,
583
-
MCD_taskTable, channel);
584
-
}
585
-
}
586
-
MCD_chStatus[channel] = MCD_IDLE;
587
-
return (MCD_OK);
588
-
}
589
-
590
-
/************************ End of MCD_startDma() *********************/
591
-
592
-
/********************************************************************/
593
-
/* Function: MCD_XferProgrQuery
594
-
* Purpose: Returns progress of DMA on requested channel
595
-
* Arguments: channel - channel to retrieve progress for
596
-
* progRep - pointer to user supplied MCD_XferProg struct
597
-
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
598
-
*
599
-
* Notes:
600
-
* MCD_XferProgrQuery() upon completing or after aborting a DMA, or
601
-
* while the DMA is in progress, this function returns the first
602
-
* DMA-destination address not (or not yet) used in the DMA. When
603
-
* encountering a non-ready buffer descriptor, the information for
604
-
* the last completed descriptor is returned.
605
-
*
606
-
* MCD_XferProgQuery() has to avoid the possibility of getting
607
-
* partially-updated information in the event that we should happen
608
-
* to query DMA progress just as the DMA is updating it. It does that
609
-
* by taking advantage of the fact context is not saved frequently for
610
-
* the most part. We therefore read it at least twice until we get the
611
-
* same information twice in a row.
612
-
*
613
-
* Because a small, but not insignificant, amount of time is required
614
-
* to write out the progress-query information, especially upon
615
-
* completion of the DMA, it would be wise to guarantee some time lag
616
-
* between successive readings of the progress-query information.
617
-
*/
618
-
619
-
/* How many iterations of the loop below to execute to stabilize values */
620
-
#define STABTIME 0
621
-
622
-
int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep)
623
-
{
624
-
MCD_XferProg prevRep;
625
-
int again; /* true if we are to try again to ge
626
-
consistent results */
627
-
int i; /* used as a time-waste counter */
628
-
int destDiffBytes; /* Total no of bytes that we think actually
629
-
got xfered. */
630
-
int numIterations; /* number of iterations */
631
-
int bytesNotXfered; /* bytes that did not get xfered. */
632
-
s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr;
633
-
int subModVal, addModVal; /* Mode values to added and subtracted
634
-
from the final destAddr */
635
-
636
-
if ((channel < 0) || (channel >= NCHANNELS))
637
-
return (MCD_CHANNEL_INVALID);
638
-
639
-
/* Read a trial value for the progress-reporting values */
640
-
prevRep.lastSrcAddr =
641
-
(s8 *) ((volatile int *)MCD_taskTable[channel].
642
-
contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
643
-
prevRep.lastDestAddr =
644
-
(s8 *) ((volatile int *)MCD_taskTable[channel].
645
-
contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
646
-
prevRep.dmaSize =
647
-
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT +
648
-
CSAVE_OFFSET];
649
-
prevRep.currBufDesc =
650
-
(MCD_bufDesc *) ((volatile int *)MCD_taskTable[channel].
651
-
contextSaveSpace)[CURRBD + CSAVE_OFFSET];
652
-
/* Repeatedly reread those values until they match previous values: */
653
-
do {
654
-
/* Waste a little bit of time to ensure stability: */
655
-
for (i = 0; i < STABTIME; i++) {
656
-
/* make sure this loop does something so that it
657
-
doesn't get optimized out */
658
-
i += i >> 2;
659
-
}
660
-
/* Check them again: */
661
-
progRep->lastSrcAddr =
662
-
(s8 *) ((volatile int *)MCD_taskTable[channel].
663
-
contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
664
-
progRep->lastDestAddr =
665
-
(s8 *) ((volatile int *)MCD_taskTable[channel].
666
-
contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
667
-
progRep->dmaSize =
668
-
((volatile int *)MCD_taskTable[channel].
669
-
contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
670
-
progRep->currBufDesc =
671
-
(MCD_bufDesc *) ((volatile int *)MCD_taskTable[channel].
672
-
contextSaveSpace)[CURRBD + CSAVE_OFFSET];
673
-
/* See if they match: */
674
-
if (prevRep.lastSrcAddr != progRep->lastSrcAddr
675
-
|| prevRep.lastDestAddr != progRep->lastDestAddr
676
-
|| prevRep.dmaSize != progRep->dmaSize
677
-
|| prevRep.currBufDesc != progRep->currBufDesc) {
678
-
/* If they don't match, remember previous values and
679
-
try again: */
680
-
prevRep.lastSrcAddr = progRep->lastSrcAddr;
681
-
prevRep.lastDestAddr = progRep->lastDestAddr;
682
-
prevRep.dmaSize = progRep->dmaSize;
683
-
prevRep.currBufDesc = progRep->currBufDesc;
684
-
again = MCD_TRUE;
685
-
} else
686
-
again = MCD_FALSE;
687
-
} while (again == MCD_TRUE);
688
-
689
-
/* Update the dCount, srcAddr and destAddr */
690
-
/* To calculate dmaCount, we consider destination address. C
691
-
overs M1,P1,Z for destination */
692
-
switch (MCD_remVariants.remDestRsdIncr[channel]) {
693
-
case MINUS1:
694
-
subModVal =
695
-
((int)progRep->
696
-
lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) -
697
-
1);
698
-
addModVal =
699
-
((int)progRep->currBufDesc->
700
-
destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
701
-
LWAlignedInitDestAddr =
702
-
(progRep->currBufDesc->destAddr) - addModVal;
703
-
LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal;
704
-
destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr;
705
-
bytesNotXfered =
706
-
(destDiffBytes / MCD_remVariants.remDestIncr[channel]) *
707
-
(MCD_remVariants.remDestIncr[channel]
708
-
+ MCD_remVariants.remXferSize[channel]);
709
-
progRep->dmaSize =
710
-
destDiffBytes - bytesNotXfered + addModVal - subModVal;
711
-
break;
712
-
case ZERO:
713
-
progRep->lastDestAddr = progRep->currBufDesc->destAddr;
714
-
break;
715
-
case PLUS1:
716
-
/* This value has to be subtracted from the final
717
-
calculated dCount. */
718
-
subModVal =
719
-
((int)progRep->currBufDesc->
720
-
destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
721
-
/* These bytes are already in lastDestAddr. */
722
-
addModVal =
723
-
((int)progRep->
724
-
lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) -
725
-
1);
726
-
LWAlignedInitDestAddr =
727
-
(progRep->currBufDesc->destAddr) - subModVal;
728
-
LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal;
729
-
destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr);
730
-
numIterations =
731
-
(LWAlignedCurrDestAddr -
732
-
LWAlignedInitDestAddr) /
733
-
MCD_remVariants.remDestIncr[channel];
734
-
bytesNotXfered =
735
-
numIterations * (MCD_remVariants.remDestIncr[channel]
736
-
- MCD_remVariants.remXferSize[channel]);
737
-
progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal;
738
-
break;
739
-
default:
740
-
break;
741
-
}
742
-
743
-
/* This covers M1,P1,Z for source */
744
-
switch (MCD_remVariants.remSrcRsdIncr[channel]) {
745
-
case MINUS1:
746
-
progRep->lastSrcAddr =
747
-
progRep->currBufDesc->srcAddr +
748
-
(MCD_remVariants.remSrcIncr[channel] *
749
-
(progRep->dmaSize / MCD_remVariants.remXferSize[channel]));
750
-
break;
751
-
case ZERO:
752
-
progRep->lastSrcAddr = progRep->currBufDesc->srcAddr;
753
-
break;
754
-
case PLUS1:
755
-
progRep->lastSrcAddr =
756
-
progRep->currBufDesc->srcAddr +
757
-
(MCD_remVariants.remSrcIncr[channel] *
758
-
(progRep->dmaSize / MCD_remVariants.remXferSize[channel]));
759
-
break;
760
-
default:
761
-
break;
762
-
}
763
-
764
-
return (MCD_OK);
765
-
}
766
-
767
-
/******************* End of MCD_XferProgrQuery() ********************/
768
-
769
-
/********************************************************************/
770
-
/* MCD_resmActions() does the majority of the actions of a DMA resume.
771
-
* It is called from MCD_killDma() and MCD_resumeDma(). It has to be
772
-
* a separate function because the kill function has to negate the task
773
-
* enable before resuming it, but the resume function has to do nothing
774
-
* if there is no DMA on that channel (i.e., if the enable bit is 0).
775
-
*/
776
-
static void MCD_resmActions(int channel)
777
-
{
778
-
MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
779
-
MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus;
780
-
/* This register is selected to know which initiator is
781
-
actually asserted. */
782
-
MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
783
-
784
-
if ((MCD_dmaBar->ptdDebug >> channel) & 0x1)
785
-
MCD_chStatus[channel] = MCD_RUNNING;
786
-
else
787
-
MCD_chStatus[channel] = MCD_IDLE;
788
-
}
789
-
790
-
/********************* End of MCD_resmActions() *********************/
791
-
792
-
/********************************************************************/
793
-
/* Function: MCD_killDma
794
-
* Purpose: Halt the DMA on the requested channel, without any
795
-
* intention of resuming the DMA.
796
-
* Arguments: channel - requested channel
797
-
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
798
-
*
799
-
* Notes:
800
-
* A DMA may be killed from any state, including paused state, and it
801
-
* always goes to the MCD_HALTED state even if it is killed while in
802
-
* the MCD_NO_DMA or MCD_IDLE states.
803
-
*/
804
-
int MCD_killDma(int channel)
805
-
{
806
-
/* MCD_XferProg progRep; */
807
-
808
-
if ((channel < 0) || (channel >= NCHANNELS))
809
-
return (MCD_CHANNEL_INVALID);
810
-
811
-
MCD_dmaBar->taskControl[channel] = 0x0;
812
-
MCD_resumeDma(channel);
813
-
/*
814
-
* This must be after the write to the TCR so that the task doesn't
815
-
* start up again momentarily, and before the status assignment so
816
-
* as to override whatever MCD_resumeDma() may do to the channel
817
-
* status.
818
-
*/
819
-
MCD_chStatus[channel] = MCD_HALTED;
820
-
821
-
/*
822
-
* Update the current buffer descriptor's lastDestAddr field
823
-
*
824
-
* MCD_XferProgrQuery (channel, &progRep);
825
-
* progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
826
-
*/
827
-
return (MCD_OK);
828
-
}
829
-
830
-
/************************ End of MCD_killDma() **********************/
831
-
832
-
/********************************************************************/
833
-
/* Function: MCD_continDma
834
-
* Purpose: Continue a DMA which as stopped due to encountering an
835
-
* unready buffer descriptor.
836
-
* Arguments: channel - channel to continue the DMA on
837
-
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
838
-
*
839
-
* Notes:
840
-
* This routine does not check to see if there is a task which can
841
-
* be continued. Also this routine should not be used with single DMAs.
842
-
*/
843
-
int MCD_continDma(int channel)
844
-
{
845
-
if ((channel < 0) || (channel >= NCHANNELS))
846
-
return (MCD_CHANNEL_INVALID);
847
-
848
-
MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN;
849
-
MCD_chStatus[channel] = MCD_RUNNING;
850
-
851
-
return (MCD_OK);
852
-
}
853
-
854
-
/********************** End of MCD_continDma() **********************/
855
-
856
-
/*********************************************************************
857
-
* MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit
858
-
* to freeze a task and resume it. We freeze a task by breakpointing
859
-
* on the stated task. That is, not any specific place in the task,
860
-
* but any time that task executes. In particular, when that task
861
-
* executes, we want to freeze that task and only that task.
862
-
*
863
-
* The bits of the debug control register influence interrupts vs.
864
-
* breakpoints as follows:
865
-
* - Bits 14 and 0 enable or disable debug functions. If enabled, you
866
-
* will get the interrupt but you may or may not get a breakpoint.
867
-
* - Bits 2 and 1 decide whether you also get a breakpoint in addition
868
-
* to an interrupt.
869
-
*
870
-
* The debug unit can do these actions in response to either internally
871
-
* detected breakpoint conditions from the comparators, or in response
872
-
* to the external breakpoint pin, or both.
873
-
* - Bits 14 and 1 perform the above-described functions for
874
-
* internally-generated conditions, i.e., the debug comparators.
875
-
* - Bits 0 and 2 perform the above-described functions for external
876
-
* conditions, i.e., the breakpoint external pin.
877
-
*
878
-
* Note that, although you "always" get the interrupt when you turn
879
-
* the debug functions, the interrupt can nevertheless, if desired, be
880
-
* masked by the corresponding bit in the PTD's IMR. Note also that
881
-
* this means that bits 14 and 0 must enable debug functions before
882
-
* bits 1 and 2, respectively, have any effect.
883
-
*
884
-
* NOTE: It's extremely important to not pause more than one DMA channel
885
-
* at a time.
886
-
********************************************************************/
887
-
888
-
/********************************************************************/
889
-
/* Function: MCD_pauseDma
890
-
* Purpose: Pauses the DMA on a given channel (if any DMA is running
891
-
* on that channel).
892
-
* Arguments: channel
893
-
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
894
-
*/
895
-
int MCD_pauseDma(int channel)
896
-
{
897
-
/* MCD_XferProg progRep; */
898
-
899
-
if ((channel < 0) || (channel >= NCHANNELS))
900
-
return (MCD_CHANNEL_INVALID);
901
-
902
-
if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) {
903
-
MCD_dmaBar->debugComp1 = channel;
904
-
MCD_dmaBar->debugControl =
905
-
DBG_CTL_ENABLE | (1 << (channel + 16));
906
-
MCD_chStatus[channel] = MCD_PAUSED;
907
-
908
-
/*
909
-
* Update the current buffer descriptor's lastDestAddr field
910
-
*
911
-
* MCD_XferProgrQuery (channel, &progRep);
912
-
* progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
913
-
*/
914
-
}
915
-
return (MCD_OK);
916
-
}
917
-
918
-
/************************* End of MCD_pauseDma() ********************/
919
-
920
-
/********************************************************************/
921
-
/* Function: MCD_resumeDma
922
-
* Purpose: Resumes the DMA on a given channel (if any DMA is
923
-
* running on that channel).
924
-
* Arguments: channel - channel on which to resume DMA
925
-
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
926
-
*/
927
-
int MCD_resumeDma(int channel)
928
-
{
929
-
if ((channel < 0) || (channel >= NCHANNELS))
930
-
return (MCD_CHANNEL_INVALID);
931
-
932
-
if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
933
-
MCD_resmActions(channel);
934
-
935
-
return (MCD_OK);
936
-
}
937
-
938
-
/************************ End of MCD_resumeDma() ********************/
939
-
940
-
/********************************************************************/
941
-
/* Function: MCD_csumQuery
942
-
* Purpose: Provide the checksum after performing a non-chained DMA
943
-
* Arguments: channel - channel to report on
944
-
* csum - pointer to where to write the checksum/CRC
945
-
* Returns: MCD_ERROR if the channel is invalid, else MCD_OK
946
-
*
947
-
* Notes:
948
-
*
949
-
*/
950
-
int MCD_csumQuery(int channel, u32 * csum)
951
-
{
952
-
#ifdef MCD_INCLUDE_EU
953
-
if ((channel < 0) || (channel >= NCHANNELS))
954
-
return (MCD_CHANNEL_INVALID);
955
-
956
-
*csum = MCD_relocBuffDesc[channel].csumResult;
957
-
return (MCD_OK);
958
-
#else
959
-
return (MCD_ERROR);
960
-
#endif
961
-
}
962
-
963
-
/*********************** End of MCD_resumeDma() *********************/
964
-
965
-
/********************************************************************/
966
-
/* Function: MCD_getCodeSize
967
-
* Purpose: Provide the size requirements of the microcoded tasks
968
-
* Returns: Size in bytes
969
-
*/
970
-
int MCD_getCodeSize(void)
971
-
{
972
-
#ifdef MCD_INCLUDE_EU
973
-
return (0x2b5c);
974
-
#else
975
-
return (0x173c);
976
-
#endif
977
-
}
978
-
979
-
/********************** End of MCD_getCodeSize() ********************/
980
-
981
-
/********************************************************************/
982
-
/* Function: MCD_getVersion
983
-
* Purpose: Provide the version string and number
984
-
* Arguments: longVersion - user supplied pointer to a pointer to a char
985
-
* which points to the version string
986
-
* Returns: Version number and version string (by reference)
987
-
*/
988
-
char MCD_versionString[] = "Multi-channel DMA API Alpha v0.3 (2004-04-26)";
989
-
#define MCD_REV_MAJOR 0x00
990
-
#define MCD_REV_MINOR 0x03
991
-
992
-
int MCD_getVersion(char **longVersion)
993
-
{
994
-
*longVersion = MCD_versionString;
995
-
return ((MCD_REV_MAJOR << 8) | MCD_REV_MINOR);
996
-
}
997
-
998
-
/********************** End of MCD_getVersion() *********************/
999
-
1000
-
/********************************************************************/
1001
-
/* Private version of memcpy()
1002
-
* Note that everything this is used for is longword-aligned.
1003
-
*/
1004
-
static void MCD_memcpy(int *dest, int *src, u32 size)
1005
-
{
1006
-
u32 i;
1007
-
1008
-
for (i = 0; i < size; i += sizeof(int), dest++, src++)
1009
-
*dest = *src;
1010
-
}
-2413
drivers/dma/MCD_tasks.c
-2413
drivers/dma/MCD_tasks.c
···
1
-
// SPDX-License-Identifier: GPL-2.0+
2
-
/*
3
-
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4
-
*/
5
-
6
-
/* Contains task code and structures for Multi-channel DMA */
7
-
8
-
#include <common.h>
9
-
10
-
#include <MCD_dma.h>
11
-
12
-
u32 MCD_varTab0[];
13
-
u32 MCD_varTab1[];
14
-
u32 MCD_varTab2[];
15
-
u32 MCD_varTab3[];
16
-
u32 MCD_varTab4[];
17
-
u32 MCD_varTab5[];
18
-
u32 MCD_varTab6[];
19
-
u32 MCD_varTab7[];
20
-
u32 MCD_varTab8[];
21
-
u32 MCD_varTab9[];
22
-
u32 MCD_varTab10[];
23
-
u32 MCD_varTab11[];
24
-
u32 MCD_varTab12[];
25
-
u32 MCD_varTab13[];
26
-
u32 MCD_varTab14[];
27
-
u32 MCD_varTab15[];
28
-
29
-
u32 MCD_funcDescTab0[];
30
-
#ifdef MCD_INCLUDE_EU
31
-
u32 MCD_funcDescTab1[];
32
-
u32 MCD_funcDescTab2[];
33
-
u32 MCD_funcDescTab3[];
34
-
u32 MCD_funcDescTab4[];
35
-
u32 MCD_funcDescTab5[];
36
-
u32 MCD_funcDescTab6[];
37
-
u32 MCD_funcDescTab7[];
38
-
u32 MCD_funcDescTab8[];
39
-
u32 MCD_funcDescTab9[];
40
-
u32 MCD_funcDescTab10[];
41
-
u32 MCD_funcDescTab11[];
42
-
u32 MCD_funcDescTab12[];
43
-
u32 MCD_funcDescTab13[];
44
-
u32 MCD_funcDescTab14[];
45
-
u32 MCD_funcDescTab15[];
46
-
#endif
47
-
48
-
u32 MCD_contextSave0[];
49
-
u32 MCD_contextSave1[];
50
-
u32 MCD_contextSave2[];
51
-
u32 MCD_contextSave3[];
52
-
u32 MCD_contextSave4[];
53
-
u32 MCD_contextSave5[];
54
-
u32 MCD_contextSave6[];
55
-
u32 MCD_contextSave7[];
56
-
u32 MCD_contextSave8[];
57
-
u32 MCD_contextSave9[];
58
-
u32 MCD_contextSave10[];
59
-
u32 MCD_contextSave11[];
60
-
u32 MCD_contextSave12[];
61
-
u32 MCD_contextSave13[];
62
-
u32 MCD_contextSave14[];
63
-
u32 MCD_contextSave15[];
64
-
65
-
u32 MCD_realTaskTableSrc[] = {
66
-
0x00000000,
67
-
0x00000000,
68
-
(u32) MCD_varTab0, /* Task 0 Variable Table */
69
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
70
-
0x00000000,
71
-
0x00000000,
72
-
(u32) MCD_contextSave0, /* Task 0 context save space */
73
-
0x00000000,
74
-
0x00000000,
75
-
0x00000000,
76
-
(u32) MCD_varTab1, /* Task 1 Variable Table */
77
-
#ifdef MCD_INCLUDE_EU
78
-
(u32) MCD_funcDescTab1, /* Task 1 Fn Desc. Table & Flags */
79
-
#else
80
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
81
-
#endif
82
-
0x00000000,
83
-
0x00000000,
84
-
(u32) MCD_contextSave1, /* Task 1 context save space */
85
-
0x00000000,
86
-
0x00000000,
87
-
0x00000000,
88
-
(u32) MCD_varTab2, /* Task 2 Variable Table */
89
-
#ifdef MCD_INCLUDE_EU
90
-
(u32) MCD_funcDescTab2, /* Task 2 Fn Desc. Table & Flags */
91
-
#else
92
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
93
-
#endif
94
-
0x00000000,
95
-
0x00000000,
96
-
(u32) MCD_contextSave2, /* Task 2 context save space */
97
-
0x00000000,
98
-
0x00000000,
99
-
0x00000000,
100
-
(u32) MCD_varTab3, /* Task 3 Variable Table */
101
-
#ifdef MCD_INCLUDE_EU
102
-
(u32) MCD_funcDescTab3, /* Task 3 Fn Desc. Table & Flags */
103
-
#else
104
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
105
-
#endif
106
-
0x00000000,
107
-
0x00000000,
108
-
(u32) MCD_contextSave3, /* Task 3 context save space */
109
-
0x00000000,
110
-
0x00000000,
111
-
0x00000000,
112
-
(u32) MCD_varTab4, /* Task 4 Variable Table */
113
-
#ifdef MCD_INCLUDE_EU
114
-
(u32) MCD_funcDescTab4, /* Task 4 Fn Desc. Table & Flags */
115
-
#else
116
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
117
-
#endif
118
-
0x00000000,
119
-
0x00000000,
120
-
(u32) MCD_contextSave4, /* Task 4 context save space */
121
-
0x00000000,
122
-
0x00000000,
123
-
0x00000000,
124
-
(u32) MCD_varTab5, /* Task 5 Variable Table */
125
-
#ifdef MCD_INCLUDE_EU
126
-
(u32) MCD_funcDescTab5, /* Task 5 Fn Desc. Table & Flags */
127
-
#else
128
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
129
-
#endif
130
-
0x00000000,
131
-
0x00000000,
132
-
(u32) MCD_contextSave5, /* Task 5 context save space */
133
-
0x00000000,
134
-
0x00000000,
135
-
0x00000000,
136
-
(u32) MCD_varTab6, /* Task 6 Variable Table */
137
-
#ifdef MCD_INCLUDE_EU
138
-
(u32) MCD_funcDescTab6, /* Task 6 Fn Desc. Table & Flags */
139
-
#else
140
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
141
-
#endif
142
-
0x00000000,
143
-
0x00000000,
144
-
(u32) MCD_contextSave6, /* Task 6 context save space */
145
-
0x00000000,
146
-
0x00000000,
147
-
0x00000000,
148
-
(u32) MCD_varTab7, /* Task 7 Variable Table */
149
-
#ifdef MCD_INCLUDE_EU
150
-
(u32) MCD_funcDescTab7, /* Task 7 Fn Desc. Table & Flags */
151
-
#else
152
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
153
-
#endif
154
-
0x00000000,
155
-
0x00000000,
156
-
(u32) MCD_contextSave7, /* Task 7 context save space */
157
-
0x00000000,
158
-
0x00000000,
159
-
0x00000000,
160
-
(u32) MCD_varTab8, /* Task 8 Variable Table */
161
-
#ifdef MCD_INCLUDE_EU
162
-
(u32) MCD_funcDescTab8, /* Task 8 Fn Desc. Table & Flags */
163
-
#else
164
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
165
-
#endif
166
-
0x00000000,
167
-
0x00000000,
168
-
(u32) MCD_contextSave8, /* Task 8 context save space */
169
-
0x00000000,
170
-
0x00000000,
171
-
0x00000000,
172
-
(u32) MCD_varTab9, /* Task 9 Variable Table */
173
-
#ifdef MCD_INCLUDE_EU
174
-
(u32) MCD_funcDescTab9, /* Task 9 Fn Desc. Table & Flags */
175
-
#else
176
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
177
-
#endif
178
-
0x00000000,
179
-
0x00000000,
180
-
(u32) MCD_contextSave9, /* Task 9 context save space */
181
-
0x00000000,
182
-
0x00000000,
183
-
0x00000000,
184
-
(u32) MCD_varTab10, /* Task 10 Variable Table */
185
-
#ifdef MCD_INCLUDE_EU
186
-
(u32) MCD_funcDescTab10, /* Task 10 Fn Desc. Table & Flags */
187
-
#else
188
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
189
-
#endif
190
-
0x00000000,
191
-
0x00000000,
192
-
(u32) MCD_contextSave10, /* Task 10 context save space */
193
-
0x00000000,
194
-
0x00000000,
195
-
0x00000000,
196
-
(u32) MCD_varTab11, /* Task 11 Variable Table */
197
-
#ifdef MCD_INCLUDE_EU
198
-
(u32) MCD_funcDescTab11, /* Task 11 Fn Desc. Table & Flags */
199
-
#else
200
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
201
-
#endif
202
-
0x00000000,
203
-
0x00000000,
204
-
(u32) MCD_contextSave11, /* Task 11 context save space */
205
-
0x00000000,
206
-
0x00000000,
207
-
0x00000000,
208
-
(u32) MCD_varTab12, /* Task 12 Variable Table */
209
-
#ifdef MCD_INCLUDE_EU
210
-
(u32) MCD_funcDescTab12, /* Task 12 Fn Desc. Table & Flags */
211
-
#else
212
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
213
-
#endif
214
-
0x00000000,
215
-
0x00000000,
216
-
(u32) MCD_contextSave12, /* Task 12 context save space */
217
-
0x00000000,
218
-
0x00000000,
219
-
0x00000000,
220
-
(u32) MCD_varTab13, /* Task 13 Variable Table */
221
-
#ifdef MCD_INCLUDE_EU
222
-
(u32) MCD_funcDescTab13, /* Task 13 Fn Desc. Table & Flags */
223
-
#else
224
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
225
-
#endif
226
-
0x00000000,
227
-
0x00000000,
228
-
(u32) MCD_contextSave13, /* Task 13 context save space */
229
-
0x00000000,
230
-
0x00000000,
231
-
0x00000000,
232
-
(u32) MCD_varTab14, /* Task 14 Variable Table */
233
-
#ifdef MCD_INCLUDE_EU
234
-
(u32) MCD_funcDescTab14, /* Task 14 Fn Desc. Table & Flags */
235
-
#else
236
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
237
-
#endif
238
-
0x00000000,
239
-
0x00000000,
240
-
(u32) MCD_contextSave14, /* Task 14 context save space */
241
-
0x00000000,
242
-
0x00000000,
243
-
0x00000000,
244
-
(u32) MCD_varTab15, /* Task 15 Variable Table */
245
-
#ifdef MCD_INCLUDE_EU
246
-
(u32) MCD_funcDescTab15, /* Task 15 Fn Desc. Table & Flags */
247
-
#else
248
-
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
249
-
#endif
250
-
0x00000000,
251
-
0x00000000,
252
-
(u32) MCD_contextSave15, /* Task 15 context save space */
253
-
0x00000000,
254
-
};
255
-
256
-
u32 MCD_varTab0[] = { /* Task 0 Variable Table */
257
-
0x00000000, /* var[0] */
258
-
0x00000000, /* var[1] */
259
-
0x00000000, /* var[2] */
260
-
0x00000000, /* var[3] */
261
-
0x00000000, /* var[4] */
262
-
0x00000000, /* var[5] */
263
-
0x00000000, /* var[6] */
264
-
0x00000000, /* var[7] */
265
-
0x00000000, /* var[8] */
266
-
0x00000000, /* var[9] */
267
-
0x00000000, /* var[10] */
268
-
0x00000000, /* var[11] */
269
-
0x00000000, /* var[12] */
270
-
0x00000000, /* var[13] */
271
-
0x00000000, /* var[14] */
272
-
0x00000000, /* var[15] */
273
-
0x00000000, /* var[16] */
274
-
0x00000000, /* var[17] */
275
-
0x00000000, /* var[18] */
276
-
0x00000000, /* var[19] */
277
-
0x00000000, /* var[20] */
278
-
0x00000000, /* var[21] */
279
-
0x00000000, /* var[22] */
280
-
0x00000000, /* var[23] */
281
-
0xe0000000, /* inc[0] */
282
-
0x20000000, /* inc[1] */
283
-
0x2000ffff, /* inc[2] */
284
-
0x00000000, /* inc[3] */
285
-
0x00000000, /* inc[4] */
286
-
0x00000000, /* inc[5] */
287
-
0x00000000, /* inc[6] */
288
-
0x00000000, /* inc[7] */
289
-
};
290
-
291
-
u32 MCD_varTab1[] = {
292
-
0x00000000,
293
-
0x00000000,
294
-
0x00000000,
295
-
0x00000000,
296
-
0x00000000,
297
-
0x00000000,
298
-
0x00000000,
299
-
0x00000000,
300
-
0x00000000,
301
-
0x00000000,
302
-
0x00000000,
303
-
0x00000000,
304
-
0x00000000,
305
-
0x00000000,
306
-
0x00000000,
307
-
0x00000000,
308
-
0x00000000,
309
-
0x00000000,
310
-
0x00000000,
311
-
0x00000000,
312
-
0x00000000,
313
-
0x00000000,
314
-
0x00000000,
315
-
0x00000000,
316
-
0xe0000000,
317
-
0x20000000,
318
-
0x2000ffff,
319
-
0x00000000,
320
-
0x00000000,
321
-
0x00000000,
322
-
0x00000000,
323
-
0x00000000,
324
-
};
325
-
326
-
u32 MCD_varTab2[] = {
327
-
0x00000000,
328
-
0x00000000,
329
-
0x00000000,
330
-
0x00000000,
331
-
0x00000000,
332
-
0x00000000,
333
-
0x00000000,
334
-
0x00000000,
335
-
0x00000000,
336
-
0x00000000,
337
-
0x00000000,
338
-
0x00000000,
339
-
0x00000000,
340
-
0x00000000,
341
-
0x00000000,
342
-
0x00000000,
343
-
0x00000000,
344
-
0x00000000,
345
-
0x00000000,
346
-
0x00000000,
347
-
0x00000000,
348
-
0x00000000,
349
-
0x00000000,
350
-
0x00000000,
351
-
0xe0000000,
352
-
0x20000000,
353
-
0x2000ffff,
354
-
0x00000000,
355
-
0x00000000,
356
-
0x00000000,
357
-
0x00000000,
358
-
0x00000000,
359
-
};
360
-
361
-
u32 MCD_varTab3[] = {
362
-
0x00000000,
363
-
0x00000000,
364
-
0x00000000,
365
-
0x00000000,
366
-
0x00000000,
367
-
0x00000000,
368
-
0x00000000,
369
-
0x00000000,
370
-
0x00000000,
371
-
0x00000000,
372
-
0x00000000,
373
-
0x00000000,
374
-
0x00000000,
375
-
0x00000000,
376
-
0x00000000,
377
-
0x00000000,
378
-
0x00000000,
379
-
0x00000000,
380
-
0x00000000,
381
-
0x00000000,
382
-
0x00000000,
383
-
0x00000000,
384
-
0x00000000,
385
-
0x00000000,
386
-
0xe0000000,
387
-
0x20000000,
388
-
0x2000ffff,
389
-
0x00000000,
390
-
0x00000000,
391
-
0x00000000,
392
-
0x00000000,
393
-
0x00000000,
394
-
};
395
-
396
-
u32 MCD_varTab4[] = {
397
-
0x00000000,
398
-
0x00000000,
399
-
0x00000000,
400
-
0x00000000,
401
-
0x00000000,
402
-
0x00000000,
403
-
0x00000000,
404
-
0x00000000,
405
-
0x00000000,
406
-
0x00000000,
407
-
0x00000000,
408
-
0x00000000,
409
-
0x00000000,
410
-
0x00000000,
411
-
0x00000000,
412
-
0x00000000,
413
-
0x00000000,
414
-
0x00000000,
415
-
0x00000000,
416
-
0x00000000,
417
-
0x00000000,
418
-
0x00000000,
419
-
0x00000000,
420
-
0x00000000,
421
-
0xe0000000,
422
-
0x20000000,
423
-
0x2000ffff,
424
-
0x00000000,
425
-
0x00000000,
426
-
0x00000000,
427
-
0x00000000,
428
-
0x00000000,
429
-
};
430
-
431
-
u32 MCD_varTab5[] = {
432
-
0x00000000,
433
-
0x00000000,
434
-
0x00000000,
435
-
0x00000000,
436
-
0x00000000,
437
-
0x00000000,
438
-
0x00000000,
439
-
0x00000000,
440
-
0x00000000,
441
-
0x00000000,
442
-
0x00000000,
443
-
0x00000000,
444
-
0x00000000,
445
-
0x00000000,
446
-
0x00000000,
447
-
0x00000000,
448
-
0x00000000,
449
-
0x00000000,
450
-
0x00000000,
451
-
0x00000000,
452
-
0x00000000,
453
-
0x00000000,
454
-
0x00000000,
455
-
0x00000000,
456
-
0xe0000000,
457
-
0x20000000,
458
-
0x2000ffff,
459
-
0x00000000,
460
-
0x00000000,
461
-
0x00000000,
462
-
0x00000000,
463
-
0x00000000,
464
-
};
465
-
466
-
u32 MCD_varTab6[] = {
467
-
0x00000000,
468
-
0x00000000,
469
-
0x00000000,
470
-
0x00000000,
471
-
0x00000000,
472
-
0x00000000,
473
-
0x00000000,
474
-
0x00000000,
475
-
0x00000000,
476
-
0x00000000,
477
-
0x00000000,
478
-
0x00000000,
479
-
0x00000000,
480
-
0x00000000,
481
-
0x00000000,
482
-
0x00000000,
483
-
0x00000000,
484
-
0x00000000,
485
-
0x00000000,
486
-
0x00000000,
487
-
0x00000000,
488
-
0x00000000,
489
-
0x00000000,
490
-
0x00000000,
491
-
0xe0000000,
492
-
0x20000000,
493
-
0x2000ffff,
494
-
0x00000000,
495
-
0x00000000,
496
-
0x00000000,
497
-
0x00000000,
498
-
0x00000000,
499
-
};
500
-
501
-
u32 MCD_varTab7[] = {
502
-
0x00000000,
503
-
0x00000000,
504
-
0x00000000,
505
-
0x00000000,
506
-
0x00000000,
507
-
0x00000000,
508
-
0x00000000,
509
-
0x00000000,
510
-
0x00000000,
511
-
0x00000000,
512
-
0x00000000,
513
-
0x00000000,
514
-
0x00000000,
515
-
0x00000000,
516
-
0x00000000,
517
-
0x00000000,
518
-
0x00000000,
519
-
0x00000000,
520
-
0x00000000,
521
-
0x00000000,
522
-
0x00000000,
523
-
0x00000000,
524
-
0x00000000,
525
-
0x00000000,
526
-
0xe0000000,
527
-
0x20000000,
528
-
0x2000ffff,
529
-
0x00000000,
530
-
0x00000000,
531
-
0x00000000,
532
-
0x00000000,
533
-
0x00000000,
534
-
};
535
-
536
-
u32 MCD_varTab8[] = {
537
-
0x00000000,
538
-
0x00000000,
539
-
0x00000000,
540
-
0x00000000,
541
-
0x00000000,
542
-
0x00000000,
543
-
0x00000000,
544
-
0x00000000,
545
-
0x00000000,
546
-
0x00000000,
547
-
0x00000000,
548
-
0x00000000,
549
-
0x00000000,
550
-
0x00000000,
551
-
0x00000000,
552
-
0x00000000,
553
-
0x00000000,
554
-
0x00000000,
555
-
0x00000000,
556
-
0x00000000,
557
-
0x00000000,
558
-
0x00000000,
559
-
0x00000000,
560
-
0x00000000,
561
-
0xe0000000,
562
-
0x20000000,
563
-
0x2000ffff,
564
-
0x00000000,
565
-
0x00000000,
566
-
0x00000000,
567
-
0x00000000,
568
-
0x00000000,
569
-
};
570
-
571
-
u32 MCD_varTab9[] = {
572
-
0x00000000,
573
-
0x00000000,
574
-
0x00000000,
575
-
0x00000000,
576
-
0x00000000,
577
-
0x00000000,
578
-
0x00000000,
579
-
0x00000000,
580
-
0x00000000,
581
-
0x00000000,
582
-
0x00000000,
583
-
0x00000000,
584
-
0x00000000,
585
-
0x00000000,
586
-
0x00000000,
587
-
0x00000000,
588
-
0x00000000,
589
-
0x00000000,
590
-
0x00000000,
591
-
0x00000000,
592
-
0x00000000,
593
-
0x00000000,
594
-
0x00000000,
595
-
0x00000000,
596
-
0xe0000000,
597
-
0x20000000,
598
-
0x2000ffff,
599
-
0x00000000,
600
-
0x00000000,
601
-
0x00000000,
602
-
0x00000000,
603
-
0x00000000,
604
-
};
605
-
606
-
u32 MCD_varTab10[] = {
607
-
0x00000000,
608
-
0x00000000,
609
-
0x00000000,
610
-
0x00000000,
611
-
0x00000000,
612
-
0x00000000,
613
-
0x00000000,
614
-
0x00000000,
615
-
0x00000000,
616
-
0x00000000,
617
-
0x00000000,
618
-
0x00000000,
619
-
0x00000000,
620
-
0x00000000,
621
-
0x00000000,
622
-
0x00000000,
623
-
0x00000000,
624
-
0x00000000,
625
-
0x00000000,
626
-
0x00000000,
627
-
0x00000000,
628
-
0x00000000,
629
-
0x00000000,
630
-
0x00000000,
631
-
0xe0000000,
632
-
0x20000000,
633
-
0x2000ffff,
634
-
0x00000000,
635
-
0x00000000,
636
-
0x00000000,
637
-
0x00000000,
638
-
0x00000000,
639
-
};
640
-
641
-
u32 MCD_varTab11[] = {
642
-
0x00000000,
643
-
0x00000000,
644
-
0x00000000,
645
-
0x00000000,
646
-
0x00000000,
647
-
0x00000000,
648
-
0x00000000,
649
-
0x00000000,
650
-
0x00000000,
651
-
0x00000000,
652
-
0x00000000,
653
-
0x00000000,
654
-
0x00000000,
655
-
0x00000000,
656
-
0x00000000,
657
-
0x00000000,
658
-
0x00000000,
659
-
0x00000000,
660
-
0x00000000,
661
-
0x00000000,
662
-
0x00000000,
663
-
0x00000000,
664
-
0x00000000,
665
-
0x00000000,
666
-
0xe0000000,
667
-
0x20000000,
668
-
0x2000ffff,
669
-
0x00000000,
670
-
0x00000000,
671
-
0x00000000,
672
-
0x00000000,
673
-
0x00000000,
674
-
};
675
-
676
-
u32 MCD_varTab12[] = {
677
-
0x00000000,
678
-
0x00000000,
679
-
0x00000000,
680
-
0x00000000,
681
-
0x00000000,
682
-
0x00000000,
683
-
0x00000000,
684
-
0x00000000,
685
-
0x00000000,
686
-
0x00000000,
687
-
0x00000000,
688
-
0x00000000,
689
-
0x00000000,
690
-
0x00000000,
691
-
0x00000000,
692
-
0x00000000,
693
-
0x00000000,
694
-
0x00000000,
695
-
0x00000000,
696
-
0x00000000,
697
-
0x00000000,
698
-
0x00000000,
699
-
0x00000000,
700
-
0x00000000,
701
-
0xe0000000,
702
-
0x20000000,
703
-
0x2000ffff,
704
-
0x00000000,
705
-
0x00000000,
706
-
0x00000000,
707
-
0x00000000,
708
-
0x00000000,
709
-
};
710
-
711
-
u32 MCD_varTab13[] = {
712
-
0x00000000,
713
-
0x00000000,
714
-
0x00000000,
715
-
0x00000000,
716
-
0x00000000,
717
-
0x00000000,
718
-
0x00000000,
719
-
0x00000000,
720
-
0x00000000,
721
-
0x00000000,
722
-
0x00000000,
723
-
0x00000000,
724
-
0x00000000,
725
-
0x00000000,
726
-
0x00000000,
727
-
0x00000000,
728
-
0x00000000,
729
-
0x00000000,
730
-
0x00000000,
731
-
0x00000000,
732
-
0x00000000,
733
-
0x00000000,
734
-
0x00000000,
735
-
0x00000000,
736
-
0xe0000000,
737
-
0x20000000,
738
-
0x2000ffff,
739
-
0x00000000,
740
-
0x00000000,
741
-
0x00000000,
742
-
0x00000000,
743
-
0x00000000,
744
-
};
745
-
746
-
u32 MCD_varTab14[] = {
747
-
0x00000000,
748
-
0x00000000,
749
-
0x00000000,
750
-
0x00000000,
751
-
0x00000000,
752
-
0x00000000,
753
-
0x00000000,
754
-
0x00000000,
755
-
0x00000000,
756
-
0x00000000,
757
-
0x00000000,
758
-
0x00000000,
759
-
0x00000000,
760
-
0x00000000,
761
-
0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
779
-
};
780
-
781
-
u32 MCD_varTab15[] = {
782
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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-
};
815
-
816
-
u32 MCD_funcDescTab0[] = {
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0x202da000,
879
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0x202e2000,
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0x202f2000,
881
-
};
882
-
883
-
#ifdef MCD_INCLUDE_EU
884
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u32 MCD_funcDescTab1[] = {
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};
950
-
951
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u32 MCD_funcDescTab2[] = {
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0x202da000,
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0x202e2000,
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0x202f2000,
1016
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};
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1018
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u32 MCD_funcDescTab3[] = {
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0x202da000,
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0x202e2000,
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0x202f2000,
1083
-
};
1084
-
1085
-
u32 MCD_funcDescTab4[] = {
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0x202ea000,
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0x202da000,
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-
0x202e2000,
1149
-
0x202f2000,
1150
-
};
1151
-
1152
-
u32 MCD_funcDescTab5[] = {
1153
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0x202ea000,
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0x202da000,
1215
-
0x202e2000,
1216
-
0x202f2000,
1217
-
};
1218
-
1219
-
u32 MCD_funcDescTab6[] = {
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0x202ea000,
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-
0x202da000,
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-
0x202e2000,
1283
-
0x202f2000,
1284
-
};
1285
-
1286
-
u32 MCD_funcDescTab7[] = {
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0x202ea000,
1348
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0x202da000,
1349
-
0x202e2000,
1350
-
0x202f2000,
1351
-
};
1352
-
1353
-
u32 MCD_funcDescTab8[] = {
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-
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-
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-
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-
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-
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-
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-
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0x00000000,
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-
0x00000000,
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-
0xa0045670,
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-
0xa0000000,
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-
0xa0000000,
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-
0x20000000,
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-
0x21800000,
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-
0x21e00000,
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-
0x20400000,
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-
0x20500000,
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-
0x205a0000,
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-
0x20a00000,
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-
0x202fa000,
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-
0x202f9000,
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-
0x202ea000,
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-
0x202da000,
1416
-
0x202e2000,
1417
-
0x202f2000,
1418
-
};
1419
-
1420
-
u32 MCD_funcDescTab9[] = {
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-
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-
0x00000000,
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-
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-
0x00000000,
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
0x00000000,
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-
0x00000000,
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-
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-
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-
0x00000000,
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-
0x00000000,
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-
0x00000000,
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-
0x00000000,
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-
0x00000000,
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-
0x00000000,
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-
0x00000000,
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-
0x00000000,
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-
0xa0045670,
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-
0xa0000000,
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-
0xa0000000,
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-
0x20000000,
1473
-
0x21800000,
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-
0x21e00000,
1475
-
0x20400000,
1476
-
0x20500000,
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-
0x205a0000,
1478
-
0x20a00000,
1479
-
0x202fa000,
1480
-
0x202f9000,
1481
-
0x202ea000,
1482
-
0x202da000,
1483
-
0x202e2000,
1484
-
0x202f2000,
1485
-
};
1486
-
1487
-
u32 MCD_funcDescTab10[] = {
1488
-
0x00000000,
1489
-
0x00000000,
1490
-
0x00000000,
1491
-
0x00000000,
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-
0x00000000,
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-
0x00000000,
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-
0x00000000,
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-
0x00000000,
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-
0x00000000,
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-
0x00000000,
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-
0x00000000,
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-
0x00000000,
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-
0x00000000,
1501
-
0x00000000,
1502
-
0x00000000,
1503
-
0x00000000,
1504
-
0x00000000,
1505
-
0x00000000,
1506
-
0x00000000,
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-
0x00000000,
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-
0x00000000,
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-
0x00000000,
1510
-
0x00000000,
1511
-
0x00000000,
1512
-
0x00000000,
1513
-
0x00000000,
1514
-
0x00000000,
1515
-
0x00000000,
1516
-
0x00000000,
1517
-
0x00000000,
1518
-
0x00000000,
1519
-
0x00000000,
1520
-
0x00000000,
1521
-
0x00000000,
1522
-
0x00000000,
1523
-
0x00000000,
1524
-
0x00000000,
1525
-
0x00000000,
1526
-
0x00000000,
1527
-
0x00000000,
1528
-
0x00000000,
1529
-
0x00000000,
1530
-
0x00000000,
1531
-
0x00000000,
1532
-
0x00000000,
1533
-
0x00000000,
1534
-
0x00000000,
1535
-
0x00000000,
1536
-
0xa0045670,
1537
-
0xa0000000,
1538
-
0xa0000000,
1539
-
0x20000000,
1540
-
0x21800000,
1541
-
0x21e00000,
1542
-
0x20400000,
1543
-
0x20500000,
1544
-
0x205a0000,
1545
-
0x20a00000,
1546
-
0x202fa000,
1547
-
0x202f9000,
1548
-
0x202ea000,
1549
-
0x202da000,
1550
-
0x202e2000,
1551
-
0x202f2000,
1552
-
};
1553
-
1554
-
u32 MCD_funcDescTab11[] = {
1555
-
0x00000000,
1556
-
0x00000000,
1557
-
0x00000000,
1558
-
0x00000000,
1559
-
0x00000000,
1560
-
0x00000000,
1561
-
0x00000000,
1562
-
0x00000000,
1563
-
0x00000000,
1564
-
0x00000000,
1565
-
0x00000000,
1566
-
0x00000000,
1567
-
0x00000000,
1568
-
0x00000000,
1569
-
0x00000000,
1570
-
0x00000000,
1571
-
0x00000000,
1572
-
0x00000000,
1573
-
0x00000000,
1574
-
0x00000000,
1575
-
0x00000000,
1576
-
0x00000000,
1577
-
0x00000000,
1578
-
0x00000000,
1579
-
0x00000000,
1580
-
0x00000000,
1581
-
0x00000000,
1582
-
0x00000000,
1583
-
0x00000000,
1584
-
0x00000000,
1585
-
0x00000000,
1586
-
0x00000000,
1587
-
0x00000000,
1588
-
0x00000000,
1589
-
0x00000000,
1590
-
0x00000000,
1591
-
0x00000000,
1592
-
0x00000000,
1593
-
0x00000000,
1594
-
0x00000000,
1595
-
0x00000000,
1596
-
0x00000000,
1597
-
0x00000000,
1598
-
0x00000000,
1599
-
0x00000000,
1600
-
0x00000000,
1601
-
0x00000000,
1602
-
0x00000000,
1603
-
0xa0045670,
1604
-
0xa0000000,
1605
-
0xa0000000,
1606
-
0x20000000,
1607
-
0x21800000,
1608
-
0x21e00000,
1609
-
0x20400000,
1610
-
0x20500000,
1611
-
0x205a0000,
1612
-
0x20a00000,
1613
-
0x202fa000,
1614
-
0x202f9000,
1615
-
0x202ea000,
1616
-
0x202da000,
1617
-
0x202e2000,
1618
-
0x202f2000,
1619
-
};
1620
-
1621
-
u32 MCD_funcDescTab12[] = {
1622
-
0x00000000,
1623
-
0x00000000,
1624
-
0x00000000,
1625
-
0x00000000,
1626
-
0x00000000,
1627
-
0x00000000,
1628
-
0x00000000,
1629
-
0x00000000,
1630
-
0x00000000,
1631
-
0x00000000,
1632
-
0x00000000,
1633
-
0x00000000,
1634
-
0x00000000,
1635
-
0x00000000,
1636
-
0x00000000,
1637
-
0x00000000,
1638
-
0x00000000,
1639
-
0x00000000,
1640
-
0x00000000,
1641
-
0x00000000,
1642
-
0x00000000,
1643
-
0x00000000,
1644
-
0x00000000,
1645
-
0x00000000,
1646
-
0x00000000,
1647
-
0x00000000,
1648
-
0x00000000,
1649
-
0x00000000,
1650
-
0x00000000,
1651
-
0x00000000,
1652
-
0x00000000,
1653
-
0x00000000,
1654
-
0x00000000,
1655
-
0x00000000,
1656
-
0x00000000,
1657
-
0x00000000,
1658
-
0x00000000,
1659
-
0x00000000,
1660
-
0x00000000,
1661
-
0x00000000,
1662
-
0x00000000,
1663
-
0x00000000,
1664
-
0x00000000,
1665
-
0x00000000,
1666
-
0x00000000,
1667
-
0x00000000,
1668
-
0x00000000,
1669
-
0x00000000,
1670
-
0xa0045670,
1671
-
0xa0000000,
1672
-
0xa0000000,
1673
-
0x20000000,
1674
-
0x21800000,
1675
-
0x21e00000,
1676
-
0x20400000,
1677
-
0x20500000,
1678
-
0x205a0000,
1679
-
0x20a00000,
1680
-
0x202fa000,
1681
-
0x202f9000,
1682
-
0x202ea000,
1683
-
0x202da000,
1684
-
0x202e2000,
1685
-
0x202f2000,
1686
-
};
1687
-
1688
-
u32 MCD_funcDescTab13[] = {
1689
-
0x00000000,
1690
-
0x00000000,
1691
-
0x00000000,
1692
-
0x00000000,
1693
-
0x00000000,
1694
-
0x00000000,
1695
-
0x00000000,
1696
-
0x00000000,
1697
-
0x00000000,
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-
0x00000000,
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-
0x00000000,
1700
-
0x00000000,
1701
-
0x00000000,
1702
-
0x00000000,
1703
-
0x00000000,
1704
-
0x00000000,
1705
-
0x00000000,
1706
-
0x00000000,
1707
-
0x00000000,
1708
-
0x00000000,
1709
-
0x00000000,
1710
-
0x00000000,
1711
-
0x00000000,
1712
-
0x00000000,
1713
-
0x00000000,
1714
-
0x00000000,
1715
-
0x00000000,
1716
-
0x00000000,
1717
-
0x00000000,
1718
-
0x00000000,
1719
-
0x00000000,
1720
-
0x00000000,
1721
-
0x00000000,
1722
-
0x00000000,
1723
-
0x00000000,
1724
-
0x00000000,
1725
-
0x00000000,
1726
-
0x00000000,
1727
-
0x00000000,
1728
-
0x00000000,
1729
-
0x00000000,
1730
-
0x00000000,
1731
-
0x00000000,
1732
-
0x00000000,
1733
-
0x00000000,
1734
-
0x00000000,
1735
-
0x00000000,
1736
-
0x00000000,
1737
-
0xa0045670,
1738
-
0xa0000000,
1739
-
0xa0000000,
1740
-
0x20000000,
1741
-
0x21800000,
1742
-
0x21e00000,
1743
-
0x20400000,
1744
-
0x20500000,
1745
-
0x205a0000,
1746
-
0x20a00000,
1747
-
0x202fa000,
1748
-
0x202f9000,
1749
-
0x202ea000,
1750
-
0x202da000,
1751
-
0x202e2000,
1752
-
0x202f2000,
1753
-
};
1754
-
1755
-
u32 MCD_funcDescTab14[] = {
1756
-
0x00000000,
1757
-
0x00000000,
1758
-
0x00000000,
1759
-
0x00000000,
1760
-
0x00000000,
1761
-
0x00000000,
1762
-
0x00000000,
1763
-
0x00000000,
1764
-
0x00000000,
1765
-
0x00000000,
1766
-
0x00000000,
1767
-
0x00000000,
1768
-
0x00000000,
1769
-
0x00000000,
1770
-
0x00000000,
1771
-
0x00000000,
1772
-
0x00000000,
1773
-
0x00000000,
1774
-
0x00000000,
1775
-
0x00000000,
1776
-
0x00000000,
1777
-
0x00000000,
1778
-
0x00000000,
1779
-
0x00000000,
1780
-
0x00000000,
1781
-
0x00000000,
1782
-
0x00000000,
1783
-
0x00000000,
1784
-
0x00000000,
1785
-
0x00000000,
1786
-
0x00000000,
1787
-
0x00000000,
1788
-
0x00000000,
1789
-
0x00000000,
1790
-
0x00000000,
1791
-
0x00000000,
1792
-
0x00000000,
1793
-
0x00000000,
1794
-
0x00000000,
1795
-
0x00000000,
1796
-
0x00000000,
1797
-
0x00000000,
1798
-
0x00000000,
1799
-
0x00000000,
1800
-
0x00000000,
1801
-
0x00000000,
1802
-
0x00000000,
1803
-
0x00000000,
1804
-
0xa0045670,
1805
-
0xa0000000,
1806
-
0xa0000000,
1807
-
0x20000000,
1808
-
0x21800000,
1809
-
0x21e00000,
1810
-
0x20400000,
1811
-
0x20500000,
1812
-
0x205a0000,
1813
-
0x20a00000,
1814
-
0x202fa000,
1815
-
0x202f9000,
1816
-
0x202ea000,
1817
-
0x202da000,
1818
-
0x202e2000,
1819
-
0x202f2000,
1820
-
};
1821
-
1822
-
u32 MCD_funcDescTab15[] = {
1823
-
0x00000000,
1824
-
0x00000000,
1825
-
0x00000000,
1826
-
0x00000000,
1827
-
0x00000000,
1828
-
0x00000000,
1829
-
0x00000000,
1830
-
0x00000000,
1831
-
0x00000000,
1832
-
0x00000000,
1833
-
0x00000000,
1834
-
0x00000000,
1835
-
0x00000000,
1836
-
0x00000000,
1837
-
0x00000000,
1838
-
0x00000000,
1839
-
0x00000000,
1840
-
0x00000000,
1841
-
0x00000000,
1842
-
0x00000000,
1843
-
0x00000000,
1844
-
0x00000000,
1845
-
0x00000000,
1846
-
0x00000000,
1847
-
0x00000000,
1848
-
0x00000000,
1849
-
0x00000000,
1850
-
0x00000000,
1851
-
0x00000000,
1852
-
0x00000000,
1853
-
0x00000000,
1854
-
0x00000000,
1855
-
0x00000000,
1856
-
0x00000000,
1857
-
0x00000000,
1858
-
0x00000000,
1859
-
0x00000000,
1860
-
0x00000000,
1861
-
0x00000000,
1862
-
0x00000000,
1863
-
0x00000000,
1864
-
0x00000000,
1865
-
0x00000000,
1866
-
0x00000000,
1867
-
0x00000000,
1868
-
0x00000000,
1869
-
0x00000000,
1870
-
0x00000000,
1871
-
0xa0045670,
1872
-
0xa0000000,
1873
-
0xa0000000,
1874
-
0x20000000,
1875
-
0x21800000,
1876
-
0x21e00000,
1877
-
0x20400000,
1878
-
0x20500000,
1879
-
0x205a0000,
1880
-
0x20a00000,
1881
-
0x202fa000,
1882
-
0x202f9000,
1883
-
0x202ea000,
1884
-
0x202da000,
1885
-
0x202e2000,
1886
-
0x202f2000,
1887
-
};
1888
-
#endif /*MCD_INCLUDE_EU */
1889
-
1890
-
u32 MCD_contextSave0[128]; /* Task 0 context save space */
1891
-
u32 MCD_contextSave1[128]; /* Task 1 context save space */
1892
-
u32 MCD_contextSave2[128]; /* Task 2 context save space */
1893
-
u32 MCD_contextSave3[128]; /* Task 3 context save space */
1894
-
u32 MCD_contextSave4[128]; /* Task 4 context save space */
1895
-
u32 MCD_contextSave5[128]; /* Task 5 context save space */
1896
-
u32 MCD_contextSave6[128]; /* Task 6 context save space */
1897
-
u32 MCD_contextSave7[128]; /* Task 7 context save space */
1898
-
u32 MCD_contextSave8[128]; /* Task 8 context save space */
1899
-
u32 MCD_contextSave9[128]; /* Task 9 context save space */
1900
-
u32 MCD_contextSave10[128]; /* Task 10 context save space */
1901
-
u32 MCD_contextSave11[128]; /* Task 11 context save space */
1902
-
u32 MCD_contextSave12[128]; /* Task 12 context save space */
1903
-
u32 MCD_contextSave13[128]; /* Task 13 context save space */
1904
-
u32 MCD_contextSave14[128]; /* Task 14 context save space */
1905
-
u32 MCD_contextSave15[128]; /* Task 15 context save space */
1906
-
1907
-
u32 MCD_ChainNoEu_TDT[];
1908
-
u32 MCD_SingleNoEu_TDT[];
1909
-
#ifdef MCD_INCLUDE_EU
1910
-
u32 MCD_ChainEu_TDT[];
1911
-
u32 MCD_SingleEu_TDT[];
1912
-
#endif
1913
-
u32 MCD_ENetRcv_TDT[];
1914
-
u32 MCD_ENetXmit_TDT[];
1915
-
1916
-
u32 MCD_modelTaskTableSrc[] = {
1917
-
(u32) MCD_ChainNoEu_TDT,
1918
-
(u32) & ((u8 *) MCD_ChainNoEu_TDT)[0x0000016c],
1919
-
0x00000000,
1920
-
0x00000000,
1921
-
0x00000000,
1922
-
0x00000000,
1923
-
0x00000000,
1924
-
0x00000000,
1925
-
(u32) MCD_SingleNoEu_TDT,
1926
-
(u32) & ((u8 *) MCD_SingleNoEu_TDT)[0x000000d4],
1927
-
0x00000000,
1928
-
0x00000000,
1929
-
0x00000000,
1930
-
0x00000000,
1931
-
0x00000000,
1932
-
0x00000000,
1933
-
#ifdef MCD_INCLUDE_EU
1934
-
(u32) MCD_ChainEu_TDT,
1935
-
(u32) & ((u8 *) MCD_ChainEu_TDT)[0x000001b4],
1936
-
0x00000000,
1937
-
0x00000000,
1938
-
0x00000000,
1939
-
0x00000000,
1940
-
0x00000000,
1941
-
0x00000000,
1942
-
(u32) MCD_SingleEu_TDT,
1943
-
(u32) & ((u8 *) MCD_SingleEu_TDT)[0x00000124],
1944
-
0x00000000,
1945
-
0x00000000,
1946
-
0x00000000,
1947
-
0x00000000,
1948
-
0x00000000,
1949
-
0x00000000,
1950
-
#endif
1951
-
(u32) MCD_ENetRcv_TDT,
1952
-
(u32) & ((u8 *) MCD_ENetRcv_TDT)[0x0000009c],
1953
-
0x00000000,
1954
-
0x00000000,
1955
-
0x00000000,
1956
-
0x00000000,
1957
-
0x00000000,
1958
-
0x00000000,
1959
-
(u32) MCD_ENetXmit_TDT,
1960
-
(u32) & ((u8 *) MCD_ENetXmit_TDT)[0x000000d0],
1961
-
0x00000000,
1962
-
0x00000000,
1963
-
0x00000000,
1964
-
0x00000000,
1965
-
0x00000000,
1966
-
0x00000000,
1967
-
};
1968
-
1969
-
u32 MCD_ChainNoEu_TDT[] = {
1970
-
0x80004000,
1971
-
0x8118801b,
1972
-
0xb8c60018,
1973
-
0x10002b10,
1974
-
0x7000000d,
1975
-
0x018cf89f,
1976
-
0x6000000a,
1977
-
0x080cf89f,
1978
-
0x000001f8,
1979
-
0x98180364,
1980
-
0x8118801b,
1981
-
0xf8c6001a,
1982
-
0xb8c6601b,
1983
-
0x10002710,
1984
-
0x00000f18,
1985
-
0xb8c6001d,
1986
-
0x10001310,
1987
-
0x60000007,
1988
-
0x014cf88b,
1989
-
0x98c6001c,
1990
-
0x00000710,
1991
-
0x98c70018,
1992
-
0x10001f10,
1993
-
0x0000c818,
1994
-
0x000001f8,
1995
-
0xc1476018,
1996
-
0xc003231d,
1997
-
0x811a601b,
1998
-
0xc1862102,
1999
-
0x849be009,
2000
-
0x03fed7b8,
2001
-
0xda9b001b,
2002
-
0x9b9be01b,
2003
-
0x1000cb20,
2004
-
0x70000006,
2005
-
0x088cf88f,
2006
-
0x1000cb28,
2007
-
0x70000006,
2008
-
0x088cf88f,
2009
-
0x1000cb30,
2010
-
0x70000006,
2011
-
0x088cf88f,
2012
-
0x1000cb38,
2013
-
0x0000c728,
2014
-
0x000001f8,
2015
-
0xc1476018,
2016
-
0xc003241d,
2017
-
0x811a601b,
2018
-
0xda9b001b,
2019
-
0x9b9be01b,
2020
-
0x0000d3a0,
2021
-
0xc1862102,
2022
-
0x849be009,
2023
-
0x0bfed7b8,
2024
-
0xda9b001b,
2025
-
0x9b9be01b,
2026
-
0x1000cb20,
2027
-
0x70000006,
2028
-
0x088cf88f,
2029
-
0x1000cb28,
2030
-
0x70000006,
2031
-
0x088cf88f,
2032
-
0x1000cb30,
2033
-
0x70000006,
2034
-
0x088cf88f,
2035
-
0x1000cb38,
2036
-
0x0000c728,
2037
-
0x000001f8,
2038
-
0x8118801b,
2039
-
0xd8c60018,
2040
-
0x98c6601c,
2041
-
0x6000000b,
2042
-
0x0c8cfc9f,
2043
-
0x000001f8,
2044
-
0xa146001e,
2045
-
0x10000b08,
2046
-
0x10002050,
2047
-
0xb8c60018,
2048
-
0x10002b10,
2049
-
0x7000000a,
2050
-
0x080cf89f,
2051
-
0x6000000d,
2052
-
0x018cf89f,
2053
-
0x000001f8,
2054
-
0x8618801b,
2055
-
0x7000000e,
2056
-
0x084cf21f,
2057
-
0xd8990336,
2058
-
0x8019801b,
2059
-
0x040001f8,
2060
-
0x000001f8,
2061
-
0x000001f8,
2062
-
};
2063
-
2064
-
u32 MCD_SingleNoEu_TDT[] = {
2065
-
0x8198001b,
2066
-
0x7000000d,
2067
-
0x080cf81f,
2068
-
0x8198801b,
2069
-
0x6000000e,
2070
-
0x084cf85f,
2071
-
0x000001f8,
2072
-
0x8298001b,
2073
-
0x7000000d,
2074
-
0x010cf81f,
2075
-
0x6000000e,
2076
-
0x018cf81f,
2077
-
0xc202601b,
2078
-
0xc002221c,
2079
-
0x809a601b,
2080
-
0xc10420c2,
2081
-
0x839be009,
2082
-
0x03fed7b8,
2083
-
0xda9b001b,
2084
-
0x9b9be01b,
2085
-
0x70000006,
2086
-
0x088cf889,
2087
-
0x1000cb28,
2088
-
0x70000006,
2089
-
0x088cf889,
2090
-
0x1000cb30,
2091
-
0x70000006,
2092
-
0x088cf889,
2093
-
0x0000cb38,
2094
-
0x000001f8,
2095
-
0xc202601b,
2096
-
0xc002229c,
2097
-
0x809a601b,
2098
-
0xda9b001b,
2099
-
0x9b9be01b,
2100
-
0x0000d3a0,
2101
-
0xc10420c2,
2102
-
0x839be009,
2103
-
0x0bfed7b8,
2104
-
0xda9b001b,
2105
-
0x9b9be01b,
2106
-
0x70000006,
2107
-
0x088cf889,
2108
-
0x1000cb28,
2109
-
0x70000006,
2110
-
0x088cf889,
2111
-
0x1000cb30,
2112
-
0x70000006,
2113
-
0x088cf889,
2114
-
0x0000cb38,
2115
-
0x000001f8,
2116
-
0xc318022d,
2117
-
0x8018801b,
2118
-
0x040001f8,
2119
-
};
2120
-
2121
-
#ifdef MCD_INCLUDE_EU
2122
-
u32 MCD_ChainEu_TDT[] = {
2123
-
0x80004000,
2124
-
0x8198801b,
2125
-
0xb8c68018,
2126
-
0x10002f10,
2127
-
0x7000000d,
2128
-
0x01ccf89f,
2129
-
0x6000000a,
2130
-
0x080cf89f,
2131
-
0x000001f8,
2132
-
0x981803a4,
2133
-
0x8198801b,
2134
-
0xf8c6801a,
2135
-
0xb8c6e01b,
2136
-
0x10002b10,
2137
-
0x00001318,
2138
-
0xb8c6801d,
2139
-
0x10001710,
2140
-
0x60000007,
2141
-
0x018cf88c,
2142
-
0x98c6801c,
2143
-
0x00000b10,
2144
-
0x98c78018,
2145
-
0x10002310,
2146
-
0x0000c820,
2147
-
0x000001f8,
2148
-
0x8698801b,
2149
-
0x7000000f,
2150
-
0x084cf2df,
2151
-
0xd899042d,
2152
-
0x8019801b,
2153
-
0x60000003,
2154
-
0x2cd7c7df,
2155
-
0xd8990364,
2156
-
0x8019801b,
2157
-
0x60000003,
2158
-
0x2c17c7df,
2159
-
0x000001f8,
2160
-
0xc1c7e018,
2161
-
0xc003a35e,
2162
-
0x819a601b,
2163
-
0xc206a142,
2164
-
0x851be009,
2165
-
0x63fe0000,
2166
-
0x0d4cfddf,
2167
-
0xda9b001b,
2168
-
0x9b9be01b,
2169
-
0x70000002,
2170
-
0x004cf81f,
2171
-
0x1000cb20,
2172
-
0x70000006,
2173
-
0x088cf891,
2174
-
0x1000cb28,
2175
-
0x70000006,
2176
-
0x088cf891,
2177
-
0x1000cb30,
2178
-
0x70000006,
2179
-
0x088cf891,
2180
-
0x1000cb38,
2181
-
0x0000c728,
2182
-
0x000001f8,
2183
-
0xc1c7e018,
2184
-
0xc003a49e,
2185
-
0x819a601b,
2186
-
0xda9b001b,
2187
-
0x9b9be01b,
2188
-
0x0000d3a0,
2189
-
0xc206a142,
2190
-
0x851be009,
2191
-
0x6bfe0000,
2192
-
0x0d4cfddf,
2193
-
0xda9b001b,
2194
-
0x9b9be01b,
2195
-
0x70000002,
2196
-
0x004cf81f,
2197
-
0x1000cb20,
2198
-
0x70000006,
2199
-
0x088cf891,
2200
-
0x1000cb28,
2201
-
0x70000006,
2202
-
0x088cf891,
2203
-
0x1000cb30,
2204
-
0x70000006,
2205
-
0x088cf891,
2206
-
0x1000cb38,
2207
-
0x0000c728,
2208
-
0x000001f8,
2209
-
0x8198801b,
2210
-
0xd8c68018,
2211
-
0x98c6e01c,
2212
-
0x6000000b,
2213
-
0x0c8cfc9f,
2214
-
0x0000cc08,
2215
-
0xa1c6801e,
2216
-
0x10000f08,
2217
-
0x10002458,
2218
-
0xb8c68018,
2219
-
0x10002f10,
2220
-
0x7000000a,
2221
-
0x080cf89f,
2222
-
0x6000000d,
2223
-
0x01ccf89f,
2224
-
0x000001f8,
2225
-
0x8698801b,
2226
-
0x7000000e,
2227
-
0x084cf25f,
2228
-
0xd899037f,
2229
-
0x8019801b,
2230
-
0x040001f8,
2231
-
0x000001f8,
2232
-
0x000001f8,
2233
-
};
2234
-
2235
-
u32 MCD_SingleEu_TDT[] = {
2236
-
0x8218001b,
2237
-
0x7000000d,
2238
-
0x080cf81f,
2239
-
0x8218801b,
2240
-
0x6000000e,
2241
-
0x084cf85f,
2242
-
0x000001f8,
2243
-
0x8318001b,
2244
-
0x7000000d,
2245
-
0x014cf81f,
2246
-
0x6000000e,
2247
-
0x01ccf81f,
2248
-
0x8498001b,
2249
-
0x7000000f,
2250
-
0x080cf19f,
2251
-
0xd81882a4,
2252
-
0x8019001b,
2253
-
0x60000003,
2254
-
0x2c97c7df,
2255
-
0xd818826d,
2256
-
0x8019001b,
2257
-
0x60000003,
2258
-
0x2c17c7df,
2259
-
0x000001f8,
2260
-
0xc282e01b,
2261
-
0xc002a25e,
2262
-
0x811a601b,
2263
-
0xc184a102,
2264
-
0x841be009,
2265
-
0x63fe0000,
2266
-
0x0d4cfddf,
2267
-
0xda9b001b,
2268
-
0x9b9be01b,
2269
-
0x70000002,
2270
-
0x004cf99f,
2271
-
0x70000006,
2272
-
0x088cf88b,
2273
-
0x1000cb28,
2274
-
0x70000006,
2275
-
0x088cf88b,
2276
-
0x1000cb30,
2277
-
0x70000006,
2278
-
0x088cf88b,
2279
-
0x0000cb38,
2280
-
0x000001f8,
2281
-
0xc282e01b,
2282
-
0xc002a31e,
2283
-
0x811a601b,
2284
-
0xda9b001b,
2285
-
0x9b9be01b,
2286
-
0x0000d3a0,
2287
-
0xc184a102,
2288
-
0x841be009,
2289
-
0x6bfe0000,
2290
-
0x0d4cfddf,
2291
-
0xda9b001b,
2292
-
0x9b9be01b,
2293
-
0x70000002,
2294
-
0x004cf99f,
2295
-
0x70000006,
2296
-
0x088cf88b,
2297
-
0x1000cb28,
2298
-
0x70000006,
2299
-
0x088cf88b,
2300
-
0x1000cb30,
2301
-
0x70000006,
2302
-
0x088cf88b,
2303
-
0x0000cb38,
2304
-
0x000001f8,
2305
-
0x8144801c,
2306
-
0x0000c008,
2307
-
0xc398027f,
2308
-
0x8018801b,
2309
-
0x040001f8,
2310
-
};
2311
-
#endif
2312
-
u32 MCD_ENetRcv_TDT[] = {
2313
-
0x80004000,
2314
-
0x81988000,
2315
-
0x10000788,
2316
-
0x6000000a,
2317
-
0x080cf05f,
2318
-
0x98180209,
2319
-
0x81c40004,
2320
-
0x7000000e,
2321
-
0x010cf05f,
2322
-
0x7000000c,
2323
-
0x01ccf05f,
2324
-
0x70000004,
2325
-
0x014cf049,
2326
-
0x70000004,
2327
-
0x004cf04a,
2328
-
0x00000b88,
2329
-
0xc4030150,
2330
-
0x8119e012,
2331
-
0x03e0cf90,
2332
-
0x81188000,
2333
-
0x000ac788,
2334
-
0xc4030000,
2335
-
0x8199e000,
2336
-
0x70000004,
2337
-
0x084cfc8b,
2338
-
0x60000005,
2339
-
0x0cccf841,
2340
-
0x81c60000,
2341
-
0xc399021b,
2342
-
0x80198000,
2343
-
0x00008400,
2344
-
0x00000f08,
2345
-
0x81988000,
2346
-
0x10000788,
2347
-
0x6000000a,
2348
-
0x080cf05f,
2349
-
0xc2188209,
2350
-
0x80190000,
2351
-
0x040001f8,
2352
-
0x000001f8,
2353
-
};
2354
-
2355
-
u32 MCD_ENetXmit_TDT[] = {
2356
-
0x80004000,
2357
-
0x81988000,
2358
-
0x10000788,
2359
-
0x6000000a,
2360
-
0x080cf05f,
2361
-
0x98180309,
2362
-
0x80004003,
2363
-
0x81c60004,
2364
-
0x7000000e,
2365
-
0x014cf05f,
2366
-
0x7000000c,
2367
-
0x028cf05f,
2368
-
0x7000000d,
2369
-
0x018cf05f,
2370
-
0x70000004,
2371
-
0x01ccf04d,
2372
-
0x10000b90,
2373
-
0x60000004,
2374
-
0x020cf0a1,
2375
-
0xc3188312,
2376
-
0x83c70000,
2377
-
0x00001f10,
2378
-
0xc583a3c3,
2379
-
0x81042325,
2380
-
0x03e0c798,
2381
-
0xd8990000,
2382
-
0x9999e000,
2383
-
0x000acf98,
2384
-
0xd8992306,
2385
-
0x9999e03f,
2386
-
0x03eac798,
2387
-
0xd8990000,
2388
-
0x9999e000,
2389
-
0x000acf98,
2390
-
0xd8990000,
2391
-
0x99832302,
2392
-
0x0beac798,
2393
-
0x81988000,
2394
-
0x6000000b,
2395
-
0x0c4cfc5f,
2396
-
0x81c80000,
2397
-
0xc5190312,
2398
-
0x80198000,
2399
-
0x00008400,
2400
-
0x00000f08,
2401
-
0x81988000,
2402
-
0x10000788,
2403
-
0x6000000a,
2404
-
0x080cf05f,
2405
-
0xc2988309,
2406
-
0x80190000,
2407
-
0x040001f8,
2408
-
0x000001f8,
2409
-
};
2410
-
2411
-
#ifdef MCD_INCLUDE_EU
2412
-
MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
2413
-
#endif
-225
drivers/dma/MCD_tasksInit.c
-225
drivers/dma/MCD_tasksInit.c
···
1
-
// SPDX-License-Identifier: GPL-2.0+
2
-
/*
3
-
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4
-
*/
5
-
6
-
#include <common.h>
7
-
8
-
/* Functions for initializing variable tables of different types of tasks. */
9
-
10
-
/*
11
-
* Do not edit!
12
-
*/
13
-
14
-
#include <MCD_dma.h>
15
-
16
-
extern dmaRegs *MCD_dmaBar;
17
-
18
-
/* Task 0 */
19
-
20
-
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
21
-
int xferSize, short xferSizeIncr, int *cSave,
22
-
volatile TaskTableEntry * taskTable, int channel)
23
-
{
24
-
volatile TaskTableEntry *taskChan = taskTable + channel;
25
-
26
-
MCD_SET_VAR(taskChan, 2, (u32) currBD); /* var[2] */
27
-
MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
28
-
MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
29
-
MCD_SET_VAR(taskChan, 11, (u32) xferSize); /* var[11] */
30
-
MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
31
-
MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
32
-
MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
33
-
MCD_SET_VAR(taskChan, 3, (u32) 0x00000000); /* var[3] */
34
-
MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
35
-
MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
36
-
MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
37
-
MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
38
-
MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
39
-
MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
40
-
MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */
41
-
MCD_SET_VAR(taskChan, 12, (u32) 0x00000000); /* var[12] */
42
-
MCD_SET_VAR(taskChan, 13, (u32) 0x80000000); /* var[13] */
43
-
MCD_SET_VAR(taskChan, 14, (u32) 0x00000010); /* var[14] */
44
-
MCD_SET_VAR(taskChan, 15, (u32) 0x00000004); /* var[15] */
45
-
MCD_SET_VAR(taskChan, 16, (u32) 0x08000000); /* var[16] */
46
-
MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
47
-
MCD_SET_VAR(taskChan, 28, (u32) 0x80000000); /* inc[4] */
48
-
MCD_SET_VAR(taskChan, 29, (u32) 0x80000001); /* inc[5] */
49
-
MCD_SET_VAR(taskChan, 30, (u32) 0x40000000); /* inc[6] */
50
-
51
-
/* Set the task's Enable bit in its Task Control Register */
52
-
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
53
-
}
54
-
55
-
/* Task 1 */
56
-
57
-
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
58
-
short destIncr, int dmaSize, short xferSizeIncr,
59
-
int flags, int *currBD, int *cSave,
60
-
volatile TaskTableEntry * taskTable, int channel)
61
-
{
62
-
volatile TaskTableEntry *taskChan = taskTable + channel;
63
-
64
-
MCD_SET_VAR(taskChan, 7, (u32) srcAddr); /* var[7] */
65
-
MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
66
-
MCD_SET_VAR(taskChan, 2, (u32) destAddr); /* var[2] */
67
-
MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
68
-
MCD_SET_VAR(taskChan, 3, (u32) dmaSize); /* var[3] */
69
-
MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
70
-
MCD_SET_VAR(taskChan, 5, (u32) flags); /* var[5] */
71
-
MCD_SET_VAR(taskChan, 1, (u32) currBD); /* var[1] */
72
-
MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
73
-
MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
74
-
MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
75
-
MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
76
-
MCD_SET_VAR(taskChan, 9, (u32) 0x00000004); /* var[9] */
77
-
MCD_SET_VAR(taskChan, 10, (u32) 0x08000000); /* var[10] */
78
-
MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
79
-
MCD_SET_VAR(taskChan, 28, (u32) 0x80000001); /* inc[4] */
80
-
MCD_SET_VAR(taskChan, 29, (u32) 0x40000000); /* inc[5] */
81
-
82
-
/* Set the task's Enable bit in its Task Control Register */
83
-
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
84
-
}
85
-
86
-
/* Task 2 */
87
-
88
-
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
89
-
int xferSize, short xferSizeIncr, int *cSave,
90
-
volatile TaskTableEntry * taskTable, int channel)
91
-
{
92
-
volatile TaskTableEntry *taskChan = taskTable + channel;
93
-
94
-
MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */
95
-
MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
96
-
MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
97
-
MCD_SET_VAR(taskChan, 12, (u32) xferSize); /* var[12] */
98
-
MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
99
-
MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
100
-
MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
101
-
MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */
102
-
MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
103
-
MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
104
-
MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
105
-
MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
106
-
MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
107
-
MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
108
-
MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */
109
-
MCD_SET_VAR(taskChan, 11, (u32) 0x00000000); /* var[11] */
110
-
MCD_SET_VAR(taskChan, 13, (u32) 0x00000000); /* var[13] */
111
-
MCD_SET_VAR(taskChan, 14, (u32) 0x80000000); /* var[14] */
112
-
MCD_SET_VAR(taskChan, 15, (u32) 0x00000010); /* var[15] */
113
-
MCD_SET_VAR(taskChan, 16, (u32) 0x00000001); /* var[16] */
114
-
MCD_SET_VAR(taskChan, 17, (u32) 0x00000004); /* var[17] */
115
-
MCD_SET_VAR(taskChan, 18, (u32) 0x08000000); /* var[18] */
116
-
MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
117
-
MCD_SET_VAR(taskChan, 28, (u32) 0x80000000); /* inc[4] */
118
-
MCD_SET_VAR(taskChan, 29, (u32) 0xc0000000); /* inc[5] */
119
-
MCD_SET_VAR(taskChan, 30, (u32) 0x80000001); /* inc[6] */
120
-
MCD_SET_VAR(taskChan, 31, (u32) 0x40000000); /* inc[7] */
121
-
122
-
/* Set the task's Enable bit in its Task Control Register */
123
-
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
124
-
}
125
-
126
-
/* Task 3 */
127
-
128
-
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
129
-
short destIncr, int dmaSize, short xferSizeIncr,
130
-
int flags, int *currBD, int *cSave,
131
-
volatile TaskTableEntry * taskTable, int channel)
132
-
{
133
-
volatile TaskTableEntry *taskChan = taskTable + channel;
134
-
135
-
MCD_SET_VAR(taskChan, 8, (u32) srcAddr); /* var[8] */
136
-
MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
137
-
MCD_SET_VAR(taskChan, 3, (u32) destAddr); /* var[3] */
138
-
MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
139
-
MCD_SET_VAR(taskChan, 4, (u32) dmaSize); /* var[4] */
140
-
MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
141
-
MCD_SET_VAR(taskChan, 6, (u32) flags); /* var[6] */
142
-
MCD_SET_VAR(taskChan, 2, (u32) currBD); /* var[2] */
143
-
MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
144
-
MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
145
-
MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
146
-
MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
147
-
MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
148
-
MCD_SET_VAR(taskChan, 10, (u32) 0x00000001); /* var[10] */
149
-
MCD_SET_VAR(taskChan, 11, (u32) 0x00000004); /* var[11] */
150
-
MCD_SET_VAR(taskChan, 12, (u32) 0x08000000); /* var[12] */
151
-
MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
152
-
MCD_SET_VAR(taskChan, 28, (u32) 0xc0000000); /* inc[4] */
153
-
MCD_SET_VAR(taskChan, 29, (u32) 0x80000000); /* inc[5] */
154
-
MCD_SET_VAR(taskChan, 30, (u32) 0x80000001); /* inc[6] */
155
-
MCD_SET_VAR(taskChan, 31, (u32) 0x40000000); /* inc[7] */
156
-
157
-
/* Set the task's Enable bit in its Task Control Register */
158
-
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
159
-
}
160
-
161
-
/* Task 4 */
162
-
163
-
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
164
-
volatile TaskTableEntry * taskTable, int channel)
165
-
{
166
-
volatile TaskTableEntry *taskChan = taskTable + channel;
167
-
168
-
MCD_SET_VAR(taskChan, 0, (u32) bDBase); /* var[0] */
169
-
MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */
170
-
MCD_SET_VAR(taskChan, 6, (u32) rcvFifoPtr); /* var[6] */
171
-
MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
172
-
MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */
173
-
MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
174
-
MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
175
-
MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
176
-
MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
177
-
MCD_SET_VAR(taskChan, 9, (u32) 0x0000ffff); /* var[9] */
178
-
MCD_SET_VAR(taskChan, 10, (u32) 0x30000000); /* var[10] */
179
-
MCD_SET_VAR(taskChan, 11, (u32) 0x0fffffff); /* var[11] */
180
-
MCD_SET_VAR(taskChan, 12, (u32) 0x00000008); /* var[12] */
181
-
MCD_SET_VAR(taskChan, 24, (u32) 0x00000000); /* inc[0] */
182
-
MCD_SET_VAR(taskChan, 25, (u32) 0x60000000); /* inc[1] */
183
-
MCD_SET_VAR(taskChan, 26, (u32) 0x20000004); /* inc[2] */
184
-
MCD_SET_VAR(taskChan, 27, (u32) 0x40000000); /* inc[3] */
185
-
186
-
/* Set the task's Enable bit in its Task Control Register */
187
-
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
188
-
}
189
-
190
-
/* Task 5 */
191
-
192
-
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
193
-
volatile TaskTableEntry * taskTable, int channel)
194
-
{
195
-
volatile TaskTableEntry *taskChan = taskTable + channel;
196
-
197
-
MCD_SET_VAR(taskChan, 0, (u32) bDBase); /* var[0] */
198
-
MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */
199
-
MCD_SET_VAR(taskChan, 11, (u32) xmitFifoPtr); /* var[11] */
200
-
MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
201
-
MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */
202
-
MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
203
-
MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
204
-
MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
205
-
MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
206
-
MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
207
-
MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
208
-
MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */
209
-
MCD_SET_VAR(taskChan, 12, (u32) 0x00000000); /* var[12] */
210
-
MCD_SET_VAR(taskChan, 13, (u32) 0x0000ffff); /* var[13] */
211
-
MCD_SET_VAR(taskChan, 14, (u32) 0xffffffff); /* var[14] */
212
-
MCD_SET_VAR(taskChan, 15, (u32) 0x00000004); /* var[15] */
213
-
MCD_SET_VAR(taskChan, 16, (u32) 0x00000008); /* var[16] */
214
-
MCD_SET_VAR(taskChan, 24, (u32) 0x00000000); /* inc[0] */
215
-
MCD_SET_VAR(taskChan, 25, (u32) 0x60000000); /* inc[1] */
216
-
MCD_SET_VAR(taskChan, 26, (u32) 0x40000000); /* inc[2] */
217
-
MCD_SET_VAR(taskChan, 27, (u32) 0xc000fffc); /* inc[3] */
218
-
MCD_SET_VAR(taskChan, 28, (u32) 0xe0000004); /* inc[4] */
219
-
MCD_SET_VAR(taskChan, 29, (u32) 0x80000000); /* inc[5] */
220
-
MCD_SET_VAR(taskChan, 30, (u32) 0x4000ffff); /* inc[6] */
221
-
MCD_SET_VAR(taskChan, 31, (u32) 0xe0000001); /* inc[7] */
222
-
223
-
/* Set the task's Enable bit in its Task Control Register */
224
-
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
225
-
}
-1
drivers/dma/Makefile
-1
drivers/dma/Makefile
-8
drivers/net/Kconfig
-8
drivers/net/Kconfig
···
471
471
depends on MCFFEC
472
472
bool "Invalidate icache during ethernet operations"
473
473
474
-
config FSLDMAFEC
475
-
bool "ColdFire DMA Ethernet Support"
476
-
select PHYLIB
477
-
select SYS_DISCOVER_PHY
478
-
help
479
-
This driver supports the network interface units in the
480
-
ColdFire family.
481
-
482
474
config KS8851_MLL
483
475
bool "Microchip KS8851-MLL controller driver"
484
476
help
-1
drivers/net/Makefile
-1
drivers/net/Makefile
···
37
37
obj-$(CONFIG_FEC_MXC) += fec_mxc.o
38
38
obj-$(CONFIG_FMAN_ENET) += fm/
39
39
obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
40
-
obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
41
40
obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o
42
41
obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o
43
42
obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
-592
drivers/net/fsl_mcdmafec.c
-592
drivers/net/fsl_mcdmafec.c
···
1
-
// SPDX-License-Identifier: GPL-2.0+
2
-
/*
3
-
* (C) Copyright 2000-2004
4
-
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5
-
*
6
-
* (C) Copyright 2007 Freescale Semiconductor, Inc.
7
-
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8
-
*
9
-
* Conversion to DM
10
-
* (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
11
-
*/
12
-
13
-
#include <common.h>
14
-
#include <env.h>
15
-
#include <hang.h>
16
-
#include <malloc.h>
17
-
#include <command.h>
18
-
#include <config.h>
19
-
#include <net.h>
20
-
#include <miiphy.h>
21
-
#include <asm/global_data.h>
22
-
#include <linux/delay.h>
23
-
#include <linux/mii.h>
24
-
#include <asm/immap.h>
25
-
#include <asm/fsl_mcdmafec.h>
26
-
27
-
#include "MCD_dma.h"
28
-
29
-
#undef ET_DEBUG
30
-
#undef MII_DEBUG
31
-
32
-
/* Ethernet Transmit and Receive Buffers */
33
-
#define DBUF_LENGTH 1520
34
-
#define PKT_MAXBUF_SIZE 1518
35
-
#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
36
-
37
-
/* RxBD bits definitions */
38
-
#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
39
-
BD_ENET_RX_OV | BD_ENET_RX_TR)
40
-
41
-
DECLARE_GLOBAL_DATA_PTR;
42
-
43
-
static void init_eth_info(struct fec_info_dma *info)
44
-
{
45
-
/* setup Receive and Transmit buffer descriptor */
46
-
#ifdef CFG_SYS_FEC_BUF_USE_SRAM
47
-
static u32 tmp;
48
-
49
-
if (info->index == 0)
50
-
tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
51
-
else
52
-
info->rxbd = (cbd_t *)DBUF_LENGTH;
53
-
54
-
info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
55
-
tmp = (u32)info->rxbd;
56
-
info->txbd =
57
-
(cbd_t *)((u32)info->txbd + tmp +
58
-
(PKTBUFSRX * sizeof(cbd_t)));
59
-
tmp = (u32)info->txbd;
60
-
info->txbuf =
61
-
(char *)((u32)info->txbuf + tmp +
62
-
(CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
63
-
tmp = (u32)info->txbuf;
64
-
#else
65
-
info->rxbd =
66
-
(cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
67
-
(PKTBUFSRX * sizeof(cbd_t)));
68
-
info->txbd =
69
-
(cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
70
-
(CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
71
-
info->txbuf =
72
-
(char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
73
-
#endif
74
-
75
-
#ifdef ET_DEBUG
76
-
printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
77
-
#endif
78
-
info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
79
-
}
80
-
81
-
static void fec_halt(struct udevice *dev)
82
-
{
83
-
struct fec_info_dma *info = dev_get_priv(dev);
84
-
volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
85
-
int counter = 0xffff;
86
-
87
-
/* issue graceful stop command to the FEC transmitter if necessary */
88
-
fecp->tcr |= FEC_TCR_GTS;
89
-
90
-
/* wait for graceful stop to register */
91
-
while ((counter--) && (!(fecp->eir & FEC_EIR_GRA)))
92
-
;
93
-
94
-
/* Disable DMA tasks */
95
-
MCD_killDma(info->tx_task);
96
-
MCD_killDma(info->rx_task);
97
-
98
-
/* Disable the Ethernet Controller */
99
-
fecp->ecr &= ~FEC_ECR_ETHER_EN;
100
-
101
-
/* Clear FIFO status registers */
102
-
fecp->rfsr &= FIFO_ERRSTAT;
103
-
fecp->tfsr &= FIFO_ERRSTAT;
104
-
105
-
fecp->frst = 0x01000000;
106
-
107
-
/* Issue a reset command to the FEC chip */
108
-
fecp->ecr |= FEC_ECR_RESET;
109
-
110
-
/* wait at least 20 clock cycles */
111
-
mdelay(10);
112
-
113
-
#ifdef ET_DEBUG
114
-
printf("Ethernet task stopped\n");
115
-
#endif
116
-
}
117
-
118
-
#ifdef ET_DEBUG
119
-
static void dbg_fec_regs(struct eth_device *dev)
120
-
{
121
-
struct fec_info_dma *info = dev->priv;
122
-
volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
123
-
124
-
printf("=====\n");
125
-
printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
126
-
printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
127
-
printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
128
-
printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
129
-
printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
130
-
printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
131
-
printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
132
-
printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
133
-
printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
134
-
printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
135
-
printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
136
-
printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
137
-
printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
138
-
printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
139
-
printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
140
-
printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
141
-
printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
142
-
printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
143
-
printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
144
-
printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
145
-
printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
146
-
printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
147
-
printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
148
-
printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
149
-
printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
150
-
printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
151
-
printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
152
-
printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
153
-
printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
154
-
printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
155
-
printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
156
-
printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
157
-
printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
158
-
printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
159
-
printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
160
-
}
161
-
#endif
162
-
163
-
static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd)
164
-
{
165
-
struct bd_info *bd = gd->bd;
166
-
167
-
if ((dup_spd >> 16) == FULL) {
168
-
/* Set maximum frame length */
169
-
fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
170
-
FEC_RCR_PROM | 0x100;
171
-
fecp->tcr = FEC_TCR_FDEN;
172
-
} else {
173
-
/* Half duplex mode */
174
-
fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
175
-
FEC_RCR_MII_MODE | FEC_RCR_DRT;
176
-
fecp->tcr &= ~FEC_TCR_FDEN;
177
-
}
178
-
179
-
if ((dup_spd & 0xFFFF) == _100BASET) {
180
-
#ifdef MII_DEBUG
181
-
printf("100Mbps\n");
182
-
#endif
183
-
bd->bi_ethspeed = 100;
184
-
} else {
185
-
#ifdef MII_DEBUG
186
-
printf("10Mbps\n");
187
-
#endif
188
-
bd->bi_ethspeed = 10;
189
-
}
190
-
}
191
-
192
-
static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac)
193
-
{
194
-
u8 curr_byte; /* byte for which to compute the CRC */
195
-
int byte; /* loop - counter */
196
-
int bit; /* loop - counter */
197
-
u32 crc = 0xffffffff; /* initial value */
198
-
199
-
for (byte = 0; byte < 6; byte++) {
200
-
curr_byte = mac[byte];
201
-
for (bit = 0; bit < 8; bit++) {
202
-
if ((curr_byte & 0x01) ^ (crc & 0x01)) {
203
-
crc >>= 1;
204
-
crc = crc ^ 0xedb88320;
205
-
} else {
206
-
crc >>= 1;
207
-
}
208
-
curr_byte >>= 1;
209
-
}
210
-
}
211
-
212
-
crc = crc >> 26;
213
-
214
-
/* Set individual hash table register */
215
-
if (crc >= 32) {
216
-
fecp->ialr = (1 << (crc - 32));
217
-
fecp->iaur = 0;
218
-
} else {
219
-
fecp->ialr = 0;
220
-
fecp->iaur = (1 << crc);
221
-
}
222
-
223
-
/* Set physical address */
224
-
fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
225
-
fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
226
-
227
-
/* Clear multicast address hash table */
228
-
fecp->gaur = 0;
229
-
fecp->galr = 0;
230
-
}
231
-
232
-
static int fec_init(struct udevice *dev)
233
-
{
234
-
struct fec_info_dma *info = dev_get_priv(dev);
235
-
volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
236
-
int rval, i;
237
-
uchar enetaddr[6];
238
-
239
-
#ifdef ET_DEBUG
240
-
printf("fec_init: iobase 0x%08x ...\n", info->iobase);
241
-
#endif
242
-
243
-
fecpin_setclear(info, 1);
244
-
fec_halt(dev);
245
-
246
-
mii_init();
247
-
set_fec_duplex_speed(fecp, info->dup_spd);
248
-
249
-
/* We use strictly polling mode only */
250
-
fecp->eimr = 0;
251
-
252
-
/* Clear any pending interrupt */
253
-
fecp->eir = 0xffffffff;
254
-
255
-
/* Set station address */
256
-
if (info->index == 0)
257
-
rval = eth_env_get_enetaddr("ethaddr", enetaddr);
258
-
else
259
-
rval = eth_env_get_enetaddr("eth1addr", enetaddr);
260
-
261
-
if (!rval) {
262
-
puts("Please set a valid MAC address\n");
263
-
return -EINVAL;
264
-
}
265
-
266
-
fec_set_hwaddr(fecp, enetaddr);
267
-
268
-
/* Set Opcode/Pause Duration Register */
269
-
fecp->opd = 0x00010020;
270
-
271
-
/* Setup Buffers and Buffer Descriptors */
272
-
info->rx_idx = 0;
273
-
info->tx_idx = 0;
274
-
275
-
/* Setup Receiver Buffer Descriptors (13.14.24.18)
276
-
* Settings: Empty, Wrap */
277
-
for (i = 0; i < PKTBUFSRX; i++) {
278
-
info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
279
-
info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
280
-
info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
281
-
}
282
-
info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
283
-
284
-
/* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
285
-
* Settings: Last, Tx CRC */
286
-
for (i = 0; i < CFG_SYS_TX_ETH_BUFFER; i++) {
287
-
info->txbd[i].cbd_sc = 0;
288
-
info->txbd[i].cbd_datlen = 0;
289
-
info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
290
-
}
291
-
info->txbd[CFG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
292
-
293
-
info->used_tbd_idx = 0;
294
-
info->clean_tbd_num = CFG_SYS_TX_ETH_BUFFER;
295
-
296
-
/* Set Rx FIFO alarm and granularity value */
297
-
fecp->rfcr = 0x0c000000;
298
-
fecp->rfar = 0x0000030c;
299
-
300
-
/* Set Tx FIFO granularity value */
301
-
fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
302
-
fecp->tfar = 0x00000080;
303
-
304
-
fecp->tfwr = 0x2;
305
-
fecp->ctcwr = 0x03000000;
306
-
307
-
/* Enable DMA receive task */
308
-
MCD_startDma(info->rx_task,
309
-
(s8 *)info->rxbd,
310
-
0,
311
-
(s8 *)&fecp->rfdr,
312
-
4,
313
-
0,
314
-
4,
315
-
info->rx_init,
316
-
info->rx_pri,
317
-
(MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),
318
-
(MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
319
-
);
320
-
321
-
/* Enable DMA tx task with no ready buffer descriptors */
322
-
MCD_startDma(info->tx_task,
323
-
(s8 *)info->txbd,
324
-
0,
325
-
(s8 *)&fecp->tfdr,
326
-
4,
327
-
0,
328
-
4,
329
-
info->tx_init,
330
-
info->tx_pri,
331
-
(MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),
332
-
(MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
333
-
);
334
-
335
-
/* Now enable the transmit and receive processing */
336
-
fecp->ecr |= FEC_ECR_ETHER_EN;
337
-
338
-
return 0;
339
-
}
340
-
341
-
static int mcdmafec_init(struct udevice *dev)
342
-
{
343
-
return fec_init(dev);
344
-
}
345
-
346
-
static int mcdmafec_send(struct udevice *dev, void *packet, int length)
347
-
{
348
-
struct fec_info_dma *info = dev_get_priv(dev);
349
-
cbd_t *p_tbd, *p_used_tbd;
350
-
u16 phy_status;
351
-
352
-
miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
353
-
354
-
/* process all the consumed TBDs */
355
-
while (info->clean_tbd_num < CFG_SYS_TX_ETH_BUFFER) {
356
-
p_used_tbd = &info->txbd[info->used_tbd_idx];
357
-
if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
358
-
#ifdef ET_DEBUG
359
-
printf("Cannot clean TBD %d, in use\n",
360
-
info->clean_tbd_num);
361
-
#endif
362
-
return 0;
363
-
}
364
-
365
-
/* clean this buffer descriptor */
366
-
if (info->used_tbd_idx == (CFG_SYS_TX_ETH_BUFFER - 1))
367
-
p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
368
-
else
369
-
p_used_tbd->cbd_sc = 0;
370
-
371
-
/* update some indeces for a correct handling of TBD ring */
372
-
info->clean_tbd_num++;
373
-
info->used_tbd_idx = (info->used_tbd_idx + 1)
374
-
% CFG_SYS_TX_ETH_BUFFER;
375
-
}
376
-
377
-
/* Check for valid length of data. */
378
-
if (length > 1500 || length <= 0)
379
-
return -1;
380
-
381
-
/* Check the number of vacant TxBDs. */
382
-
if (info->clean_tbd_num < 1) {
383
-
printf("No available TxBDs ...\n");
384
-
return -1;
385
-
}
386
-
387
-
/* Get the first TxBD to send the mac header */
388
-
p_tbd = &info->txbd[info->tx_idx];
389
-
p_tbd->cbd_datlen = length;
390
-
p_tbd->cbd_bufaddr = (u32)packet;
391
-
p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
392
-
info->tx_idx = (info->tx_idx + 1) % CFG_SYS_TX_ETH_BUFFER;
393
-
394
-
/* Enable DMA transmit task */
395
-
MCD_continDma(info->tx_task);
396
-
397
-
info->clean_tbd_num -= 1;
398
-
399
-
/* wait until frame is sent . */
400
-
while (p_tbd->cbd_sc & BD_ENET_TX_READY)
401
-
udelay(10);
402
-
403
-
return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
404
-
}
405
-
406
-
static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp)
407
-
{
408
-
struct fec_info_dma *info = dev_get_priv(dev);
409
-
volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
410
-
411
-
cbd_t *prbd = &info->rxbd[info->rx_idx];
412
-
u32 ievent;
413
-
int frame_length, len = 0;
414
-
415
-
/* Check if any critical events have happened */
416
-
ievent = fecp->eir;
417
-
if (ievent != 0) {
418
-
fecp->eir = ievent;
419
-
420
-
if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
421
-
printf("fec_recv: error\n");
422
-
fec_halt(dev);
423
-
fec_init(dev);
424
-
return 0;
425
-
}
426
-
427
-
if (ievent & FEC_EIR_HBERR) {
428
-
/* Heartbeat error */
429
-
fecp->tcr |= FEC_TCR_GTS;
430
-
}
431
-
432
-
if (ievent & FEC_EIR_GRA) {
433
-
/* Graceful stop complete */
434
-
if (fecp->tcr & FEC_TCR_GTS) {
435
-
printf("fec_recv: tcr_gts\n");
436
-
fec_halt(dev);
437
-
fecp->tcr &= ~FEC_TCR_GTS;
438
-
fec_init(dev);
439
-
}
440
-
}
441
-
}
442
-
443
-
if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
444
-
if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
445
-
!(prbd->cbd_sc & BD_ENET_RX_ERR) &&
446
-
((prbd->cbd_datlen - 4) > 14)) {
447
-
/* Get buffer address and size */
448
-
frame_length = prbd->cbd_datlen - 4;
449
-
450
-
/* Fill the buffer and pass it to upper layers */
451
-
net_process_received_packet((uchar *)prbd->cbd_bufaddr,
452
-
frame_length);
453
-
len = frame_length;
454
-
}
455
-
456
-
/* Reset buffer descriptor as empty */
457
-
if (info->rx_idx == (PKTBUFSRX - 1))
458
-
prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
459
-
else
460
-
prbd->cbd_sc = BD_ENET_RX_EMPTY;
461
-
462
-
prbd->cbd_datlen = PKTSIZE_ALIGN;
463
-
464
-
/* Now, we have an empty RxBD, restart the DMA receive task */
465
-
MCD_continDma(info->rx_task);
466
-
467
-
/* Increment BD count */
468
-
info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX;
469
-
}
470
-
471
-
return len;
472
-
}
473
-
474
-
static void mcdmafec_halt(struct udevice *dev)
475
-
{
476
-
fec_halt(dev);
477
-
}
478
-
479
-
static const struct eth_ops mcdmafec_ops = {
480
-
.start = mcdmafec_init,
481
-
.send = mcdmafec_send,
482
-
.recv = mcdmafec_recv,
483
-
.stop = mcdmafec_halt,
484
-
};
485
-
486
-
/*
487
-
* Boot sequence, called just after mcffec_of_to_plat,
488
-
* as DM way, it replaces old mcffec_initialize.
489
-
*/
490
-
static int mcdmafec_probe(struct udevice *dev)
491
-
{
492
-
struct fec_info_dma *info = dev_get_priv(dev);
493
-
struct eth_pdata *pdata = dev_get_plat(dev);
494
-
int node = dev_of_offset(dev);
495
-
int retval;
496
-
const u32 *val;
497
-
498
-
info->index = dev_seq(dev);
499
-
info->iobase = pdata->iobase;
500
-
info->miibase = pdata->iobase;
501
-
info->phy_addr = -1;
502
-
503
-
val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL);
504
-
if (val)
505
-
info->rx_task = fdt32_to_cpu(*val);
506
-
507
-
val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL);
508
-
if (val)
509
-
info->tx_task = fdt32_to_cpu(*val);
510
-
511
-
val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL);
512
-
if (val)
513
-
info->rx_pri = fdt32_to_cpu(*val);
514
-
515
-
val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL);
516
-
if (val)
517
-
info->tx_pri = fdt32_to_cpu(*val);
518
-
519
-
val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL);
520
-
if (val)
521
-
info->rx_init = fdt32_to_cpu(*val);
522
-
523
-
val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL);
524
-
if (val)
525
-
info->tx_init = fdt32_to_cpu(*val);
526
-
527
-
#ifdef CFG_SYS_FEC_BUF_USE_SRAM
528
-
u32 tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
529
-
#endif
530
-
init_eth_info(info);
531
-
532
-
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
533
-
info->bus = mdio_alloc();
534
-
if (!info->bus)
535
-
return -ENOMEM;
536
-
strlcpy(info->bus->name, dev->name, MDIO_NAME_LEN);
537
-
info->bus->read = mcffec_miiphy_read;
538
-
info->bus->write = mcffec_miiphy_write;
539
-
540
-
retval = mdio_register(info->bus);
541
-
if (retval < 0)
542
-
return retval;
543
-
#endif
544
-
545
-
return 0;
546
-
}
547
-
548
-
static int mcdmafec_remove(struct udevice *dev)
549
-
{
550
-
struct fec_info_dma *priv = dev_get_priv(dev);
551
-
552
-
mdio_unregister(priv->bus);
553
-
mdio_free(priv->bus);
554
-
555
-
return 0;
556
-
}
557
-
558
-
/*
559
-
* Boot sequence, called 1st
560
-
*/
561
-
static int mcdmafec_of_to_plat(struct udevice *dev)
562
-
{
563
-
struct eth_pdata *pdata = dev_get_plat(dev);
564
-
const u32 *val;
565
-
566
-
pdata->iobase = dev_read_addr(dev);
567
-
/* Default to 10Mbit/s */
568
-
pdata->max_speed = 10;
569
-
570
-
val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
571
-
if (val)
572
-
pdata->max_speed = fdt32_to_cpu(*val);
573
-
574
-
return 0;
575
-
}
576
-
577
-
static const struct udevice_id mcdmafec_ids[] = {
578
-
{ .compatible = "fsl,mcf-dma-fec" },
579
-
{ }
580
-
};
581
-
582
-
U_BOOT_DRIVER(mcffec) = {
583
-
.name = "mcdmafec",
584
-
.id = UCLASS_ETH,
585
-
.of_match = mcdmafec_ids,
586
-
.of_to_plat = mcdmafec_of_to_plat,
587
-
.probe = mcdmafec_probe,
588
-
.remove = mcdmafec_remove,
589
-
.ops = &mcdmafec_ops,
590
-
.priv_auto = sizeof(struct fec_info_dma),
591
-
.plat_auto = sizeof(struct eth_pdata),
592
-
};
-369
include/MCD_dma.h
-369
include/MCD_dma.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0+ */
2
-
/*
3
-
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4
-
*/
5
-
6
-
#ifndef _MCD_API_H
7
-
#define _MCD_API_H
8
-
9
-
/* Turn Execution Unit tasks ON (#define) or OFF (#undef) */
10
-
#undef MCD_INCLUDE_EU
11
-
12
-
/* Number of DMA channels */
13
-
#define NCHANNELS 16
14
-
15
-
/* Total number of variants */
16
-
#ifdef MCD_INCLUDE_EU
17
-
#define NUMOFVARIANTS 6
18
-
#else
19
-
#define NUMOFVARIANTS 4
20
-
#endif
21
-
22
-
/* Define sizes of the various tables */
23
-
#define TASK_TABLE_SIZE (NCHANNELS*32)
24
-
#define VAR_TAB_SIZE (128)
25
-
#define CONTEXT_SAVE_SIZE (128)
26
-
#define FUNCDESC_TAB_SIZE (256)
27
-
28
-
#ifdef MCD_INCLUDE_EU
29
-
#define FUNCDESC_TAB_NUM 16
30
-
#else
31
-
#define FUNCDESC_TAB_NUM 1
32
-
#endif
33
-
34
-
#ifndef DEFINESONLY
35
-
36
-
/* Portability typedefs */
37
-
#if 1
38
-
#include "common.h"
39
-
#else
40
-
#ifndef s32
41
-
typedef int s32;
42
-
#endif
43
-
#ifndef u32
44
-
typedef unsigned int u32;
45
-
#endif
46
-
#ifndef s16
47
-
typedef short s16;
48
-
#endif
49
-
#ifndef u16
50
-
typedef unsigned short u16;
51
-
#endif
52
-
#ifndef s8
53
-
typedef char s8;
54
-
#endif
55
-
#ifndef u8
56
-
typedef unsigned char u8;
57
-
#endif
58
-
#endif
59
-
60
-
/*
61
-
* These structures represent the internal registers of the
62
-
* multi-channel DMA
63
-
*/
64
-
struct dmaRegs_s {
65
-
u32 taskbar; /* task table base address */
66
-
u32 currPtr;
67
-
u32 endPtr;
68
-
u32 varTablePtr;
69
-
u16 dma_rsvd0;
70
-
u16 ptdControl; /* ptd control */
71
-
u32 intPending; /* interrupt pending */
72
-
u32 intMask; /* interrupt mask */
73
-
u16 taskControl[16]; /* task control */
74
-
u8 priority[32]; /* priority */
75
-
u32 initiatorMux; /* initiator mux control */
76
-
u32 taskSize0; /* task size control 0. */
77
-
u32 taskSize1; /* task size control 1. */
78
-
u32 dma_rsvd1; /* reserved */
79
-
u32 dma_rsvd2; /* reserved */
80
-
u32 debugComp1; /* debug comparator 1 */
81
-
u32 debugComp2; /* debug comparator 2 */
82
-
u32 debugControl; /* debug control */
83
-
u32 debugStatus; /* debug status */
84
-
u32 ptdDebug; /* priority task decode debug */
85
-
u32 dma_rsvd3[31]; /* reserved */
86
-
};
87
-
typedef volatile struct dmaRegs_s dmaRegs;
88
-
89
-
#endif
90
-
91
-
/* PTD contrl reg bits */
92
-
#define PTD_CTL_TSK_PRI 0x8000
93
-
#define PTD_CTL_COMM_PREFETCH 0x0001
94
-
95
-
/* Task Control reg bits and field masks */
96
-
#define TASK_CTL_EN 0x8000
97
-
#define TASK_CTL_VALID 0x4000
98
-
#define TASK_CTL_ALWAYS 0x2000
99
-
#define TASK_CTL_INIT_MASK 0x1f00
100
-
#define TASK_CTL_ASTRT 0x0080
101
-
#define TASK_CTL_HIPRITSKEN 0x0040
102
-
#define TASK_CTL_HLDINITNUM 0x0020
103
-
#define TASK_CTL_ASTSKNUM_MASK 0x000f
104
-
105
-
/* Priority reg bits and field masks */
106
-
#define PRIORITY_HLD 0x80
107
-
#define PRIORITY_PRI_MASK 0x07
108
-
109
-
/* Debug Control reg bits and field masks */
110
-
#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
111
-
#define DBG_CTL_AUTO_ARM 0x00008000
112
-
#define DBG_CTL_BREAK 0x00004000
113
-
#define DBG_CTL_COMP1_TYP_MASK 0x00003800
114
-
#define DBG_CTL_COMP2_TYP_MASK 0x00000070
115
-
#define DBG_CTL_EXT_BREAK 0x00000004
116
-
#define DBG_CTL_INT_BREAK 0x00000002
117
-
118
-
/*
119
-
* PTD Debug reg selector addresses
120
-
* This reg must be written with a value to show the contents of
121
-
* one of the desired internal register.
122
-
*/
123
-
#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
124
-
#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
125
-
have initiators asserted */
126
-
127
-
/* General return values */
128
-
#define MCD_OK 0
129
-
#define MCD_ERROR -1
130
-
#define MCD_TABLE_UNALIGNED -2
131
-
#define MCD_CHANNEL_INVALID -3
132
-
133
-
/* MCD_initDma input flags */
134
-
#define MCD_RELOC_TASKS 0x00000001
135
-
#define MCD_NO_RELOC_TASKS 0x00000000
136
-
#define MCD_COMM_PREFETCH_EN 0x00000002 /* MCF547x/548x ONLY */
137
-
138
-
/*
139
-
* MCD_dmaStatus Status Values for each channel:
140
-
* MCD_NO_DMA - No DMA has been requested since reset
141
-
* MCD_IDLE - DMA active, but the initiator is currently inactive
142
-
* MCD_RUNNING - DMA active, and the initiator is currently active
143
-
* MCD_PAUSED - DMA active but it is currently paused
144
-
* MCD_HALTED - the most recent DMA has been killed with MCD_killTask()
145
-
* MCD_DONE - the most recent DMA has completed
146
-
*/
147
-
#define MCD_NO_DMA 1
148
-
#define MCD_IDLE 2
149
-
#define MCD_RUNNING 3
150
-
#define MCD_PAUSED 4
151
-
#define MCD_HALTED 5
152
-
#define MCD_DONE 6
153
-
154
-
/* MCD_startDma parameter defines */
155
-
156
-
/* Constants for the funcDesc parameter */
157
-
/*
158
-
* MCD_NO_BYTE_SWAP - to disable byte swapping
159
-
* MCD_BYTE_REVERSE - to reverse the bytes of each u32 of the DMAed data
160
-
* MCD_U16_REVERSE - to reverse the 16-bit halves of each 32-bit data
161
-
* value being DMAed
162
-
* MCD_U16_BYTE_REVERSE - to reverse the byte halves of each 16-bit half of
163
-
* each 32-bit data value DMAed
164
-
* MCD_NO_BIT_REV - do not reverse the bits of each byte DMAed
165
-
* MCD_BIT_REV - reverse the bits of each byte DMAed
166
-
* MCD_CRC16 - to perform CRC-16 on DMAed data
167
-
* MCD_CRCCCITT - to perform CRC-CCITT on DMAed data
168
-
* MCD_CRC32 - to perform CRC-32 on DMAed data
169
-
* MCD_CSUMINET - to perform internet checksums on DMAed data
170
-
* MCD_NO_CSUM - to perform no checksumming
171
-
*/
172
-
#define MCD_NO_BYTE_SWAP 0x00045670
173
-
#define MCD_BYTE_REVERSE 0x00076540
174
-
#define MCD_U16_REVERSE 0x00067450
175
-
#define MCD_U16_BYTE_REVERSE 0x00054760
176
-
#define MCD_NO_BIT_REV 0x00000000
177
-
#define MCD_BIT_REV 0x00088880
178
-
/* CRCing: */
179
-
#define MCD_CRC16 0xc0100000
180
-
#define MCD_CRCCCITT 0xc0200000
181
-
#define MCD_CRC32 0xc0300000
182
-
#define MCD_CSUMINET 0xc0400000
183
-
#define MCD_NO_CSUM 0xa0000000
184
-
185
-
#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \
186
-
MCD_NO_CSUM)
187
-
#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
188
-
189
-
/* Constants for the flags parameter */
190
-
#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
191
-
#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
192
-
#define MCD_TT_FLAGS_SP 0x00000004 /* MCF547x/548x ONLY */
193
-
#define MCD_TT_FLAGS_MASK 0x000000ff
194
-
#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
195
-
196
-
#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
197
-
#define MCD_CHAIN_DMA /* TBD */
198
-
#define MCD_EU_DMA /* TBD */
199
-
#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
200
-
#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
201
-
202
-
/* these flags are valid for MCD_startDma and the chained buffer descriptors */
203
-
/*
204
-
* MCD_BUF_READY - indicates that this buf is now under the DMA's ctrl
205
-
* MCD_WRAP - to tell the FEC Dmas to wrap to the first BD
206
-
* MCD_INTERRUPT - to generate an interrupt after completion of the DMA
207
-
* MCD_END_FRAME - tell the DMA to end the frame when transferring
208
-
* last byte of data in buffer
209
-
* MCD_CRC_RESTART - to empty out the accumulated checksum prior to
210
-
* performing the DMA
211
-
*/
212
-
#define MCD_BUF_READY 0x80000000
213
-
#define MCD_WRAP 0x20000000
214
-
#define MCD_INTERRUPT 0x10000000
215
-
#define MCD_END_FRAME 0x08000000
216
-
#define MCD_CRC_RESTART 0x40000000
217
-
218
-
/* Defines for the FEC buffer descriptor control/status word*/
219
-
#define MCD_FEC_BUF_READY 0x8000
220
-
#define MCD_FEC_WRAP 0x2000
221
-
#define MCD_FEC_INTERRUPT 0x1000
222
-
#define MCD_FEC_END_FRAME 0x0800
223
-
224
-
/* Defines for general intuitiveness */
225
-
226
-
#define MCD_TRUE 1
227
-
#define MCD_FALSE 0
228
-
229
-
/* Three different cases for destination and source. */
230
-
#define MINUS1 -1
231
-
#define ZERO 0
232
-
#define PLUS1 1
233
-
234
-
#ifndef DEFINESONLY
235
-
236
-
/* Task Table Entry struct*/
237
-
typedef struct {
238
-
u32 TDTstart; /* task descriptor table start */
239
-
u32 TDTend; /* task descriptor table end */
240
-
u32 varTab; /* variable table start */
241
-
u32 FDTandFlags; /* function descriptor table start & flags */
242
-
volatile u32 descAddrAndStatus;
243
-
volatile u32 modifiedVarTab;
244
-
u32 contextSaveSpace; /* context save space start */
245
-
u32 literalBases;
246
-
} TaskTableEntry;
247
-
248
-
/* Chained buffer descriptor:
249
-
* flags - flags describing the DMA
250
-
* csumResult - checksum performed since last checksum reset
251
-
* srcAddr - the address to move data from
252
-
* destAddr - the address to move data to
253
-
* lastDestAddr - the last address written to
254
-
* dmaSize - the no of bytes to xfer independent of the xfer sz
255
-
* next - next buffer descriptor in chain
256
-
* info - private info about this descriptor; DMA does not affect it
257
-
*/
258
-
typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
259
-
struct MCD_bufDesc_struct {
260
-
u32 flags;
261
-
u32 csumResult;
262
-
s8 *srcAddr;
263
-
s8 *destAddr;
264
-
s8 *lastDestAddr;
265
-
u32 dmaSize;
266
-
MCD_bufDesc *next;
267
-
u32 info;
268
-
};
269
-
270
-
/* Progress Query struct:
271
-
* lastSrcAddr - the most-recent or last, post-increment source address
272
-
* lastDestAddr - the most-recent or last, post-increment destination address
273
-
* dmaSize - the amount of data transferred for the current buffer
274
-
* currBufDesc - pointer to the current buffer descriptor being DMAed
275
-
*/
276
-
277
-
typedef volatile struct MCD_XferProg_struct {
278
-
s8 *lastSrcAddr;
279
-
s8 *lastDestAddr;
280
-
u32 dmaSize;
281
-
MCD_bufDesc *currBufDesc;
282
-
} MCD_XferProg;
283
-
284
-
/* FEC buffer descriptor */
285
-
typedef volatile struct MCD_bufDescFec_struct {
286
-
u16 statCtrl;
287
-
u16 length;
288
-
u32 dataPointer;
289
-
} MCD_bufDescFec;
290
-
291
-
/*************************************************************************/
292
-
/* API function Prototypes - see MCD_dmaApi.c for further notes */
293
-
294
-
/* MCD_startDma starts a particular kind of DMA:
295
-
* srcAddr - the channel on which to run the DMA
296
-
* srcIncr - the address to move data from, or buffer-descriptor address
297
-
* destAddr - the amount to increment the source address per transfer
298
-
* destIncr - the address to move data to
299
-
* dmaSize - the amount to increment the destination address per transfer
300
-
* xferSize - the number bytes in of each data movement (1, 2, or 4)
301
-
* initiator - what device initiates the DMA
302
-
* priority - priority of the DMA
303
-
* flags - flags describing the DMA
304
-
* funcDesc - description of byte swapping, bit swapping, and CRC actions
305
-
*/
306
-
int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
307
-
s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
308
-
int priority, u32 flags, u32 funcDesc);
309
-
310
-
/*
311
-
* MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
312
-
* registers, relocating and creating the appropriate task structures, and
313
-
* setting up some global settings
314
-
*/
315
-
int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags);
316
-
317
-
/* MCD_dmaStatus() returns the status of the DMA on the requested channel. */
318
-
int MCD_dmaStatus(int channel);
319
-
320
-
/* MCD_XferProgrQuery() returns progress of DMA on requested channel */
321
-
int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep);
322
-
323
-
/*
324
-
* MCD_killDma() halts the DMA on the requested channel, without any
325
-
* intention of resuming the DMA.
326
-
*/
327
-
int MCD_killDma(int channel);
328
-
329
-
/*
330
-
* MCD_continDma() continues a DMA which as stopped due to encountering an
331
-
* unready buffer descriptor.
332
-
*/
333
-
int MCD_continDma(int channel);
334
-
335
-
/*
336
-
* MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
337
-
* running on that channel).
338
-
*/
339
-
int MCD_pauseDma(int channel);
340
-
341
-
/*
342
-
* MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
343
-
* running on that channel).
344
-
*/
345
-
int MCD_resumeDma(int channel);
346
-
347
-
/* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */
348
-
int MCD_csumQuery(int channel, u32 * csum);
349
-
350
-
/*
351
-
* MCD_getCodeSize provides the packed size required by the microcoded task
352
-
* and structures.
353
-
*/
354
-
int MCD_getCodeSize(void);
355
-
356
-
/*
357
-
* MCD_getVersion provides a pointer to a version string and returns a
358
-
* version number.
359
-
*/
360
-
int MCD_getVersion(char **longVersion);
361
-
362
-
/* macro for setting a location in the variable table */
363
-
#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
364
-
/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
365
-
so I'm avoiding surrounding it with "do {} while(0)" */
366
-
367
-
#endif /* DEFINESONLY */
368
-
369
-
#endif /* _MCD_API_H */
-10
include/MCD_progCheck.h
-10
include/MCD_progCheck.h
-43
include/MCD_tasksInit.h
-43
include/MCD_tasksInit.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0+ */
2
-
/*
3
-
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4
-
*/
5
-
6
-
#ifndef MCD_TSK_INIT_H
7
-
#define MCD_TSK_INIT_H 1
8
-
9
-
/*
10
-
* Do not edit!
11
-
*/
12
-
13
-
/* Task 0 */
14
-
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
15
-
int xferSize, short xferSizeIncr, int *cSave,
16
-
volatile TaskTableEntry * taskTable, int channel);
17
-
18
-
/* Task 1 */
19
-
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
20
-
short destIncr, int dmaSize, short xferSizeIncr,
21
-
int flags, int *currBD, int *cSave,
22
-
volatile TaskTableEntry * taskTable, int channel);
23
-
24
-
/* Task 2 */
25
-
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
26
-
int xferSize, short xferSizeIncr, int *cSave,
27
-
volatile TaskTableEntry * taskTable, int channel);
28
-
29
-
/* Task 3 */
30
-
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
31
-
short destIncr, int dmaSize, short xferSizeIncr,
32
-
int flags, int *currBD, int *cSave,
33
-
volatile TaskTableEntry * taskTable, int channel);
34
-
35
-
/* Task 4 */
36
-
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
37
-
volatile TaskTableEntry * taskTable, int channel);
38
-
39
-
/* Task 5 */
40
-
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
41
-
volatile TaskTableEntry * taskTable, int channel);
42
-
43
-
#endif /* MCD_TSK_INIT_H */