jcs.org
"Das U-Boot" Source Tree
ARC: HSDK: split HSDK and HSDK-4xD DTS
Split HSDK and HSDK-4xD device tree files so they can have
different model names.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
authored by
Eugeniy Paltsev
and committed by
Alexey Brodkin
28db0d69
f0f84efe
+167
-144
+1
-1
arch/arc/dts/Makefile
+1
-1
arch/arc/dts/Makefile
···
5
5
dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb
6
6
dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb
7
7
dtb-$(CONFIG_TARGET_EMSDP) += emsdp.dtb
8
-
dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb
8
+
dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb hsdk-4xd.dtb
9
9
dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb
10
10
11
11
targets += $(dtb-y)
+12
arch/arc/dts/hsdk-4xd.dts
+12
arch/arc/dts/hsdk-4xd.dts
+150
arch/arc/dts/hsdk-common.dtsi
+150
arch/arc/dts/hsdk-common.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Copyright (C) 2017-2020 Synopsys, Inc. All rights reserved.
4
+
* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
5
+
*/
6
+
/dts-v1/;
7
+
8
+
#include "skeleton.dtsi"
9
+
#include "dt-bindings/clock/snps,hsdk-cgu.h"
10
+
#include "dt-bindings/reset/snps,hsdk-reset.h"
11
+
12
+
/ {
13
+
#address-cells = <1>;
14
+
#size-cells = <1>;
15
+
16
+
aliases {
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+
console = &uart0;
18
+
spi0 = &spi0;
19
+
};
20
+
21
+
cpu_card {
22
+
core_clk: core_clk {
23
+
#clock-cells = <0>;
24
+
compatible = "fixed-clock";
25
+
clock-frequency = <500000000>;
26
+
u-boot,dm-pre-reloc;
27
+
};
28
+
};
29
+
30
+
clk-fmeas {
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+
clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
32
+
<&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
33
+
<&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
34
+
<&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
35
+
<&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
36
+
<&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
37
+
<&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
38
+
<&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
39
+
<&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
40
+
<&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
41
+
<&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
42
+
<&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
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+
<&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>;
44
+
clock-names = "cpu-pll", "sys-pll",
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+
"tun-pll", "ddr-clk",
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+
"cpu-clk", "hdmi-pll",
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+
"tun-clk", "hdmi-clk",
48
+
"apb-clk", "axi-clk",
49
+
"eth-clk", "usb-clk",
50
+
"sdio-clk", "hdmi-sys-clk",
51
+
"gfx-core-clk", "gfx-dma-clk",
52
+
"gfx-cfg-clk", "dmac-core-clk",
53
+
"dmac-cfg-clk", "sdio-ref-clk",
54
+
"spi-clk", "i2c-clk",
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+
"uart-clk", "ebi-clk",
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+
"rom-clk", "pwm-clk";
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+
};
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+
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+
cgu_clk: cgu-clk@f0000000 {
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+
compatible = "snps,hsdk-cgu-clock";
61
+
reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
62
+
#clock-cells = <1>;
63
+
};
64
+
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+
cgu_rst: reset-controller@f00008a0 {
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+
compatible = "snps,hsdk-reset";
67
+
#reset-cells = <1>;
68
+
reg = <0xf00008a0 0x4>, <0xf0000ff0 0x4>;
69
+
};
70
+
71
+
uart0: serial0@f0005000 {
72
+
compatible = "snps,dw-apb-uart";
73
+
reg = <0xf0005000 0x1000>;
74
+
reg-shift = <2>;
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+
reg-io-width = <4>;
76
+
};
77
+
78
+
ethernet@f0008000 {
79
+
#interrupt-cells = <1>;
80
+
compatible = "snps,arc-dwmac-3.70a";
81
+
reg = <0xf0008000 0x2000>;
82
+
phy-mode = "gmii";
83
+
};
84
+
85
+
ehci@0xf0040000 {
86
+
compatible = "generic-ehci";
87
+
reg = <0xf0040000 0x100>;
88
+
};
89
+
90
+
ohci@0xf0060000 {
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+
compatible = "generic-ohci";
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+
reg = <0xf0060000 0x100>;
93
+
};
94
+
95
+
mmcclk_ciu: mmcclk-ciu {
96
+
compatible = "fixed-clock";
97
+
/*
98
+
* DW sdio controller has external ciu clock divider
99
+
* controlled via register in SDIO IP. Due to its
100
+
* unexpected default value (it should divide by 1
101
+
* but it divides by 8) SDIO IP uses wrong clock and
102
+
* works unstable (see STAR 9001204800)
103
+
* We switched to the minimum possible value of the
104
+
* divisor (div-by-2) in HSDK platform code.
105
+
* So default mmcclk ciu clock is 50000000 Hz.
106
+
*/
107
+
clock-frequency = <50000000>;
108
+
#clock-cells = <0>;
109
+
};
110
+
111
+
mmc: mmc0@f000a000 {
112
+
compatible = "snps,dw-mshc";
113
+
reg = <0xf000a000 0x400>;
114
+
bus-width = <4>;
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+
fifo-depth = <256>;
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+
clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>;
117
+
clock-names = "biu", "ciu";
118
+
max-frequency = <25000000>;
119
+
};
120
+
121
+
spi0: spi@f0020000 {
122
+
compatible = "snps,dw-apb-ssi";
123
+
reg = <0xf0020000 0x1000>;
124
+
#address-cells = <1>;
125
+
#size-cells = <0>;
126
+
spi-max-frequency = <4000000>;
127
+
clocks = <&cgu_clk CLK_SYS_SPI_REF>;
128
+
clock-names = "spi_clk";
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+
cs-gpio = <&cs_gpio 0>;
130
+
spi_flash@0 {
131
+
compatible = "jedec,spi-nor";
132
+
reg = <0>;
133
+
spi-max-frequency = <4000000>;
134
+
};
135
+
};
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+
137
+
cs_gpio: gpio@f00014b0 {
138
+
compatible = "snps,creg-gpio";
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+
reg = <0xf00014b0 0x4>;
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+
gpio-controller;
141
+
#gpio-cells = <1>;
142
+
gpio-bank-name = "hsdk-spi-cs";
143
+
gpio-count = <1>;
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+
gpio-first-shift = <0>;
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+
gpio-bit-per-line = <2>;
146
+
gpio-activate-val = <2>;
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+
gpio-deactivate-val = <3>;
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+
gpio-default-val = <1>;
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+
};
150
+
};
+3
-142
arch/arc/dts/hsdk.dts
+3
-142
arch/arc/dts/hsdk.dts
···
1
1
// SPDX-License-Identifier: GPL-2.0+
2
2
/*
3
-
* Copyright (C) 2017 Synopsys, Inc. All rights reserved.
3
+
* Copyright (C) 2017-2020 Synopsys, Inc. All rights reserved.
4
+
* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
4
5
*/
5
6
/dts-v1/;
6
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7
-
#include "skeleton.dtsi"
8
-
#include "dt-bindings/clock/snps,hsdk-cgu.h"
9
-
#include "dt-bindings/reset/snps,hsdk-reset.h"
8
+
#include "hsdk-common.dtsi"
10
9
11
10
/ {
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11
model = "snps,hsdk";
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-
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#address-cells = <1>;
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-
#size-cells = <1>;
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-
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aliases {
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-
console = &uart0;
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-
spi0 = &spi0;
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-
};
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-
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cpu_card {
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-
core_clk: core_clk {
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#clock-cells = <0>;
25
-
compatible = "fixed-clock";
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-
clock-frequency = <500000000>;
27
-
u-boot,dm-pre-reloc;
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-
};
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};
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-
31
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clk-fmeas {
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-
clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
33
-
<&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
34
-
<&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
35
-
<&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
36
-
<&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
37
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<&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
38
-
<&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
39
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<&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
40
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<&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
41
-
<&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
42
-
<&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
43
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<&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
44
-
<&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>;
45
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clock-names = "cpu-pll", "sys-pll",
46
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"tun-pll", "ddr-clk",
47
-
"cpu-clk", "hdmi-pll",
48
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"tun-clk", "hdmi-clk",
49
-
"apb-clk", "axi-clk",
50
-
"eth-clk", "usb-clk",
51
-
"sdio-clk", "hdmi-sys-clk",
52
-
"gfx-core-clk", "gfx-dma-clk",
53
-
"gfx-cfg-clk", "dmac-core-clk",
54
-
"dmac-cfg-clk", "sdio-ref-clk",
55
-
"spi-clk", "i2c-clk",
56
-
"uart-clk", "ebi-clk",
57
-
"rom-clk", "pwm-clk";
58
-
};
59
-
60
-
cgu_clk: cgu-clk@f0000000 {
61
-
compatible = "snps,hsdk-cgu-clock";
62
-
reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
63
-
#clock-cells = <1>;
64
-
};
65
-
66
-
cgu_rst: reset-controller@f00008a0 {
67
-
compatible = "snps,hsdk-reset";
68
-
#reset-cells = <1>;
69
-
reg = <0xf00008a0 0x4>, <0xf0000ff0 0x4>;
70
-
};
71
-
72
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uart0: serial0@f0005000 {
73
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compatible = "snps,dw-apb-uart";
74
-
reg = <0xf0005000 0x1000>;
75
-
reg-shift = <2>;
76
-
reg-io-width = <4>;
77
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};
78
-
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-
ethernet@f0008000 {
80
-
#interrupt-cells = <1>;
81
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compatible = "snps,arc-dwmac-3.70a";
82
-
reg = <0xf0008000 0x2000>;
83
-
phy-mode = "gmii";
84
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};
85
-
86
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ehci@0xf0040000 {
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compatible = "generic-ehci";
88
-
reg = <0xf0040000 0x100>;
89
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};
90
-
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ohci@0xf0060000 {
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compatible = "generic-ohci";
93
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reg = <0xf0060000 0x100>;
94
-
};
95
-
96
-
mmcclk_ciu: mmcclk-ciu {
97
-
compatible = "fixed-clock";
98
-
/*
99
-
* DW sdio controller has external ciu clock divider
100
-
* controlled via register in SDIO IP. Due to its
101
-
* unexpected default value (it should divide by 1
102
-
* but it divides by 8) SDIO IP uses wrong clock and
103
-
* works unstable (see STAR 9001204800)
104
-
* We switched to the minimum possible value of the
105
-
* divisor (div-by-2) in HSDK platform code.
106
-
* So default mmcclk ciu clock is 50000000 Hz.
107
-
*/
108
-
clock-frequency = <50000000>;
109
-
#clock-cells = <0>;
110
-
};
111
-
112
-
mmc: mmc0@f000a000 {
113
-
compatible = "snps,dw-mshc";
114
-
reg = <0xf000a000 0x400>;
115
-
bus-width = <4>;
116
-
fifo-depth = <256>;
117
-
clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>;
118
-
clock-names = "biu", "ciu";
119
-
max-frequency = <25000000>;
120
-
};
121
-
122
-
spi0: spi@f0020000 {
123
-
compatible = "snps,dw-apb-ssi";
124
-
reg = <0xf0020000 0x1000>;
125
-
#address-cells = <1>;
126
-
#size-cells = <0>;
127
-
spi-max-frequency = <4000000>;
128
-
clocks = <&cgu_clk CLK_SYS_SPI_REF>;
129
-
clock-names = "spi_clk";
130
-
cs-gpio = <&cs_gpio 0>;
131
-
spi_flash@0 {
132
-
compatible = "jedec,spi-nor";
133
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reg = <0>;
134
-
spi-max-frequency = <4000000>;
135
-
};
136
-
};
137
-
138
-
cs_gpio: gpio@f00014b0 {
139
-
compatible = "snps,creg-gpio";
140
-
reg = <0xf00014b0 0x4>;
141
-
gpio-controller;
142
-
#gpio-cells = <1>;
143
-
gpio-bank-name = "hsdk-spi-cs";
144
-
gpio-count = <1>;
145
-
gpio-first-shift = <0>;
146
-
gpio-bit-per-line = <2>;
147
-
gpio-activate-val = <2>;
148
-
gpio-deactivate-val = <3>;
149
-
gpio-default-val = <1>;
150
-
};
151
12
};
+1
-1
configs/hsdk_4xd_defconfig
+1
-1
configs/hsdk_4xd_defconfig