"Das U-Boot" Source Tree

imx6: aristainetos: add support for rev C board

add support for revision C boards. This board has
no longer a NAND.

Signed-off-by: Heiko Schocher <hs@denx.de>

authored by

Heiko Schocher and committed by
Stefano Babic
227cb300 c08aa771

+586 -1
+2
arch/arm/dts/Makefile
··· 582 582 imx6dl-aristainetos2b_7.dtb \ 583 583 imx6dl-aristainetos2b_csl_4.dtb \ 584 584 imx6dl-aristainetos2b_csl_7.dtb \ 585 + imx6dl-aristainetos2c_4.dtb \ 586 + imx6dl-aristainetos2c_7.dtb \ 585 587 imx6dl-brppt2.dtb \ 586 588 imx6dl-dhcom-pdk2.dtb \ 587 589 imx6dl-icore.dtb \
+13
arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0+ or X11 2 + /* 3 + * Copyright (C) 2019 Heiko Schocher <hs@denx.de> 4 + */ 5 + 6 + #include <imx6qdl-aristainetos2c-u-boot.dtsi> 7 + 8 + &lcd_panel { 9 + pinctrl-names = "default"; 10 + pinctrl-0 = <&pinctrl_ipu_disp>; 11 + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; 12 + backlight = <&backlight>; 13 + };
+50
arch/arm/dts/imx6dl-aristainetos2c_4.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0) 2 + /* 3 + * support for the imx6 based aristainetos2c board 4 + * parts for 4.3 inch LG display on spi1 port1 5 + * 6 + * Copyright (C) 2019 Heiko Schocher <hs@denx.de> 7 + * 8 + */ 9 + /dts-v1/; 10 + 11 + #include "imx6dl-aristainetos2_4.dtsi" 12 + #include "imx6qdl-aristainetos2c.dtsi" 13 + 14 + / { 15 + model = "aristainetos2c i.MX6 Dual Lite Board 4"; 16 + compatible = "fsl,imx6dl"; 17 + 18 + }; 19 + 20 + &ecspi1 { 21 + lcd_panel: display@0 { 22 + compatible = "lg,lg4573"; 23 + spi-max-frequency = <10000000>; 24 + reg = <1>; 25 + power-on-delay = <10>; 26 + 27 + display-timings { 28 + 480x800p57 { 29 + native-mode; 30 + clock-frequency = <27000027>; 31 + hactive = <480>; 32 + vactive = <800>; 33 + hfront-porch = <10>; 34 + hback-porch = <59>; 35 + hsync-len = <10>; 36 + vback-porch = <15>; 37 + vfront-porch = <15>; 38 + vsync-len = <15>; 39 + hsync-active = <1>; 40 + vsync-active = <1>; 41 + }; 42 + }; 43 + 44 + port { 45 + panel_in: endpoint { 46 + remote-endpoint = <&display_out>; 47 + }; 48 + }; 49 + }; 50 + };
+19
arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0+ or X11 2 + /* 3 + * Copyright (C) 2019 Heiko Schocher <hs@denx.de> 4 + */ 5 + 6 + #include <imx6qdl-aristainetos2c-u-boot.dtsi> 7 + / { 8 + vdd_panel_reg: regulator-panel { 9 + compatible = "regulator-fixed"; 10 + regulator-name = "panel_regulator"; 11 + regulator-min-microvolt = <3300000>; 12 + regulator-max-microvolt = <3300000>; 13 + regulator-always-on; 14 + }; 15 + }; 16 + 17 + &panel0 { 18 + power-supply = <&vdd_panel_reg>; 19 + };
+16
arch/arm/dts/imx6dl-aristainetos2c_7.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0) 2 + /* 3 + * support for the imx6 based aristainetos2c board 4 + * 5 + * Copyright (C) 2019 Heiko Schocher <hs@denx.de> 6 + * Copyright (C) 2015 Heiko Schocher <hs@denx.de> 7 + * 8 + */ 9 + /dts-v1/; 10 + #include "imx6dl-aristainetos2_7.dtsi" 11 + #include "imx6qdl-aristainetos2c.dtsi" 12 + 13 + / { 14 + model = "aristainetos2c i.MX6 Dual Lite Board 7"; 15 + compatible = "fsl,imx6dl"; 16 + };
+77
arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0+ or X11 2 + /* 3 + * Copyright (C) 2019 Heiko Schocher <hs@denx.de> 4 + */ 5 + 6 + / { 7 + chosen { 8 + u-boot,dm-pre-reloc; 9 + stdout-path = &uart2; 10 + }; 11 + 12 + wdt-reboot { 13 + compatible = "wdt-reboot"; 14 + wdt = <&wdog1>; 15 + }; 16 + }; 17 + 18 + &uart2 { 19 + u-boot,dm-pre-reloc; 20 + }; 21 + 22 + &pinctrl_gpio { 23 + u-boot,dm-pre-reloc; 24 + }; 25 + 26 + &pinctrl_uart2 { 27 + u-boot,dm-pre-reloc; 28 + }; 29 + 30 + &iomuxc { 31 + u-boot,dm-pre-reloc; 32 + }; 33 + 34 + &aips2 { 35 + u-boot,dm-pre-reloc; 36 + }; 37 + 38 + &backlight { 39 + pwms = <&pwm1 0 300000>; 40 + default-brightness-level = <2>; 41 + }; 42 + 43 + /* 44 + * allow switching write protect / reset pin by gpio, 45 + * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot 46 + */ 47 + &gpio2 { 48 + u-boot,dm-pre-reloc; 49 + 50 + wp_spi_nor { 51 + gpio-hog; 52 + output-high; 53 + gpios = <15 GPIO_ACTIVE_HIGH>; 54 + }; 55 + 56 + reset_spi_nor { 57 + gpio-hog; 58 + output-high; 59 + gpios = <28 GPIO_ACTIVE_HIGH>; 60 + }; 61 + }; 62 + 63 + &gpio4 { 64 + u-boot,dm-pre-reloc; 65 + }; 66 + 67 + &ecspi1 { 68 + u-boot,dm-pre-reloc; 69 + }; 70 + 71 + &flash { 72 + u-boot,dm-pre-reloc; 73 + }; 74 + 75 + &pinctrl_ecspi1 { 76 + u-boot,dm-pre-reloc; 77 + };
+228
arch/arm/dts/imx6qdl-aristainetos2c.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0) 2 + /* 3 + * support for the imx6 based aristainetos2c board 4 + * 5 + * Copyright (C) 2019 Heiko Schocher <hs@denx.de> 6 + * Copyright (C) 2015 Heiko Schocher <hs@denx.de> 7 + * 8 + */ 9 + #include <dt-bindings/gpio/gpio.h> 10 + #include <dt-bindings/clock/imx6qdl-clock.h> 11 + 12 + #include "imx6qdl-aristainetos2-common.dtsi" 13 + 14 + / { 15 + leds { 16 + compatible = "gpio-leds"; 17 + pinctrl-names = "default"; 18 + pinctrl-0 = <&pinctrl_gpio>; 19 + 20 + LED_blue { 21 + label = "led_blue"; 22 + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; 23 + }; 24 + 25 + LED_green { 26 + label = "led_green"; 27 + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 28 + }; 29 + 30 + LED_red { 31 + label = "led_red"; 32 + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; 33 + }; 34 + 35 + LED_yellow { 36 + label = "led_yellow"; 37 + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; 38 + }; 39 + 40 + LED_ena { 41 + label = "led_ena"; 42 + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 43 + }; 44 + }; 45 + }; 46 + 47 + &ecspi1 { 48 + fsl,spi-num-chipselects = <3>; 49 + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH 50 + &gpio4 10 GPIO_ACTIVE_HIGH 51 + &gpio4 11 GPIO_ACTIVE_HIGH>; 52 + pinctrl-names = "default"; 53 + pinctrl-0 = <&pinctrl_ecspi1>; 54 + status = "okay"; 55 + pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; 56 + pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 57 + 58 + flash: m25p80@0 { 59 + #address-cells = <1>; 60 + #size-cells = <1>; 61 + compatible = "micron,n25q128a11", "jedec,spi-nor"; 62 + spi-max-frequency = <20000000>; 63 + reg = <0>; 64 + }; 65 + }; 66 + 67 + &ecspi4 { 68 + fsl,spi-num-chipselects = <2>; 69 + cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; 70 + pinctrl-names = "default"; 71 + pinctrl-0 = <&pinctrl_ecspi4>; 72 + status = "okay"; 73 + }; 74 + 75 + &i2c1 { 76 + tpm@20 { 77 + compatible = "infineon,slb9645tt"; 78 + reg = <0x20>; 79 + }; 80 + }; 81 + 82 + &can1 { 83 + pinctrl-names = "default"; 84 + pinctrl-0 = <&pinctrl_flexcan1>; 85 + status = "okay"; 86 + }; 87 + 88 + &can2 { 89 + pinctrl-names = "default"; 90 + pinctrl-0 = <&pinctrl_flexcan2>; 91 + status = "okay"; 92 + }; 93 + 94 + &usdhc1 { 95 + pinctrl-names = "default"; 96 + pinctrl-0 = <&pinctrl_usdhc1>; 97 + cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; 98 + wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; 99 + no-1-8-v; 100 + status = "okay"; 101 + }; 102 + 103 + &usdhc2 { 104 + pinctrl-names = "default"; 105 + pinctrl-0 = <&pinctrl_usdhc2>; 106 + bus-width = <8>; 107 + no-1-8-v; 108 + non-removable; 109 + status = "okay"; 110 + }; 111 + 112 + &iomuxc { 113 + pinctrl_ecspi1: ecspi1grp { 114 + fsl,pins = < 115 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 116 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 117 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 118 + /* SS0# */ 119 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 120 + /* SS1# */ 121 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 122 + /* SS2# */ 123 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 124 + /* WP pin NOR Flash */ 125 + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 126 + /* Flash nReset */ 127 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 128 + >; 129 + }; 130 + 131 + pinctrl_ecspi4: ecspi4grp { 132 + fsl,pins = < 133 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 134 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 135 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 136 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ 137 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ 138 + >; 139 + }; 140 + 141 + pinctrl_gpio: gpiogrp { 142 + fsl,pins = < 143 + /* led enable */ 144 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 145 + /* LCD power enable */ 146 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 147 + /* led yellow */ 148 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 149 + /* led red */ 150 + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 151 + /* led green */ 152 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 153 + /* led blue */ 154 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 155 + /* Profibus IRQ */ 156 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 157 + /* FPGA IRQ currently unused*/ 158 + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 159 + /* Display reset because of clock failure */ 160 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 161 + /* spi bus #2 SS driver enable */ 162 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 163 + /* RST_LOC# PHY reset input (has pull-down!)*/ 164 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 165 + /* Touchscreen IRQ */ 166 + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 167 + /* PCIe reset */ 168 + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 169 + /* make sure pin is GPIO and not ENET_REF_CLK */ 170 + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 171 + /* TPM PP */ 172 + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0 173 + /* TPM Reset */ 174 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 175 + >; 176 + }; 177 + 178 + pinctrl_flexcan1: flexcan1grp { 179 + fsl,pins = < 180 + MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 181 + MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 182 + >; 183 + }; 184 + 185 + pinctrl_flexcan2: flexcan2grp { 186 + fsl,pins = < 187 + MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 188 + MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 189 + >; 190 + }; 191 + 192 + pinctrl_usbotg: usbotggrp { 193 + fsl,pins = < 194 + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 195 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 196 + >; 197 + }; 198 + 199 + pinctrl_usdhc1: usdhc1grp { 200 + fsl,pins = < 201 + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 202 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 203 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 204 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 205 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 206 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 207 + /* SD1 card detect input */ 208 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 209 + /* SD1 write protect input */ 210 + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 211 + >; 212 + }; 213 + 214 + pinctrl_usdhc2: usdhc2grp { 215 + fsl,pins = < 216 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 217 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 218 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 219 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 220 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 221 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 222 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 223 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 224 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 225 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 226 + >; 227 + }; 228 + };
+11
arch/arm/mach-imx/mx6/Kconfig
··· 158 158 imply CMD_SATA 159 159 imply CMD_DM 160 160 161 + config TARGET_ARISTAINETOS2C 162 + bool "Support aristainetos2-revC" 163 + select BOARD_LATE_INIT 164 + select MX6DL 165 + select SYS_I2C_MXC 166 + select MXC_UART 167 + select FEC_MXC 168 + select DM 169 + imply CMD_SATA 170 + imply CMD_DM 171 + 161 172 config TARGET_CGTQMX6EVAL 162 173 bool "cgtqmx6eval" 163 174 select BOARD_LATE_INIT
+12
board/aristainetos/Kconfig
··· 33 33 default 4 34 34 35 35 endif 36 + 37 + if TARGET_ARISTAINETOS2C 38 + 39 + source "board/aristainetos/common/Kconfig" 40 + 41 + config SYS_BOARD 42 + default "aristainetos" 43 + 44 + config SYS_BOARD_VERSION 45 + default 5 46 + 47 + endif
+7
board/aristainetos/MAINTAINERS
··· 6 6 F: configs/aristainetos2_defconfig 7 7 F: configs/aristainetos2b_defconfig 8 8 F: configs/aristainetos2bcsl_defconfig 9 + F: configs/aristainetos2c_defconfig 9 10 F: arch/arm/dts/imx6qdl-aristainetos2.dtsi 10 11 F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi 11 12 F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi ··· 27 28 F: arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi 28 29 F: arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi 29 30 F: arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi 31 + F: arch/arm/dts/imx6dl-aristainetos2c_4.dts 32 + F: arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi 33 + F: arch/arm/dts/imx6dl-aristainetos2c_7.dts 34 + F: arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi 35 + F: arch/arm/dts/imx6qdl-aristainetos2c.dtsi 36 + F: arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi
+8 -1
board/aristainetos/aristainetos.c
··· 492 492 } 493 493 #if ((CONFIG_SYS_BOARD_VERSION == 2) || \ 494 494 (CONFIG_SYS_BOARD_VERSION == 3) || \ 495 - (CONFIG_SYS_BOARD_VERSION == 4)) 495 + (CONFIG_SYS_BOARD_VERSION == 4) || \ 496 + (CONFIG_SYS_BOARD_VERSION == 5)) 496 497 , { 497 498 .bus = -1, 498 499 .addr = 0, ··· 520 521 }; 521 522 size_t display_count = ARRAY_SIZE(displays); 522 523 524 + #if defined(CONFIG_NAND) 523 525 iomux_v3_cfg_t nfc_pads[] = { 524 526 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), 525 527 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), ··· 573 575 /* enable apbh clock gating */ 574 576 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 575 577 } 578 + #else 579 + static void setup_gpmi_nand(void) 580 + { 581 + } 582 + #endif 576 583 577 584 int board_init(void) 578 585 {
+1
board/aristainetos/common/Kconfig
··· 5 5 2 version 2 6 6 3 version 2b 7 7 4 version 2bcsl 8 + 5 version 2c 8 9 9 10 config SYS_I2C_MXC_I2C1 10 11 default y
+115
configs/aristainetos2c_defconfig
··· 1 + CONFIG_ARM=y 2 + CONFIG_SYS_THUMB_BUILD=y 3 + CONFIG_ARCH_MX6=y 4 + CONFIG_SYS_TEXT_BASE=0x17800000 5 + CONFIG_SYS_MALLOC_F_LEN=0xe000 6 + CONFIG_ENV_SIZE=0x3000 7 + CONFIG_ENV_OFFSET=0xD0000 8 + CONFIG_TARGET_ARISTAINETOS2C=y 9 + CONFIG_NR_DRAM_BANKS=1 10 + CONFIG_ENV_SECT_SIZE=0x10000 11 + CONFIG_IMX_HAB=y 12 + # CONFIG_CMD_DEKBLOB is not set 13 + CONFIG_FIT=y 14 + CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" 15 + CONFIG_BOOTDELAY=3 16 + CONFIG_USE_BOOTCOMMAND=y 17 + CONFIG_BOOTCOMMAND="run ari_boot" 18 + # CONFIG_CONSOLE_MUX is not set 19 + CONFIG_SYS_CONSOLE_IS_IN_ENV=y 20 + CONFIG_SUPPORT_RAW_INITRD=y 21 + CONFIG_VERSION_VARIABLE=y 22 + CONFIG_BOUNCE_BUFFER=y 23 + CONFIG_BOARD_TYPES=y 24 + CONFIG_BOARD_EARLY_INIT_F=y 25 + CONFIG_HUSH_PARSER=y 26 + CONFIG_AUTOBOOT_KEYED=y 27 + CONFIG_AUTOBOOT_ENCRYPTION=y 28 + CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" 29 + CONFIG_CMD_BOOTZ=y 30 + # CONFIG_BOOTM_NETBSD is not set 31 + # CONFIG_BOOTM_PLAN9 is not set 32 + # CONFIG_BOOTM_RTEMS is not set 33 + # CONFIG_BOOTM_VXWORKS is not set 34 + # CONFIG_CMD_FLASH is not set 35 + CONFIG_CMD_GPIO=y 36 + CONFIG_CMD_I2C=y 37 + CONFIG_CMD_MMC=y 38 + # CONFIG_CMD_PINMUX is not set 39 + # CONFIG_CMD_SATA is not set 40 + CONFIG_CMD_USB=y 41 + CONFIG_CMD_DHCP=y 42 + CONFIG_CMD_MII=y 43 + CONFIG_CMD_PING=y 44 + CONFIG_CMD_BMP=y 45 + CONFIG_CMD_CACHE=y 46 + # CONFIG_CMD_HASH is not set 47 + CONFIG_CMD_EXT2=y 48 + CONFIG_CMD_EXT4=y 49 + CONFIG_CMD_EXT4_WRITE=y 50 + CONFIG_CMD_FAT=y 51 + CONFIG_CMD_FS_GENERIC=y 52 + CONFIG_CMD_MTDPARTS=y 53 + CONFIG_CMD_UBI=y 54 + CONFIG_OF_CONTROL=y 55 + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_4" 56 + CONFIG_OF_LIST="imx6dl-aristainetos2c_4 imx6dl-aristainetos2c_7" 57 + CONFIG_DTB_RESELECT=y 58 + CONFIG_MULTI_DTB_FIT=y 59 + CONFIG_ENV_IS_IN_SPI_FLASH=y 60 + CONFIG_ENV_SPI_EARLY=y 61 + CONFIG_SYS_REDUNDAND_ENVIRONMENT=y 62 + CONFIG_ENV_OFFSET_REDUND=0xE0000 63 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y 64 + CONFIG_APBH_DMA=y 65 + CONFIG_APBH_DMA_BURST=y 66 + CONFIG_APBH_DMA_BURST8=y 67 + CONFIG_DM_GPIO=y 68 + CONFIG_GPIO_HOG=y 69 + CONFIG_DM_PCA953X=y 70 + CONFIG_DM_I2C=y 71 + CONFIG_LED=y 72 + CONFIG_LED_GPIO=y 73 + CONFIG_MISC=y 74 + CONFIG_I2C_EEPROM=y 75 + CONFIG_DM_MMC=y 76 + CONFIG_FSL_USDHC=y 77 + CONFIG_MTD=y 78 + CONFIG_MTD_DEVICE=y 79 + CONFIG_DM_SPI_FLASH=y 80 + CONFIG_SF_DEFAULT_MODE=0 81 + CONFIG_SF_DEFAULT_SPEED=20000000 82 + CONFIG_SPI_FLASH_STMICRO=y 83 + CONFIG_SPI_FLASH_MTD=y 84 + CONFIG_MTD_UBI_FASTMAP=y 85 + CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 86 + CONFIG_PHYLIB=y 87 + CONFIG_PHY_MICREL=y 88 + CONFIG_PHY_MICREL_KSZ90X1=y 89 + CONFIG_DM_ETH=y 90 + CONFIG_MII=y 91 + CONFIG_PHY=y 92 + CONFIG_PINCTRL=y 93 + CONFIG_PINCTRL_IMX6=y 94 + CONFIG_DM_PMIC=y 95 + CONFIG_DM_REGULATOR=y 96 + CONFIG_DM_REGULATOR_FIXED=y 97 + CONFIG_DM_PWM=y 98 + CONFIG_PWM_IMX=y 99 + CONFIG_DM_RTC=y 100 + CONFIG_RTC_DS1307=y 101 + CONFIG_DM_SERIAL=y 102 + CONFIG_SPI=y 103 + CONFIG_DM_SPI=y 104 + CONFIG_MXC_SPI=y 105 + CONFIG_SYSRESET=y 106 + CONFIG_SYSRESET_WATCHDOG=y 107 + CONFIG_USB=y 108 + CONFIG_DM_USB=y 109 + CONFIG_USB_STORAGE=y 110 + CONFIG_DM_VIDEO=y 111 + CONFIG_SYS_WHITE_ON_BLACK=y 112 + CONFIG_DISPLAY=y 113 + CONFIG_VIDEO_IPUV3=y 114 + CONFIG_IMX_WATCHDOG=y 115 + # CONFIG_EFI_LOADER is not set
+27
include/configs/aristainetos2.h
··· 128 128 "${fit_file}\0" \ 129 129 "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ 130 130 "${fit_addr_r} ${rescue_fit_file}\0" 131 + #elif (CONFIG_SYS_BOARD_VERSION == 5) 132 + #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ 133 + "emmcpart=1\0" \ 134 + "emmc_rescue_part=3\0" \ 135 + "emmcdev=1\0" \ 136 + "emmcroot=/dev/mmcblk1p1 rootwait rw\0" \ 137 + "dead=led led_red on\0" \ 138 + "mtdids=nor0=spi0.0\0" \ 139 + "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ 140 + "-(ubi-nor)\0" \ 141 + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ 142 + "bootmode=${bootmode} mmcpart=${mmcpart} " \ 143 + "emmcpart=${emmcpart}\0" \ 144 + "mainboot=echo Booting from eMMC ...; " \ 145 + "run mainargs addmtd addmisc;" \ 146 + "if test -n ${addmiscM}; then run addmiscM;fi;" \ 147 + "if test -n ${addmiscC}; then run addmiscC;fi;" \ 148 + "if test -n ${addmiscD}; then run addmiscD;fi;" \ 149 + "run boot_board_type;" \ 150 + "bootm ${fit_addr_r}\0" \ 151 + "mainargs=setenv bootargs console=${console},${baudrate} " \ 152 + "root=${emmcroot} rootfstype=ext4\0 " \ 153 + "main_load_fit=ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \ 154 + "${fit_file}; " \ 155 + "imi ${fit_addr_r}\0 " \ 156 + "rescue_load_fit=ext4load mmc ${emmcdev}:${emmc_rescue_part} " \ 157 + "${fit_addr_r} ${rescue_fit_file};imi ${fit_addr_r}\0" 131 158 #else 132 159 #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ 133 160 "dead=led led_red on\0" \