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Merge https://source.denx.de/u-boot/custodians/u-boot-watchdog

- rti: support SPL (or re-start) (Alexander)
- rti: drop hack manipulating WDT clock rate (Alexander)

Tom Rini 121e62e8 38a37111

+7 -14
+7 -14
drivers/watchdog/rti_wdt.c
··· 131 131 u32 timer_margin; 132 132 int ret; 133 133 134 - if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY) 134 + timer_margin = timeout_ms * priv->clk_hz / 1000; 135 + timer_margin >>= WDT_PRELOAD_SHIFT; 136 + if (timer_margin > WDT_PRELOAD_MAX) 137 + timer_margin = WDT_PRELOAD_MAX; 138 + 139 + if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY && 140 + readl(priv->regs + RTIDWDPRLD) != timer_margin) 135 141 return -EBUSY; 136 142 137 143 ret = rti_wdt_load_fw(dev); 138 144 if (ret < 0) 139 145 return ret; 140 - 141 - timer_margin = timeout_ms * priv->clk_hz / 1000; 142 - timer_margin >>= WDT_PRELOAD_SHIFT; 143 - if (timer_margin > WDT_PRELOAD_MAX) 144 - timer_margin = WDT_PRELOAD_MAX; 145 146 146 147 writel(timer_margin, priv->regs + RTIDWDPRLD); 147 148 writel(RTIWWDRX_NMI, priv->regs + RTIWWDRXCTRL); ··· 185 186 return ret; 186 187 187 188 priv->clk_hz = clk_get_rate(&clk); 188 - 189 - /* 190 - * If watchdog is running at 32k clock, it is not accurate. 191 - * Adjust frequency down in this case so that it does not expire 192 - * earlier than expected. 193 - */ 194 - if (priv->clk_hz < 32768) 195 - priv->clk_hz = priv->clk_hz * 9 / 10; 196 189 197 190 return 0; 198 191 }