8080: Support Z80 interrupt modes

src/cpu/e8080/e8080.c

···
 
 	c->flags = 0;
 
+	c->int_val = 0;
+	c->nmi_val = 0;
+	c->int_req = 0;
+
+	c->int_cnt = 0;
+	c->int_pc = 0;
+
 	c->mem_rd_ext = NULL;
 	c->mem_wr_ext = NULL;
 
···
 	c->hook_rst = fct;
 }
 
+void e8080_rst (e8080_t *c, unsigned val)
+{
+	e8080_set_clk (c, 0, 11);
+
+	e8080_set_sp (c, e8080_get_sp (c) - 2);
+	e8080_set_mem16 (c, e8080_get_sp (c), e8080_get_pc (c));
+	e8080_set_pc (c, val);
+}
+
+void e8080_set_int (e8080_t *c, unsigned char val)
+{
+	c->int_val = (val != 0);
+
+	if (c->int_val && c->iff) {
+		c->int_req = 1;
+	}
+
+}
+
 unsigned char e8080_get_port8 (e8080_t *c, unsigned addr)
 {
 	if (c->get_port8 != NULL) {
···
 		*val = e8080_get_sp (c);
 		return (0);
 	}
+	else if (strcmp (reg, "i") == 0) {
+		*val = e8080_get_i (c);
+		return (0);
+	}
+	else if (strcmp (reg, "icnt") == 0) {
+		*val = e8080_get_int_cnt (c);
+		return (0);
+	}
+	else if (strcmp (reg, "iff") == 0) {
+		*val = e8080_get_iff1 (c);
+		return (0);
+	}
+	else if (strcmp (reg, "iff2") == 0) {
+		*val = e8080_get_iff2 (c);
+		return (0);
+	}
+	else if (strcmp (reg, "im") == 0) {
+		*val = e8080_get_im (c);
+		return (0);
+	}
+	else if (strcmp (reg, "ipc") == 0) {
+		*val = e8080_get_int_pc (c);
+		return (0);
+	}
 	else if (strcmp (reg, "r") == 0) {
 		*val = e8080_get_r (c);
 		return (0);
···
 		e8080_set_sp (c, val);
 		return (0);
 	}
+	else if (strcmp (reg, "i") == 0) {
+		e8080_set_i (c, val);
+		return (0);
+	}
+	else if (strcmp (reg, "icnt") == 0) {
+		e8080_set_int_cnt (c, val);
+		return (0);
+	}
+	else if (strcmp (reg, "iff") == 0) {
+		e8080_set_iff1 (c, val);
+		return (0);
+	}
+	else if (strcmp (reg, "iff2") == 0) {
+		e8080_set_iff2 (c, val);
+		return (0);
+	}
+	else if (strcmp (reg, "im") == 0) {
+		e8080_set_im (c, val);
+		return (0);
+	}
+	else if (strcmp (reg, "ipc") == 0) {
+		e8080_set_int_pc (c, val);
+		return (0);
+	}
 	else if (strcmp (reg, "r") == 0) {
 		e8080_set_r (c, val);
 		return (0);
···
 	c->iff = 0;
 	c->iff2 = 0;
 
+	c->int_req = 0;
+	c->int_pc = 0;
+	c->im = 0;
+
 	c->halt = 0;
 }
 
+void e8080_interrupt (e8080_t *c)
+{
+	unsigned addr;
+
+	e8080_inc_r (c);
+	c->inscnt += 1;
+
+	if (c->halt) {
+		c->halt = 0;
+		e8080_set_pc (c, e8080_get_pc (c) + 1);
+	}
+
+	c->int_cnt += 1;
+	c->int_pc = e8080_get_pc (c);
+
+	c->int_req = 0;
+
+	if (c->im == 1) {
+		e8080_rst (c, 0x38);
+
+		c->iff = 0;
+		c->iff2 = 0;
+	}
+	else if (c->im == 2) {
+		addr = (e8080_get_i (c) << 8) | 0xff;
+		addr = e8080_get_mem16 (c, addr);
+
+		e8080_rst (c, addr);
+
+		c->iff = 0;
+		c->iff2 = 0;
+	}
+	else {
+		fprintf (stderr, "8080: interrupt mode %u\n", c->im);
+	}
+}
+
 void e8080_execute (e8080_t *c)
 {
 	unsigned short pc;
+	unsigned char  iff;
 
 	if (c->halt) {
-		c->delay = 4;
+		if (c->int_req && c->iff) {
+			e8080_interrupt (c);
+		}
+		else {
+			c->delay += 1;
+		}
 		return;
 	}
 
···
 	}
 #endif
 
+	iff = c->iff;
+
 	c->op[c->inst[0]] (c);
 
 	c->inscnt += 1;
+
+	if (c->int_req && iff && c->iff) {
+		e8080_interrupt (c);
+	}
 }
 
 void e8080_clock (e8080_t *c, unsigned n)

src/cpu/e8080/e8080.h

···
 	unsigned char  iff;
 	unsigned char  iff2;
 
+	unsigned char  im;
+
 	unsigned char  halt;
+
+	unsigned char  int_val;
+	unsigned char  nmi_val;
+	unsigned char  int_req;
+
+	unsigned       int_cnt;
+	unsigned short int_pc;
 
 	void           *mem_rd_ext;
 	void           *mem_wr_ext;
···
 #define e8080_get_l2(c) ((c)->reg2[5]);
 #define e8080_get_psw2(c) ((c)->psw2)
 
+#define e8080_get_halt(c) ((c)->halt)
+#define e8080_get_iff1(c) ((c)->iff)
+#define e8080_get_iff2(c) ((c)->iff2)
+#define e8080_get_im(c) ((c)->im)
+#define e8080_get_int_cnt(c) ((c)->int_cnt)
+#define e8080_get_int_pc(c) ((c)->int_pc)
+
 #define e8080_set_a(c, v) do { (c)->reg[7] = (v) & 0xff; } while (0)
 #define e8080_set_b(c, v) do { (c)->reg[0] = (v) & 0xff; } while (0)
 #define e8080_set_c(c, v) do { (c)->reg[1] = (v) & 0xff; } while (0)
···
 #define e8080_set_h2(c, v) do { (c)->reg2[4] = (v) & 0xff; } while (0)
 #define e8080_set_l2(c, v) do { (c)->reg2[5] = (v) & 0xff; } while (0)
 #define e8080_set_psw2(c, v) do { (c)->psw2 = (v) & 0xff; } while (0)
+
+#define e8080_set_halt(c, v) do { (c)->halt = ((v) != 0); } while (0)
+#define e8080_set_iff1(c, v) do { (c)->iff = ((v) != 0); } while (0)
+#define e8080_set_iff2(c, v) do { (c)->iff2 = ((v) != 0); } while (0)
+#define e8080_set_im(c, v) do { (c)->im = (v); } while (0)
+#define e8080_set_int_cnt(c, v) do { (c)->int_cnt = (v); } while (0)
+#define e8080_set_int_pc(c, v) do { (c)->int_pc = (v) & 0xffff; } while (0)
 
 #define e8080_get_cf(c) (((c)->psw & E8080_FLG_C) != 0)
 #define e8080_get_nf(c) (((c)->psw & E8080_FLG_N) != 0)
···
 void e8080_set_hook_all_fct (e8080_t *c, void *ext, void *fct);
 void e8080_set_hook_undef_fct (e8080_t *c, void *ext, void *fct);
 void e8080_set_hook_rst_fct (e8080_t *c, void *ext, void *fct);
+
+void e8080_rst (e8080_t *c, unsigned val);
+
+void e8080_set_int (e8080_t *c, unsigned char val);
 
 unsigned char e8080_get_port8 (e8080_t *c, unsigned addr);
 void e8080_set_port8 (e8080_t *c, unsigned addr, unsigned char val);

src/cpu/e8080/op_ed.c

···
 /* OP ED 45: RETN */
 static void op_ed_45 (e8080_t *c)
 {
+	e8080_set_iff1 (c, e8080_get_iff2 (c));
 	e8080_set_pc (c, e8080_get_mem16 (c, e8080_get_sp (c)));
 	e8080_set_sp (c, e8080_get_sp (c) + 2);
 	e8080_set_clk (c, 0, 14);
+}
+
+/* OP ED 46: IM 0 */
+static void op_ed_46 (e8080_t *c)
+{
+	c->im = 0;
+
+	e8080_set_clk (c, 2, 8);
 }
 
 /* OP ED 47: LD I, A */
···
 	e8080_set_clk (c, 4, 20);
 }
 
+/* OP ED 56: IM 1 */
+static void op_ed_56 (e8080_t *c)
+{
+	c->im = 1;
+
+	e8080_set_clk (c, 2, 8);
+}
+
 /* OP ED 57: LD A, I */
 static void op_ed_57 (e8080_t *c)
 {
···
 	adr = e8080_uint16 (c->inst[2], c->inst[3]);
 	e8080_set_de (c, e8080_get_mem16 (c, adr));
 	e8080_set_clk (c, 4, 20);
+}
+
+/* OP ED 5E: IM 2 */
+static void op_ed_5e (e8080_t *c)
+{
+	c->im = 2;
+
+	e8080_set_clk (c, 2, 8);
 }
 
 /* OP ED 5F: LD A, R */
···
 	op_ed_ud, op_ed_ud, op_ed_ud, op_ed_ud, op_ed_ud, op_ed_ud, op_ed_ud, op_ed_ud,
 	op_ed_ud, op_ed_ud, op_ed_ud, op_ed_ud, op_ed_ud, op_ed_ud, op_ed_ud, op_ed_ud, /* 30 */
 	op_ed_ud, op_ed_ud, op_ed_ud, op_ed_ud, op_ed_ud, op_ed_ud, op_ed_ud, op_ed_ud,
-	op_ed_40, op_ed_41, op_ed_42, op_ed_43, op_ed_44, op_ed_45, op_ed_ud, op_ed_47, /* 40 */
+	op_ed_40, op_ed_41, op_ed_42, op_ed_43, op_ed_44, op_ed_45, op_ed_46, op_ed_47, /* 40 */
 	op_ed_40, op_ed_41, op_ed_4a, op_ed_4b, op_ed_ud, op_ed_4d, op_ed_ud, op_ed_4f,
-	op_ed_40, op_ed_41, op_ed_52, op_ed_53, op_ed_ud, op_ed_45, op_ed_ud, op_ed_57, /* 50 */
-	op_ed_40, op_ed_41, op_ed_5a, op_ed_5b, op_ed_ud, op_ed_45, op_ed_ud, op_ed_5f,
+	op_ed_40, op_ed_41, op_ed_52, op_ed_53, op_ed_ud, op_ed_45, op_ed_56, op_ed_57, /* 50 */
+	op_ed_40, op_ed_41, op_ed_5a, op_ed_5b, op_ed_ud, op_ed_45, op_ed_5e, op_ed_5f,
 	op_ed_40, op_ed_41, op_ed_62, op_ed_63, op_ed_ud, op_ed_45, op_ed_ud, op_ed_67, /* 60 */
 	op_ed_40, op_ed_41, op_ed_6a, op_ed_6b, op_ed_ud, op_ed_45, op_ed_ud, op_ed_6f,
 	op_ed_70, op_ed_71, op_ed_72, op_ed_73, op_ed_ud, op_ed_45, op_ed_ud, op_ed_ud, /* 70 */

src/cpu/e8080/op_z80.c

···
 static void op_76 (e8080_t *c)
 {
 	c->halt = 1;
-	e8080_set_clk (c, 1, 7);
+	e8080_set_clk (c, 0, 7);
 }
 
 /* OP 80: ADD A, r */

src/cpu/e8080/opcodes.c

···
 static void op_76 (e8080_t *c)
 {
 	c->halt = 1;
-	e8080_set_clk (c, 1, 7);
+	e8080_set_clk (c, 0, 7);
 }
 
 /* OP 80: ADD R */
···
 /* OP F3: DI */
 static void op_f3 (e8080_t *c)
 {
-	c->iff = 0;
-	c->iff2 = 0;
+	e8080_set_iff1 (c, 0);
+	e8080_set_iff2 (c, 0);
 	e8080_set_clk (c, 1, 4);
 }
 
···
 /* OP FB: EI */
 static void op_fb (e8080_t *c)
 {
-	c->iff = 1;
-	c->iff2 = 1;
+	e8080_set_iff1 (c, 1);
+	e8080_set_iff2 (c, 1);
 	e8080_set_clk (c, 1, 4);
 }