openbsd-src/sys/arch/arm/cortex/ at jcs · jcs.org/openbsd-src

jcs.org / openbsd-src

jcs's openbsd hax

openbsd

openbsd-src / sys / arch / arm / cortex /

at jcs 8 files

clockintr: remove clockintr_init(), clockintr_flags

2 years ago

move simplebusvar.h so it can be used without ifdef ok kettenis@ phessler@

2 years ago

clockintr: remove clockintr_init(), clockintr_flags

2 years ago

Constify struct cfattach.

4 years ago

Expose already existing bus_dmamem_alloc_range interface. Needed by recent virtio changes.

8 months ago

Add a cortex bus which represents the ARM MPCore Complex. It will attach only to ARM Cortex A9 and A15 SoCs. The generic interrupt controller and timer will attach to this bus, later a secondary cache controller can be added. The base address for those controllers are figured out using the periphbase register.

13 years ago

Implement ampintcmsi(4) in ampintc(4) to support MSI. The GICv2M is an extension to the GIC controller, which is represented as subnode in the device tree. There can be multiple GICv2Ms, so it makes sense to attach those to ampintc(4) as some kind of simplebus. The GICv2M is simply an interrupt generator that can be used by PCIe devices to ring the door bell. There is no need for further configuration, we only need to find out which SPIs we are allowed to use for MSI and to register an edge triggered interrupt on a (randomly) allocated SPI.

7 years ago

Add a secure monitor call function, so that a secondary cache controller driver can talk to its controller properly.

13 years ago