jcs's openbsd hax
openbsd
0
fork

Configure Feed

Select the types of activity you want to include in your feed.

rkclock: add RK3128 support

+527 -15
+461 -15
sys/dev/fdt/rkclock.c
··· 29 29 #include <dev/ofw/ofw_misc.h> 30 30 #include <dev/ofw/fdt.h> 31 31 32 + #define SEL(l, f) (((1 << (l - f + 1)) - 1) << f) 33 + #define DIV(l, f) SEL(l, f) 34 + 35 + /* RK3128 registers */ 36 + #define RK3128_CRU_APLL_CON(i) (0x0000 + (i) * 4) 37 + #define RK3128_CRU_DPLL_CON(i) (0x0010 + (i) * 4) 38 + #define RK3128_CRU_CPLL_CON(i) (0x0020 + (i) * 4) 39 + #define RK3128_CRU_GPLL_CON(i) (0x0030 + (i) * 4) 40 + #define RK3128_CRU_PLL_POSTDIV1_MASK SEL(14, 12) 41 + #define RK3128_CRU_PLL_POSTDIV1_SHIFT 12 42 + #define RK3128_CRU_PLL_FBDIV_MASK SEL(11, 0) 43 + #define RK3128_CRU_PLL_FBDIV_SHIFT 0 44 + #define RK3128_CRU_PLL_DSMPD_MASK (1 << 12) 45 + #define RK3128_CRU_PLL_DSMPD_SHIFT 12 46 + #define RK3128_CRU_PLL_PLL_LOCK (1 << 10) 47 + #define RK3128_CRU_PLL_POSTDIV2_MASK SEL(8, 6) 48 + #define RK3128_CRU_PLL_POSTDIV2_SHIFT 6 49 + #define RK3128_CRU_PLL_REFDIV_MASK SEL(5, 0) 50 + #define RK3128_CRU_PLL_REFDIV_SHIFT 0 51 + #define RK3128_CRU_PLL_FRACDIV_MASK SEL(23, 0) 52 + #define RK3128_CRU_PLL_FRACDIV_SHIFT 0 53 + #define RK3128_CRU_MODE_CON 0x0040 54 + #define RK3128_CRU_MODE_PLL_WORK_MODE_MASK 0x3 55 + #define RK3128_CRU_MODE_PLL_WORK_MODE_SLOW 0x0 56 + #define RK3128_CRU_MODE_PLL_WORK_MODE_NORMAL 0x1 57 + #define RK3128_CRU_CLKSEL_CON(i) (0x0044 + (i) * 4) 58 + #define RK3128_CRU_CLKGATE_CON(i) (0x00d0 + (i) * 4) 59 + #define RK3128_CRU_SOFTRST_CON(i) (0x0110 + (i) * 4) 60 + 32 61 /* RK3288 registers */ 33 62 #define RK3288_CRU_APLL_CON(i) (0x0000 + (i) * 4) 34 63 #define RK3288_CRU_CPLL_CON(i) (0x0020 + (i) * 4) ··· 247 276 uint32_t flags; 248 277 }; 249 278 250 - #define SEL(l, f) (((1 << (l - f + 1)) - 1) << f) 251 - #define DIV(l, f) SEL(l, f) 252 - 253 279 #define FIXED_PARENT (1 << 0) 254 280 #define SET_PARENT (1 << 1) 255 281 ··· 285 311 struct cfdriver rkclock_cd = { 286 312 NULL, "rkclock", DV_DULL 287 313 }; 314 + 315 + void rk3128_init(struct rkclock_softc *); 316 + uint32_t rk3128_get_frequency(void *, uint32_t *); 317 + int rk3128_set_frequency(void *, uint32_t *, uint32_t); 318 + int rk3128_set_mmc_frequency(void *, uint32_t, uint32_t, uint32_t); 319 + int rk3128_set_parent(void *, uint32_t *, uint32_t *); 320 + void rk3128_enable(void *, uint32_t *, int); 321 + void rk3128_reset(void *, uint32_t *, int); 288 322 289 323 void rk3288_init(struct rkclock_softc *); 290 324 uint32_t rk3288_get_frequency(void *, uint32_t *); ··· 368 402 369 403 const struct rkclock_compat rkclock_compat[] = { 370 404 { 405 + "rockchip,rk3128-cru", NULL, 0, rk3128_init, 406 + rk3128_enable, rk3128_get_frequency, 407 + rk3128_set_frequency, rk3128_set_parent, 408 + rk3128_reset 409 + }, 410 + { 371 411 "rockchip,rk3288-cru", NULL, 0, rk3288_init, 372 412 rk3288_enable, rk3288_get_frequency, 373 413 rk3288_set_frequency, NULL, ··· 548 588 549 589 /* Derive maximum value from mask. */ 550 590 max_div_con = clk->div_mask >> (ffs(clk->div_mask) - 1); 551 - 591 + 552 592 parent_freq = sc->sc_cd.cd_get_frequency(sc, &idx); 553 593 div = (parent_freq + freq - 1) / freq; 554 594 div_con = (div > 0 ? div - 1 : 0); ··· 571 611 rkclock_get_frequency(struct rkclock_softc *sc, uint32_t idx) 572 612 { 573 613 const struct rkclock *clk; 574 - uint32_t reg, mux, div_con; 614 + uint32_t reg, mux, div_con, ret; 575 615 int shift; 576 616 577 617 clk = rkclock_lookup(sc, idx); ··· 592 632 else 593 633 div_con = (reg & clk->div_mask) >> shift; 594 634 595 - if (clk->parents[mux] == 0) { 596 - printf("%s: parent 0x%08x\n", __func__, idx); 635 + if (clk->parents[mux] == 0) 597 636 return 0; 598 - } 599 637 idx = clk->parents[mux]; 600 - return sc->sc_cd.cd_get_frequency(sc, &idx) / (div_con + 1); 638 + ret = sc->sc_cd.cd_get_frequency(sc, &idx); 639 + return ret / (div_con + 1); 601 640 } 602 641 603 642 int ··· 611 650 612 651 clk = rkclock_lookup(sc, idx); 613 652 if (clk == NULL) { 614 - printf("%s(%s, %u, %u)\n", __func__, sc->sc_dev.dv_xname, 615 - idx, freq); 653 + printf("%s(%s, %u, %u) failed lookup\n", __func__, 654 + sc->sc_dev.dv_xname, idx, freq); 616 655 return -1; 617 656 } 618 657 ··· 623 662 else 624 663 mux = (reg & clk->sel_mask) >> sel_shift; 625 664 626 - if (clk->parents[mux] == 0) { 627 - printf("%s(%s, %u, %u) parent\n", __func__, 628 - sc->sc_dev.dv_xname, idx, freq); 665 + if (clk->parents[mux] == 0) 629 666 return 0; 630 - } 631 667 632 668 if (clk->flags & SET_PARENT) { 633 669 parent = clk->parents[mux]; ··· 723 759 shift = ffs(clk->sel_mask) - 1; 724 760 HWRITE4(sc, clk->reg, clk->sel_mask << 16 | mux << shift); 725 761 return 0; 762 + } 763 + 764 + /* 765 + * Rockchip RK3128 766 + */ 767 + 768 + const struct rkclock rk3128_clocks[] = { 769 + { 770 + RK3128_ARMCLK, RK3128_CRU_CLKSEL_CON(0), 771 + (1 << 7), DIV(4, 0), 772 + { RK3128_PLL_APLL, RK3128_PLL_GPLL_DIV2 } 773 + }, 774 + { 775 + RK3128_SCLK_SDMMC, RK3128_CRU_CLKSEL_CON(11), 776 + SEL(7, 6), DIV(5, 0), 777 + { RK3128_PLL_CPLL, RK3128_PLL_GPLL, RK3128_PLL_GPLL_DIV2, 778 + RK3128_XIN24M } 779 + }, 780 + { 781 + RK3128_SCLK_SDIO, RK3128_CRU_CLKSEL_CON(12), 782 + SEL(7, 6), DIV(5, 0), 783 + { RK3128_PLL_CPLL, RK3128_PLL_GPLL, RK3128_PLL_GPLL_DIV2, 784 + RK3128_XIN24M } 785 + }, 786 + { 787 + RK3128_SCLK_EMMC, RK3128_CRU_CLKSEL_CON(12), 788 + SEL(15, 14), DIV(13, 8), 789 + { RK3128_PLL_CPLL, RK3128_PLL_GPLL, RK3128_PLL_GPLL_DIV2, 790 + RK3128_XIN24M } 791 + }, 792 + { 793 + RK3128_SCLK_UART0, RK3128_CRU_CLKSEL_CON(13), 794 + SEL(12, 12), DIV(6, 0), 795 + { RK3128_PLL_CPLL, RK3128_PLL_GPLL, RK3128_PLL_GPLL_DIV2, 796 + RK3128_SCLK_USB480M } 797 + }, 798 + { 799 + RK3128_SCLK_MAC, RK3128_CRU_CLKSEL_CON(5), 800 + SEL(7, 6), DIV(4, 0), 801 + { RK3128_PLL_CPLL, RK3128_PLL_GPLL, RK3128_PLL_GPLL_DIV2 } 802 + }, 803 + { 804 + RK3128_SCLK_MAC_SRC, RK3128_CRU_CLKSEL_CON(5), 805 + SEL(7, 6), DIV(4, 0), 806 + { RK3128_PLL_CPLL, RK3128_PLL_GPLL, RK3128_PLL_GPLL_DIV2 } 807 + }, 808 + { 809 + RK3128_PCLK_I2C0, RK3128_CRU_CLKSEL_CON(10), 810 + SEL(15, 14), DIV(4, 0), 811 + { RK3128_PLL_GPLL, RK3128_PLL_CPLL, RK3128_PLL_GPLL_DIV2, 812 + RK3128_PLL_GPLL_DIV3 } 813 + }, 814 + { 815 + RK3128_PCLK_I2C1, RK3128_CRU_CLKSEL_CON(10), 816 + SEL(15, 14), DIV(4, 0), 817 + { RK3128_PLL_GPLL, RK3128_PLL_CPLL, RK3128_PLL_GPLL_DIV2, 818 + RK3128_PLL_GPLL_DIV3 } 819 + }, 820 + { 821 + RK3128_PCLK_I2C2, RK3128_CRU_CLKSEL_CON(10), 822 + SEL(15, 14), DIV(4, 0), 823 + { RK3128_PLL_GPLL, RK3128_PLL_CPLL, RK3128_PLL_GPLL_DIV2, 824 + RK3128_PLL_GPLL_DIV3 } 825 + }, 826 + { 827 + RK3128_PCLK_I2C3, RK3128_CRU_CLKSEL_CON(10), 828 + SEL(15, 14), DIV(4, 0), 829 + { RK3128_PLL_GPLL, RK3128_PLL_CPLL, RK3128_PLL_GPLL_DIV2, 830 + RK3128_PLL_GPLL_DIV3 } 831 + }, 832 + { 833 + RK3128_PCLK_PWM, RK3128_CRU_CLKSEL_CON(10), 834 + SEL(15, 14), DIV(4, 0), 835 + { RK3128_PLL_GPLL, RK3128_PLL_CPLL, RK3128_PLL_GPLL_DIV2, 836 + RK3128_PLL_GPLL_DIV3 } 837 + }, 838 + { 839 + RK3128_DCLK_VOP, RK3128_CRU_CLKSEL_CON(27), 840 + SEL(1, 0), DIV(15, 8), 841 + { RK3128_PLL_CPLL, RK3128_PLL_GPLL, RK3128_PLL_GPLL_DIV2, 842 + RK3128_PLL_GPLL_DIV3 } 843 + }, 844 + {} 845 + }; 846 + 847 + void 848 + rk3128_init(struct rkclock_softc *sc) 849 + { 850 + int i; 851 + 852 + /* The code below assumes all clocks are enabled. Check this! */ 853 + for (i = 0; i <= 10; i++) { 854 + if (HREAD4(sc, RK3128_CRU_CLKGATE_CON(i)) != 0x00000000) { 855 + printf("CRU_CLKGATE_CON%d: 0x%08x\n", i, 856 + HREAD4(sc, RK3128_CRU_CLKGATE_CON(i))); 857 + } 858 + } 859 + 860 + sc->sc_clocks = rk3128_clocks; 861 + } 862 + 863 + uint32_t 864 + rk3128_get_pll(struct rkclock_softc *sc, bus_size_t base) 865 + { 866 + uint32_t fbdiv, postdiv1, postdiv2, refdiv, con; 867 + uint32_t dsmpd, fracdiv; 868 + uint64_t frac = 0; 869 + 870 + con = HREAD4(sc, RK3128_CRU_MODE_CON); 871 + 872 + switch ((con >> (base >> 2)) & 0x1) { 873 + case 0: 874 + /* slow */ 875 + return 24000000; 876 + case 1: 877 + /* normal */ 878 + con = HREAD4(sc, base); 879 + postdiv1 = (con & RK3128_CRU_PLL_POSTDIV1_MASK) >> 880 + RK3128_CRU_PLL_POSTDIV1_SHIFT; 881 + fbdiv = (con & RK3128_CRU_PLL_FBDIV_MASK) >> 882 + RK3128_CRU_PLL_FBDIV_SHIFT; 883 + 884 + con = HREAD4(sc, base + 0x0004); 885 + dsmpd = (con & RK3128_CRU_PLL_DSMPD_MASK) >> 886 + RK3128_CRU_PLL_DSMPD_SHIFT; 887 + fracdiv = (con & RK3128_CRU_PLL_FRACDIV_MASK) >> 888 + RK3128_CRU_PLL_FRACDIV_SHIFT; 889 + postdiv2 = (con & RK3128_CRU_PLL_POSTDIV2_MASK) >> 890 + RK3128_CRU_PLL_POSTDIV2_SHIFT; 891 + refdiv = (con & RK3128_CRU_PLL_REFDIV_MASK) >> 892 + RK3128_CRU_PLL_REFDIV_SHIFT; 893 + 894 + if (dsmpd == 0) 895 + frac = (24000000ULL * fracdiv / refdiv) >> 24; 896 + return ((24000000ULL * fbdiv / refdiv) + frac) / postdiv1 / 897 + postdiv2; 898 + default: 899 + return 32768; 900 + } 901 + } 902 + 903 + int 904 + rk3128_set_pll(struct rkclock_softc *sc, bus_size_t base, uint32_t freq) 905 + { 906 + uint32_t fbdiv, postdiv1, postdiv2, refdiv; 907 + int mode_shift; 908 + 909 + /* 910 + * It is not clear whether all combinations of the clock 911 + * dividers result in a stable clock. Therefore this function 912 + * only supports a limited set of PLL clock rates. For now 913 + * this set covers all the CPU frequencies supported by the 914 + * Linux kernel. 915 + */ 916 + switch (freq) { 917 + case 1608000000U: 918 + case 1584000000U: 919 + case 1560000000U: 920 + case 1536000000U: 921 + case 1512000000U: 922 + case 1488000000U: 923 + case 1464000000U: 924 + case 1440000000U: 925 + case 1416000000U: 926 + case 1392000000U: 927 + case 1368000000U: 928 + case 1344000000U: 929 + case 1320000000U: 930 + case 1296000000U: 931 + case 1272000000U: 932 + case 1248000000U: 933 + case 1200000000U: 934 + case 1104000000U: 935 + postdiv1 = postdiv2 = refdiv = 1; 936 + break; 937 + case 1188000000U: 938 + refdiv = 2; postdiv1 = postdiv2 = 1; 939 + break; 940 + case 1100000000U: 941 + refdiv = 12; postdiv1 = postdiv2 = 1; 942 + break; 943 + case 1000000000U: 944 + refdiv = 6; postdiv1 = postdiv2 = 1; 945 + break; 946 + case 1008000000U: 947 + case 984000000U: 948 + case 960000000U: 949 + case 936000000U: 950 + case 912000000U: 951 + case 888000000U: 952 + case 864000000U: 953 + case 840000000U: 954 + case 816000000U: 955 + case 696000000U: 956 + case 624000000U: 957 + postdiv1 = 2; postdiv2 = refdiv = 1; 958 + break; 959 + case 900000000U: 960 + refdiv = 4; postdiv1 = 2; postdiv2 = 1; 961 + break; 962 + case 800000000U: 963 + case 700000000U: 964 + case 500000000U: 965 + refdiv = 6; postdiv1 = 2; postdiv2 = 1; 966 + break; 967 + case 600000000U: 968 + case 504000000U: 969 + postdiv1 = 3; postdiv2 = refdiv = 1; 970 + break; 971 + case 594000000U: 972 + refdiv = 2; postdiv1 = 2; postdiv2 = 1; 973 + break; 974 + case 408000000U: 975 + case 312000000U: 976 + postdiv1 = postdiv2 = 2; refdiv = 1; 977 + break; 978 + case 216000000U: 979 + postdiv1 = 4; postdiv2 = 2; refdiv = 1; 980 + break; 981 + case 96000000U: 982 + postdiv1 = postdiv2 = 4; refdiv = 1; 983 + break; 984 + default: 985 + printf("%s: %u Hz\n", __func__, freq); 986 + return -1; 987 + } 988 + 989 + /* Calculate feedback divider. */ 990 + fbdiv = freq * postdiv1 * postdiv2 * refdiv / 24000000; 991 + 992 + /* 993 + * Select slow mode to guarantee a stable clock while we're 994 + * adjusting the PLL. 995 + */ 996 + mode_shift = base >> 2; 997 + HWRITE4(sc, RK3128_CRU_MODE_CON, 998 + (RK3128_CRU_MODE_PLL_WORK_MODE_MASK << 16 | 999 + RK3128_CRU_MODE_PLL_WORK_MODE_SLOW) << mode_shift); 1000 + 1001 + /* Set PLL rate. */ 1002 + HWRITE4(sc, base, 1003 + RK3128_CRU_PLL_POSTDIV1_MASK << 16 | 1004 + postdiv1 << RK3128_CRU_PLL_POSTDIV1_SHIFT | 1005 + RK3128_CRU_PLL_FBDIV_MASK << 16 | 1006 + fbdiv << RK3128_CRU_PLL_FBDIV_SHIFT); 1007 + HWRITE4(sc, base + 0x0004, 1008 + RK3128_CRU_PLL_DSMPD_MASK << 16 | RK3128_CRU_PLL_DSMPD_MASK | 1009 + RK3128_CRU_PLL_POSTDIV2_MASK << 16 | 1010 + postdiv2 << RK3128_CRU_PLL_POSTDIV2_SHIFT | 1011 + RK3128_CRU_PLL_REFDIV_MASK << 16 | 1012 + refdiv << RK3128_CRU_PLL_REFDIV_SHIFT); 1013 + 1014 + /* Wait for PLL to stabilize. */ 1015 + while ((HREAD4(sc, base + 0x0004) & RK3128_CRU_PLL_PLL_LOCK) == 0) 1016 + delay(10); 1017 + 1018 + /* Switch back to normal mode. */ 1019 + HWRITE4(sc, RK3128_CRU_MODE_CON, 1020 + (RK3128_CRU_MODE_PLL_WORK_MODE_MASK << 16 | 1021 + RK3128_CRU_MODE_PLL_WORK_MODE_NORMAL) << mode_shift); 1022 + 1023 + return 0; 1024 + } 1025 + 1026 + uint32_t 1027 + rk3128_get_frequency(void *cookie, uint32_t *cells) 1028 + { 1029 + struct rkclock_softc *sc = cookie; 1030 + uint32_t idx = cells[0]; 1031 + 1032 + switch (idx) { 1033 + case RK3128_PLL_APLL: 1034 + return rk3128_get_pll(sc, RK3128_CRU_APLL_CON(0)); 1035 + case RK3128_PLL_DPLL: 1036 + return rk3128_get_pll(sc, RK3128_CRU_DPLL_CON(0)); 1037 + case RK3128_PLL_CPLL: 1038 + return rk3128_get_pll(sc, RK3128_CRU_CPLL_CON(0)); 1039 + case RK3128_PLL_GPLL: 1040 + return rk3128_get_pll(sc, RK3128_CRU_GPLL_CON(0)); 1041 + case RK3128_PLL_GPLL_DIV2: 1042 + return rk3128_get_pll(sc, RK3128_CRU_GPLL_CON(0)) / 2; 1043 + case RK3128_PLL_GPLL_DIV3: 1044 + return rk3128_get_pll(sc, RK3128_CRU_GPLL_CON(0)) / 3; 1045 + case RK3128_XIN24M: 1046 + return 24000000; 1047 + default: 1048 + return rkclock_get_frequency(sc, idx); 1049 + } 1050 + } 1051 + 1052 + int 1053 + rk3128_set_frequency(void *cookie, uint32_t *cells, uint32_t freq) 1054 + { 1055 + struct rkclock_softc *sc = cookie; 1056 + uint32_t idx = cells[0]; 1057 + int error; 1058 + 1059 + switch (idx) { 1060 + case RK3128_PLL_APLL: 1061 + return rk3128_set_pll(sc, RK3128_CRU_APLL_CON(0), freq); 1062 + case RK3128_ARMCLK: 1063 + idx = RK3128_PLL_APLL; 1064 + error = rk3128_set_frequency(sc, &idx, freq); 1065 + if (error == 0) { 1066 + HWRITE4(sc, RK3128_CRU_CLKSEL_CON(0), 1067 + ((1 << 7) | 0x1f) << 16); 1068 + } 1069 + return error; 1070 + default: 1071 + return rkclock_set_frequency(sc, idx, freq); 1072 + } 1073 + } 1074 + 1075 + void 1076 + rk3128_enable(void *cookie, uint32_t *cells, int on) 1077 + { 1078 + struct rkclock_softc *sc = cookie; 1079 + uint32_t idx = cells[0]; 1080 + uint32_t reg, bit; 1081 + 1082 + switch (idx) { 1083 + case RK3128_SCLK_SDMMC: 1084 + case RK3128_SCLK_EMMC: 1085 + case RK3128_SCLK_UART0: 1086 + case RK3128_SCLK_UART1: 1087 + case RK3128_SCLK_UART2: 1088 + case RK3128_SCLK_MAC: 1089 + case RK3128_SCLK_MAC_RX: 1090 + case RK3128_SCLK_MAC_TX: 1091 + case RK3128_SCLK_SDMMC_DRV: 1092 + case RK3128_SCLK_SDIO_DRV: 1093 + case RK3128_SCLK_EMMC_DRV: 1094 + case RK3128_SCLK_SDMMC_SAMPLE: 1095 + case RK3128_SCLK_SDIO_SAMPLE: 1096 + case RK3128_SCLK_EMMC_SAMPLE: 1097 + case RK3128_SCLK_OTGPHY0: 1098 + case RK3128_SCLK_OTGPHY1: 1099 + case RK3128_ACLK_GMAC: 1100 + case RK3128_PCLK_I2C0: 1101 + case RK3128_PCLK_I2C1: 1102 + case RK3128_PCLK_I2C2: 1103 + case RK3128_PCLK_I2C3: 1104 + case RK3128_PCLK_PWM: 1105 + case RK3128_PCLK_TSADC: 1106 + case RK3128_PCLK_GMAC: 1107 + case RK3128_HCLK_SDMMC: 1108 + case RK3128_HCLK_EMMC: 1109 + case RK3128_HCLK_HOST2: 1110 + /* Enabled by default. */ 1111 + return; 1112 + case RK3128_SCLK_SDIO: 1113 + reg = 2; bit = 13; 1114 + break; 1115 + case RK3128_HCLK_SDIO: 1116 + reg = 5; bit = 11; 1117 + break; 1118 + case RK3128_ACLK_VIO0: 1119 + reg = 3; bit = 0; 1120 + break; 1121 + case RK3128_DCLK_VOP: 1122 + reg = 3; bit = 1; 1123 + break; 1124 + case RK3128_ACLK_VIO1: 1125 + reg = 1; bit = 4; 1126 + break; 1127 + case RK3128_ACLK_LCDC0: 1128 + reg = 6; bit = 0; 1129 + break; 1130 + case RK3128_HCLK_LCDC0: 1131 + reg = 6; bit = 1; 1132 + break; 1133 + case RK3128_HCLK_VIO: 1134 + reg = 0; bit = 11; 1135 + break; 1136 + case RK3128_SCLK_MIPI_24M: 1137 + reg = 2; bit = 8; 1138 + break; 1139 + case RK3128_PCLK_MIPIPHY: 1140 + reg = 9; bit = 14; 1141 + break; 1142 + case RK3128_PCLK_MIPI_HOST: 1143 + reg = 9; bit = 5; 1144 + break; 1145 + default: 1146 + printf("%s: %d\n", __func__, idx); 1147 + return; 1148 + } 1149 + 1150 + /* gate register: 1 = gated (disabled), 0 = ungated (enabled) */ 1151 + HWRITE4(sc, RK3128_CRU_CLKGATE_CON(reg), 1152 + (1 << bit) << 16 | (on ? 0 : (1 << bit))); 1153 + } 1154 + 1155 + int 1156 + rk3128_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells) 1157 + { 1158 + struct rkclock_softc *sc = cookie; 1159 + 1160 + return rkclock_set_parent(sc, cells[0], pcells[1]); 1161 + } 1162 + 1163 + void 1164 + rk3128_reset(void *cookie, uint32_t *cells, int on) 1165 + { 1166 + struct rkclock_softc *sc = cookie; 1167 + uint32_t idx = cells[0]; 1168 + uint32_t mask = (1 << (idx % 16)); 1169 + 1170 + HWRITE4(sc, RK3128_CRU_SOFTRST_CON(idx / 16), 1171 + mask << 16 | (on ? mask : 0)); 726 1172 } 727 1173 728 1174 /*
+66
sys/dev/fdt/rkclock_clocks.h
··· 1 1 /* Public Domain */ 2 2 3 3 /* 4 + * RK3128 clocks. 5 + */ 6 + 7 + #define RK3128_PLL_APLL 1 8 + #define RK3128_PLL_DPLL 2 9 + #define RK3128_PLL_CPLL 3 10 + #define RK3128_PLL_GPLL 4 11 + #define RK3128_ARMCLK 5 12 + #define RK3128_PLL_GPLL_DIV2 6 13 + #define RK3128_PLL_GPLL_DIV3 7 14 + 15 + #define RK3128_SCLK_SDMMC 68 16 + #define RK3128_SCLK_SDIO 69 17 + #define RK3128_SCLK_EMMC 71 18 + #define RK3128_SCLK_UART0 77 19 + #define RK3128_SCLK_UART1 78 20 + #define RK3128_SCLK_UART2 79 21 + #define RK3128_SCLK_SDMMC_DRV 114 22 + #define RK3128_SCLK_SDIO_DRV 115 23 + #define RK3128_SCLK_EMMC_DRV 117 24 + #define RK3128_SCLK_SDMMC_SAMPLE 118 25 + #define RK3128_SCLK_SDIO_SAMPLE 119 26 + #define RK3128_SCLK_EMMC_SAMPLE 121 27 + #define RK3128_SCLK_MAC_SRC 124 28 + #define RK3128_SCLK_MAC 126 29 + #define RK3128_SCLK_MAC_RX 129 30 + #define RK3128_SCLK_MAC_TX 130 31 + #define RK3128_SCLK_OTGPHY0 142 32 + #define RK3128_SCLK_OTGPHY1 143 33 + #define RK3128_SCLK_MIPI_24M 148 34 + #define RK3128_SCLK_USB480M 154 35 + 36 + #define RK3128_DCLK_VOP 190 37 + 38 + #define RK3128_ACLK_VIO0 192 39 + #define RK3128_ACLK_VIO1 193 40 + #define RK3128_ACLK_LCDC0 204 41 + #define RK3128_ACLK_GMAC 212 42 + 43 + #define RK3128_PCLK_MIPIPHY 325 44 + #define RK3128_PCLK_I2C0 332 45 + #define RK3128_PCLK_I2C1 333 46 + #define RK3128_PCLK_I2C2 334 47 + #define RK3128_PCLK_I2C3 335 48 + #define RK3128_PCLK_TSADC 344 49 + #define RK3128_PCLK_PWM 350 50 + #define RK3128_PCLK_GMAC 367 51 + #define RK3128_PCLK_MIPI_HOST 370 52 + 53 + #define RK3128_HCLK_SDMMC 456 54 + #define RK3128_HCLK_SDIO 457 55 + #define RK3128_HCLK_EMMC 459 56 + #define RK3128_HCLK_LCDC0 463 57 + #define RK3128_HCLK_VIO 466 58 + #define RK3128_HCLK_HOST2 473 59 + 60 + #define RK3128_SRST_I2C0 43 61 + #define RK3128_SRST_GMAC 56 62 + #define RK3128_SRST_SDMMC 81 63 + #define RK3128_SRST_SDIO 82 64 + #define RK3128_SRST_EMMC 83 65 + #define RK3128_SRST_SARADC 87 66 + 67 + #define RK3128_XIN24M 1023 68 + 69 + /* 4 70 * RK3288 clocks. 5 71 */ 6 72