Reactos

[XDK] Add definitions required for newer storage class drivers (cdrom) That introduced some warnings in the current code which were corrected as well

CORE-17129

+864 -10
+1
drivers/storage/class/ramdisk/ramdisk.c
··· 1733 1733 } 1734 1734 1735 1735 case BusQueryDeviceSerialNumber: 1736 + case BusQueryContainerID: 1736 1737 { 1737 1738 /* Nothing to do */ 1738 1739 break;
+1 -1
ntoskrnl/mm/ARM3/mdlsup.c
··· 666 666 IN MEMORY_CACHING_TYPE CacheType, 667 667 IN PVOID BaseAddress, 668 668 IN ULONG BugCheckOnFailure, 669 - IN MM_PAGE_PRIORITY Priority) 669 + IN ULONG Priority) // MM_PAGE_PRIORITY 670 670 { 671 671 PVOID Base; 672 672 PPFN_NUMBER MdlPages, LastPage;
+6
sdk/include/ndk/mmtypes.h
··· 125 125 PagedPoolCacheAligned, 126 126 NonPagedPoolCacheAlignedMustS, 127 127 MaxPoolType, 128 + 129 + NonPagedPoolBase = 0, 130 + NonPagedPoolBaseMustSucceed = NonPagedPoolBase + 2, 131 + NonPagedPoolBaseCacheAligned = NonPagedPoolBase + 4, 132 + NonPagedPoolBaseCacheAlignedMustS = NonPagedPoolBase + 6, 133 + 128 134 NonPagedPoolSession = 32, 129 135 PagedPoolSession, 130 136 NonPagedPoolMustSucceedSession,
+50
sdk/include/xdk/exfuncs.h
··· 950 950 _In_ PLARGE_INTEGER LocalTime, 951 951 _Out_ PLARGE_INTEGER SystemTime); 952 952 953 + #if (NTDDI_VERSION >= NTDDI_WINBLUE) 954 + 955 + #define EX_TIMER_HIGH_RESOLUTION 0x4 956 + #define EX_TIMER_NO_WAKE 0x8 957 + #define EX_TIMER_UNLIMITED_TOLERANCE ((LONGLONG)-1) 958 + #define EX_TIMER_NOTIFICATION (1UL << 31) 959 + 960 + NTKERNELAPI 961 + PEX_TIMER 962 + NTAPI 963 + ExAllocateTimer( 964 + _In_opt_ PEXT_CALLBACK Callback, 965 + _In_opt_ PVOID CallbackContext, 966 + _In_ ULONG Attributes); 967 + 968 + NTKERNELAPI 969 + BOOLEAN 970 + NTAPI 971 + ExSetTimer( 972 + _In_ PEX_TIMER Timer, 973 + _In_ LONGLONG DueTime, 974 + _In_ LONGLONG Period, 975 + _In_opt_ PEXT_SET_PARAMETERS Parameters); 976 + 977 + NTKERNELAPI 978 + BOOLEAN 979 + NTAPI 980 + ExCancelTimer( 981 + _Inout_ PEX_TIMER Timer, 982 + _In_opt_ PEXT_CANCEL_PARAMETERS Parameters); 983 + 984 + NTKERNELAPI 985 + BOOLEAN 986 + NTAPI 987 + ExDeleteTimer( 988 + _In_ PEX_TIMER Timer, 989 + _In_ BOOLEAN Cancel, 990 + _In_ BOOLEAN Wait, 991 + _In_opt_ PEXT_DELETE_PARAMETERS Parameters); 992 + 993 + FORCEINLINE 994 + VOID 995 + ExInitializeSetTimerParameters( 996 + _Out_ PEXT_SET_PARAMETERS Parameters) 997 + { 998 + ASSERT(FALSE); 999 + } 1000 + 1001 + #endif // NTDDI_WINBLUE 1002 + 953 1003 _IRQL_requires_max_(DISPATCH_LEVEL) 954 1004 NTKERNELAPI 955 1005 VOID
+46
sdk/include/xdk/extypes.h
··· 277 277 #define IF_NTOS_DEBUG(FlagName) if(FALSE) 278 278 #endif 279 279 280 + #if (NTDDI_VERSION >= NTDDI_WINBLUE) 281 + 282 + typedef struct _EXT_SET_PARAMETERS_V0 283 + { 284 + ULONG Version; 285 + ULONG Reserved; 286 + LONGLONG NoWakeTolerance; 287 + } EXT_SET_PARAMETERS, *PEXT_SET_PARAMETERS; 288 + 289 + typedef EXT_SET_PARAMETERS KT2_SET_PARAMETERS, *PKT2_SET_PARAMETERS; 290 + 291 + typedef struct _EX_TIMER *PEX_TIMER; 292 + 293 + _Function_class_(EXT_CALLBACK) 294 + _IRQL_requires_(DISPATCH_LEVEL) 295 + _IRQL_requires_same_ 296 + typedef 297 + VOID 298 + NTAPI 299 + EXT_CALLBACK( 300 + _In_ PEX_TIMER Timer, 301 + _In_opt_ PVOID Context); 302 + 303 + typedef EXT_CALLBACK *PEXT_CALLBACK; 304 + 305 + _Function_class_(EXT_DELETE_CALLBACK) 306 + _IRQL_requires_(DISPATCH_LEVEL) 307 + _IRQL_requires_same_ 308 + typedef 309 + VOID 310 + NTAPI 311 + EXT_DELETE_CALLBACK( 312 + _In_opt_ PVOID Context); 313 + 314 + typedef EXT_DELETE_CALLBACK *PEXT_DELETE_CALLBACK; 315 + typedef PVOID PEXT_CANCEL_PARAMETERS; 316 + typedef struct _EXT_DELETE_PARAMETERS 317 + { 318 + ULONG Version; 319 + ULONG Reserved; 320 + PEXT_DELETE_CALLBACK DeleteCallback; 321 + PVOID DeleteContext; 322 + } EXT_DELETE_PARAMETERS, *PEXT_DELETE_PARAMETERS; 323 + 324 + #endif // NTDDI_WINBLUE 325 + 280 326 $endif (_WDMDDK_) 281 327 $if (_NTDDK_) 282 328 typedef struct _ZONE_SEGMENT_HEADER {
+477 -3
sdk/include/xdk/iotypes.h
··· 119 119 120 120 typedef USHORT IRQ_DEVICE_POLICY, *PIRQ_DEVICE_POLICY; 121 121 122 - typedef enum _IRQ_DEVICE_POLICY_USHORT { 122 + enum _IRQ_DEVICE_POLICY_USHORT { 123 123 IrqPolicyMachineDefault = 0, 124 124 IrqPolicyAllCloseProcessors = 1, 125 125 IrqPolicyOneCloseProcessor = 2, ··· 391 391 _In_ PIO_INTERRUPT_MESSAGE_INFO InterruptMessageTable; 392 392 } ConnectionContext; 393 393 } IO_DISCONNECT_INTERRUPT_PARAMETERS, *PIO_DISCONNECT_INTERRUPT_PARAMETERS; 394 + 395 + typedef struct _IO_REPORT_INTERRUPT_ACTIVE_STATE_PARAMETERS 396 + { 397 + ULONG Version; 398 + union 399 + { 400 + PVOID Generic; 401 + PKINTERRUPT InterruptObject; 402 + PIO_INTERRUPT_MESSAGE_INFO InterruptMessageTable; 403 + } ConnectionContext; 404 + } IO_REPORT_INTERRUPT_ACTIVE_STATE_PARAMETERS, *PIO_REPORT_INTERRUPT_ACTIVE_STATE_PARAMETERS; 394 405 395 406 typedef enum _IO_ACCESS_TYPE { 396 407 ReadAccess, ··· 920 931 ULONG NonDynamic:1; 921 932 ULONG WarmEjectSupported:1; 922 933 ULONG NoDisplayInUI:1; 923 - ULONG Reserved:14; 934 + ULONG Reserved1:1; 935 + ULONG WakeFromInterrupt:1; 936 + ULONG SecureDevice:1; 937 + ULONG ChildOfVgaEnabledBridge:1; 938 + ULONG DecodeIoOnBoot:1; 939 + ULONG Reserved:9; 924 940 ULONG Address; 925 941 ULONG UINumber; 926 942 DEVICE_POWER_STATE DeviceState[PowerSystemMaximum]; ··· 2027 2043 #define DEVICE_DESCRIPTION_VERSION 0x0000 2028 2044 #define DEVICE_DESCRIPTION_VERSION1 0x0001 2029 2045 #define DEVICE_DESCRIPTION_VERSION2 0x0002 2046 + #define DEVICE_DESCRIPTION_VERSION3 0x0003 2030 2047 2031 2048 typedef struct _DEVICE_DESCRIPTION { 2032 2049 ULONG Version; ··· 2045 2062 DMA_SPEED DmaSpeed; 2046 2063 ULONG MaximumLength; 2047 2064 ULONG DmaPort; 2065 + #if (NTDDI_VERSION >= NTDDI_WIN8) 2066 + ULONG DmaAddressWidth; 2067 + ULONG DmaControllerInstance; 2068 + ULONG DmaRequestLine; 2069 + PHYSICAL_ADDRESS DeviceAddress; 2070 + #endif // NTDDI_WIN8 2048 2071 } DEVICE_DESCRIPTION, *PDEVICE_DESCRIPTION; 2049 2072 2073 + #define DMA_ADAPTER_INFO_VERSION1 1 2074 + 2075 + #define ADAPTER_INFO_SYNCHRONOUS_CALLBACK 0x0001 2076 + #define ADAPTER_INFO_API_BYPASS 0x0002 2077 + 2078 + typedef struct _DMA_ADAPTER_INFO_V1 2079 + { 2080 + ULONG ReadDmaCounterAvailable; 2081 + ULONG ScatterGatherLimit; 2082 + ULONG DmaAddressWidth; 2083 + ULONG Flags; 2084 + ULONG MinimumTransferUnit; 2085 + } DMA_ADAPTER_INFO_V1, *PDMA_ADAPTER_INFO_V1; 2086 + 2087 + typedef struct _DMA_ADAPTER_INFO 2088 + { 2089 + ULONG Version; 2090 + union 2091 + { 2092 + DMA_ADAPTER_INFO_V1 V1; 2093 + }; 2094 + } DMA_ADAPTER_INFO, *PDMA_ADAPTER_INFO; 2095 + 2096 + #define DMA_TRANSFER_INFO_VERSION1 1 2097 + #define DMA_TRANSFER_INFO_VERSION2 2 2098 + 2099 + typedef struct _DMA_TRANSFER_INFO_V1 2100 + { 2101 + ULONG MapRegisterCount; 2102 + ULONG ScatterGatherElementCount; 2103 + ULONG ScatterGatherListSize; 2104 + } DMA_TRANSFER_INFO_V1, *PDMA_TRANSFER_INFO_V1; 2105 + 2106 + typedef struct _DMA_TRANSFER_INFO_V2 2107 + { 2108 + ULONG MapRegisterCount; 2109 + ULONG ScatterGatherElementCount; 2110 + ULONG ScatterGatherListSize; 2111 + ULONG LogicalPageCount; 2112 + } DMA_TRANSFER_INFO_V2, *PDMA_TRANSFER_INFO_V2; 2113 + 2114 + typedef struct _DMA_TRANSFER_INFO 2115 + { 2116 + ULONG Version; 2117 + union { 2118 + DMA_TRANSFER_INFO_V1 V1; 2119 + DMA_TRANSFER_INFO_V2 V2; 2120 + }; 2121 + } DMA_TRANSFER_INFO, *PDMA_TRANSFER_INFO; 2122 + 2123 + #define DMA_TRANSFER_CONTEXT_VERSION1 1 2124 + 2125 + #ifdef _WIN64 2126 + #define DMA_TRANSFER_CONTEXT_SIZE_V1 128 2127 + #else 2128 + #define DMA_TRANSFER_CONTEXT_SIZE_V1 64 2129 + #endif 2130 + 2050 2131 typedef enum _DEVICE_RELATION_TYPE { 2051 2132 BusRelations, 2052 2133 EjectionRelations, ··· 2194 2275 struct _DMA_OPERATIONS* DmaOperations; 2195 2276 } DMA_ADAPTER, *PDMA_ADAPTER; 2196 2277 2278 + typedef enum 2279 + { 2280 + DmaComplete, 2281 + DmaAborted, 2282 + DmaError, 2283 + DmaCancelled 2284 + } DMA_COMPLETION_STATUS; 2285 + 2197 2286 typedef VOID 2198 2287 (NTAPI *PPUT_DMA_ADAPTER)( 2199 2288 PDMA_ADAPTER DmaAdapter); ··· 2313 2402 _In_ PMDL OriginalMdl, 2314 2403 _Out_ PMDL *TargetMdl); 2315 2404 2405 + typedef NTSTATUS 2406 + (NTAPI *PGET_DMA_ADAPTER_INFO)( 2407 + _In_ PDMA_ADAPTER DmaAdapter, 2408 + _Inout_ PDMA_ADAPTER_INFO AdapterInfo); 2409 + 2410 + typedef NTSTATUS 2411 + (NTAPI *PGET_DMA_TRANSFER_INFO)( 2412 + _In_ PDMA_ADAPTER DmaAdapter, 2413 + _In_ PMDL Mdl, 2414 + _In_ ULONGLONG Offset, 2415 + _In_ ULONG Length, 2416 + _In_ BOOLEAN WriteOnly, 2417 + _Inout_ PDMA_TRANSFER_INFO TransferInfo); 2418 + 2419 + typedef NTSTATUS 2420 + (NTAPI *PINITIALIZE_DMA_TRANSFER_CONTEXT)( 2421 + _In_ PDMA_ADAPTER DmaAdapter, 2422 + _Out_ PVOID DmaTransferContext); 2423 + 2424 + typedef PVOID 2425 + (NTAPI *PALLOCATE_COMMON_BUFFER_EX)( 2426 + _In_ PDMA_ADAPTER DmaAdapter, 2427 + _In_opt_ PPHYSICAL_ADDRESS MaximumAddress, 2428 + _In_ ULONG Length, 2429 + _Out_ PPHYSICAL_ADDRESS LogicalAddress, 2430 + _In_ BOOLEAN CacheEnabled, 2431 + _In_ NODE_REQUIREMENT PreferredNode); 2432 + 2433 + typedef NTSTATUS 2434 + (NTAPI *PALLOCATE_ADAPTER_CHANNEL_EX)( 2435 + _In_ PDMA_ADAPTER DmaAdapter, 2436 + _In_ PDEVICE_OBJECT DeviceObject, 2437 + _In_ PVOID DmaTransferContext, 2438 + _In_ ULONG NumberOfMapRegisters, 2439 + _In_ ULONG Flags, 2440 + _In_opt_ PDRIVER_CONTROL ExecutionRoutine, 2441 + _In_opt_ PVOID ExecutionContext, 2442 + _Out_opt_ PVOID *MapRegisterBase); 2443 + 2444 + typedef NTSTATUS 2445 + (NTAPI *PCONFIGURE_ADAPTER_CHANNEL)( 2446 + _In_ PDMA_ADAPTER DmaAdapter, 2447 + _In_ ULONG FunctionNumber, 2448 + _In_ PVOID Context); 2449 + 2450 + typedef BOOLEAN 2451 + (NTAPI *PCANCEL_ADAPTER_CHANNEL)( 2452 + _In_ PDMA_ADAPTER DmaAdapter, 2453 + _In_ PDEVICE_OBJECT DeviceObject, 2454 + _In_ PVOID DmaTransferContext); 2455 + 2456 + typedef 2457 + _Function_class_(DMA_COMPLETION_ROUTINE) 2458 + _IRQL_requires_max_(DISPATCH_LEVEL) 2459 + _IRQL_requires_min_(DISPATCH_LEVEL) 2460 + VOID 2461 + NTAPI 2462 + DMA_COMPLETION_ROUTINE( 2463 + _In_ PDMA_ADAPTER DmaAdapter, 2464 + _In_ PDEVICE_OBJECT DeviceObject, 2465 + _In_ PVOID CompletionContext, 2466 + _In_ DMA_COMPLETION_STATUS Status); 2467 + 2468 + typedef DMA_COMPLETION_ROUTINE *PDMA_COMPLETION_ROUTINE; 2469 + 2470 + typedef NTSTATUS 2471 + (NTAPI *PMAP_TRANSFER_EX)( 2472 + _In_ PDMA_ADAPTER DmaAdapter, 2473 + _In_ PMDL Mdl, 2474 + _In_ PVOID MapRegisterBase, 2475 + _In_ ULONGLONG Offset, 2476 + _In_ ULONG DeviceOffset, 2477 + _Inout_ PULONG Length, 2478 + _In_ BOOLEAN WriteToDevice, 2479 + _Out_writes_bytes_opt_(ScatterGatherBufferLength) PSCATTER_GATHER_LIST ScatterGatherBuffer, 2480 + _In_ ULONG ScatterGatherBufferLength, 2481 + _In_opt_ PDMA_COMPLETION_ROUTINE DmaCompletionRoutine, 2482 + _In_opt_ PVOID CompletionContext); 2483 + 2484 + typedef NTSTATUS 2485 + (NTAPI *PGET_SCATTER_GATHER_LIST_EX)( 2486 + _In_ PDMA_ADAPTER DmaAdapter, 2487 + _In_ PDEVICE_OBJECT DeviceObject, 2488 + _In_ PVOID DmaTransferContext, 2489 + _In_ PMDL Mdl, 2490 + _In_ ULONGLONG Offset, 2491 + _In_ ULONG Length, 2492 + _In_ ULONG Flags, 2493 + _In_opt_ PDRIVER_LIST_CONTROL ExecutionRoutine, 2494 + _In_opt_ PVOID Context, 2495 + _In_ BOOLEAN WriteToDevice, 2496 + _In_opt_ PDMA_COMPLETION_ROUTINE DmaCompletionRoutine, 2497 + _In_opt_ PVOID CompletionContext, 2498 + _Out_opt_ PSCATTER_GATHER_LIST *ScatterGatherList); 2499 + 2500 + typedef NTSTATUS 2501 + (NTAPI *PBUILD_SCATTER_GATHER_LIST_EX)( 2502 + _In_ PDMA_ADAPTER DmaAdapter, 2503 + _In_ PDEVICE_OBJECT DeviceObject, 2504 + _In_ PVOID DmaTransferContext, 2505 + _In_ PMDL Mdl, 2506 + _In_ ULONGLONG Offset, 2507 + _In_ ULONG Length, 2508 + _In_ ULONG Flags, 2509 + _In_opt_ PDRIVER_LIST_CONTROL ExecutionRoutine, 2510 + _In_opt_ PVOID Context, 2511 + _In_ BOOLEAN WriteToDevice, 2512 + _In_ PVOID ScatterGatherBuffer, 2513 + _In_ ULONG ScatterGatherLength, 2514 + _In_opt_ PDMA_COMPLETION_ROUTINE DmaCompletionRoutine, 2515 + _In_opt_ PVOID CompletionContext, 2516 + _Out_opt_ PVOID ScatterGatherList); 2517 + 2518 + typedef NTSTATUS 2519 + (NTAPI *PFLUSH_ADAPTER_BUFFERS_EX)( 2520 + _In_ PDMA_ADAPTER DmaAdapter, 2521 + _In_ PMDL Mdl, 2522 + _In_ PVOID MapRegisterBase, 2523 + _In_ ULONGLONG Offset, 2524 + _In_ ULONG Length, 2525 + _In_ BOOLEAN WriteToDevice); 2526 + 2527 + typedef VOID 2528 + (NTAPI *PFREE_ADAPTER_OBJECT)( 2529 + _In_ PDMA_ADAPTER DmaAdapter, 2530 + _In_ IO_ALLOCATION_ACTION AllocationAction); 2531 + 2532 + typedef NTSTATUS 2533 + (NTAPI *PCANCEL_MAPPED_TRANSFER)( 2534 + _In_ PDMA_ADAPTER DmaAdapter, 2535 + _In_ PVOID DmaTransferContext); 2536 + 2537 + typedef NTSTATUS 2538 + (NTAPI *PALLOCATE_DOMAIN_COMMON_BUFFER)( 2539 + _In_ PDMA_ADAPTER DmaAdapter, 2540 + _In_ HANDLE DomainHandle, 2541 + _In_opt_ PPHYSICAL_ADDRESS MaximumAddress, 2542 + _In_ ULONG Length, 2543 + _In_ ULONG Flags, 2544 + _In_opt_ MEMORY_CACHING_TYPE *CacheType, 2545 + _In_ NODE_REQUIREMENT PreferredNode, 2546 + _Out_ PPHYSICAL_ADDRESS LogicalAddress, 2547 + _Out_ PVOID *VirtualAddress); 2548 + 2549 + typedef NTSTATUS 2550 + (NTAPI *PFLUSH_DMA_BUFFER)( 2551 + _In_ PDMA_ADAPTER DmaAdapter, 2552 + _In_ PMDL Mdl, 2553 + _In_ BOOLEAN ReadOperation); 2554 + 2555 + typedef NTSTATUS 2556 + (NTAPI *PJOIN_DMA_DOMAIN)( 2557 + _In_ PDMA_ADAPTER DmaAdapter, 2558 + _In_ HANDLE DomainHandle); 2559 + 2560 + typedef NTSTATUS 2561 + (NTAPI *PLEAVE_DMA_DOMAIN)( 2562 + _In_ PDMA_ADAPTER DmaAdapter); 2563 + 2564 + typedef HANDLE 2565 + (NTAPI *PGET_DMA_DOMAIN)( 2566 + _In_ PDMA_ADAPTER DmaAdapter); 2567 + 2568 + typedef PVOID 2569 + (NTAPI *PALLOCATE_COMMON_BUFFER_WITH_BOUNDS)( 2570 + _In_ PDMA_ADAPTER DmaAdapter, 2571 + _In_opt_ PPHYSICAL_ADDRESS MinimumAddress, 2572 + _In_opt_ PPHYSICAL_ADDRESS MaximumAddress, 2573 + _In_ ULONG Length, 2574 + _In_ ULONG Flags, 2575 + _In_opt_ MEMORY_CACHING_TYPE *CacheType, 2576 + _In_ NODE_REQUIREMENT PreferredNode, 2577 + _Out_ PPHYSICAL_ADDRESS LogicalAddress); 2578 + 2579 + typedef struct _DMA_COMMON_BUFFER_VECTOR DMA_COMMON_BUFFER_VECTOR, *PDMA_COMMON_BUFFER_VECTOR; 2580 + 2581 + typedef NTSTATUS 2582 + (NTAPI *PALLOCATE_COMMON_BUFFER_VECTOR)( 2583 + _In_ PDMA_ADAPTER DmaAdapter, 2584 + _In_ PHYSICAL_ADDRESS LowAddress, 2585 + _In_ PHYSICAL_ADDRESS HighAddress, 2586 + _In_ MEMORY_CACHING_TYPE CacheType, 2587 + _In_ ULONG IdealNode, 2588 + _In_ ULONG Flags, 2589 + _In_ ULONG NumberOfElements, 2590 + _In_ ULONGLONG SizeOfElements, 2591 + _Out_ PDMA_COMMON_BUFFER_VECTOR *VectorOut); 2592 + 2593 + typedef VOID 2594 + (NTAPI *PGET_COMMON_BUFFER_FROM_VECTOR_BY_INDEX)( 2595 + _In_ PDMA_ADAPTER DmaAdapter, 2596 + _In_ PDMA_COMMON_BUFFER_VECTOR Vector, 2597 + _In_ ULONG Index, 2598 + _Out_ PVOID *VirtualAddressOut, 2599 + _Out_ PPHYSICAL_ADDRESS LogicalAddressOut); 2600 + 2601 + typedef VOID 2602 + (NTAPI *PFREE_COMMON_BUFFER_FROM_VECTOR)( 2603 + _In_ PDMA_ADAPTER DmaAdapter, 2604 + _In_ PDMA_COMMON_BUFFER_VECTOR Vector, 2605 + _In_ ULONG Index); 2606 + 2607 + typedef VOID 2608 + (NTAPI *PFREE_COMMON_BUFFER_VECTOR)( 2609 + _In_ PDMA_ADAPTER DmaAdapter, 2610 + _In_ PDMA_COMMON_BUFFER_VECTOR Vector); 2611 + 2316 2612 typedef struct _DMA_OPERATIONS { 2317 2613 ULONG Size; 2318 2614 PPUT_DMA_ADAPTER PutDmaAdapter; ··· 2330 2626 PCALCULATE_SCATTER_GATHER_LIST_SIZE CalculateScatterGatherList; 2331 2627 PBUILD_SCATTER_GATHER_LIST BuildScatterGatherList; 2332 2628 PBUILD_MDL_FROM_SCATTER_GATHER_LIST BuildMdlFromScatterGatherList; 2629 + PGET_DMA_ADAPTER_INFO GetDmaAdapterInfo; 2630 + PGET_DMA_TRANSFER_INFO GetDmaTransferInfo; 2631 + PINITIALIZE_DMA_TRANSFER_CONTEXT InitializeDmaTransferContext; 2632 + PALLOCATE_COMMON_BUFFER_EX AllocateCommonBufferEx; 2633 + PALLOCATE_ADAPTER_CHANNEL_EX AllocateAdapterChannelEx; 2634 + PCONFIGURE_ADAPTER_CHANNEL ConfigureAdapterChannel; 2635 + PCANCEL_ADAPTER_CHANNEL CancelAdapterChannel; 2636 + PMAP_TRANSFER_EX MapTransferEx; 2637 + PGET_SCATTER_GATHER_LIST_EX GetScatterGatherListEx; 2638 + PBUILD_SCATTER_GATHER_LIST_EX BuildScatterGatherListEx; 2639 + PFLUSH_ADAPTER_BUFFERS_EX FlushAdapterBuffersEx; 2640 + PFREE_ADAPTER_OBJECT FreeAdapterObject; 2641 + PCANCEL_MAPPED_TRANSFER CancelMappedTransfer; 2642 + PALLOCATE_DOMAIN_COMMON_BUFFER AllocateDomainCommonBuffer; 2643 + PFLUSH_DMA_BUFFER FlushDmaBuffer; 2644 + PJOIN_DMA_DOMAIN JoinDmaDomain; 2645 + PLEAVE_DMA_DOMAIN LeaveDmaDomain; 2646 + PGET_DMA_DOMAIN GetDmaDomain; 2647 + PALLOCATE_COMMON_BUFFER_WITH_BOUNDS AllocateCommonBufferWithBounds; 2648 + PALLOCATE_COMMON_BUFFER_VECTOR AllocateCommonBufferVector; 2649 + PGET_COMMON_BUFFER_FROM_VECTOR_BY_INDEX GetCommonBufferFromVectorByIndex; 2650 + PFREE_COMMON_BUFFER_FROM_VECTOR FreeCommonBufferFromVector; 2651 + PFREE_COMMON_BUFFER_VECTOR FreeCommonBufferVector; 2333 2652 } DMA_OPERATIONS, *PDMA_OPERATIONS; 2334 2653 2335 2654 typedef struct _IO_RESOURCE_DESCRIPTOR { ··· 2355 2674 struct { 2356 2675 ULONG MinimumVector; 2357 2676 ULONG MaximumVector; 2677 + #if defined(NT_PROCESSOR_GROUPS) 2678 + IRQ_DEVICE_POLICY AffinityPolicy; 2679 + USHORT Group; 2680 + #else 2681 + IRQ_DEVICE_POLICY AffinityPolicy; 2682 + #endif 2683 + IRQ_PRIORITY PriorityPolicy; 2684 + KAFFINITY TargetedProcessors; 2358 2685 } Interrupt; 2359 2686 struct { 2360 2687 ULONG MinimumChannel; ··· 2589 2916 BusQueryHardwareIDs, 2590 2917 BusQueryCompatibleIDs, 2591 2918 BusQueryInstanceID, 2592 - BusQueryDeviceSerialNumber 2919 + BusQueryDeviceSerialNumber, 2920 + BusQueryContainerID 2593 2921 } BUS_QUERY_ID_TYPE, *PBUS_QUERY_ID_TYPE; 2594 2922 2595 2923 typedef enum _DEVICE_TEXT_TYPE { ··· 7110 7438 } IO_PRIORITY_INFO, *PIO_PRIORITY_INFO; 7111 7439 #endif 7112 7440 $endif (_NTIFS_) 7441 + 7442 + $if (_WDMDDK_) 7443 + 7444 + #define D3COLD_SUPPORT_INTERFACE_VERSION 1 7445 + 7446 + typedef 7447 + _Function_class_(SET_D3COLD_SUPPORT) 7448 + _IRQL_requires_(PASSIVE_LEVEL) 7449 + VOID 7450 + SET_D3COLD_SUPPORT( 7451 + _In_reads_opt_(_Inexpressible_("varies")) PVOID Context, 7452 + _In_ BOOLEAN D3ColdSupport); 7453 + 7454 + typedef SET_D3COLD_SUPPORT *PSET_D3COLD_SUPPORT; 7455 + 7456 + typedef enum _DEVICE_WAKE_DEPTH 7457 + { 7458 + DeviceWakeDepthNotWakeable = 0, 7459 + DeviceWakeDepthD0, 7460 + DeviceWakeDepthD1, 7461 + DeviceWakeDepthD2, 7462 + DeviceWakeDepthD3hot, 7463 + DeviceWakeDepthD3cold, 7464 + DeviceWakeDepthMaximum 7465 + } DEVICE_WAKE_DEPTH, *PDEVICE_WAKE_DEPTH; 7466 + 7467 + FORCEINLINE 7468 + DEVICE_POWER_STATE 7469 + MapWakeDepthToDstate( 7470 + _In_ DEVICE_WAKE_DEPTH WakeDepth) 7471 + { 7472 + const DEVICE_POWER_STATE dstateMap[DeviceWakeDepthMaximum] = 7473 + { 7474 + PowerDeviceD0, 7475 + PowerDeviceD0, 7476 + PowerDeviceD1, 7477 + PowerDeviceD2, 7478 + PowerDeviceD3, 7479 + PowerDeviceD3 7480 + }; 7481 + 7482 + if (WakeDepth < 0 || WakeDepth >= DeviceWakeDepthMaximum) 7483 + { 7484 + return PowerDeviceUnspecified; 7485 + } 7486 + else 7487 + { 7488 + return dstateMap[WakeDepth]; 7489 + } 7490 + } 7491 + 7492 + typedef 7493 + _Function_class_(GET_IDLE_WAKE_INFO) 7494 + _IRQL_requires_(PASSIVE_LEVEL) 7495 + NTSTATUS 7496 + GET_IDLE_WAKE_INFO( 7497 + _In_reads_opt_(_Inexpressible_("varies")) PVOID Context, 7498 + _In_ SYSTEM_POWER_STATE SystemPowerState, 7499 + _Out_ PDEVICE_WAKE_DEPTH DeepestWakeableDstate); 7500 + 7501 + typedef GET_IDLE_WAKE_INFO *PGET_IDLE_WAKE_INFO; 7502 + 7503 + typedef 7504 + _Function_class_(GET_D3COLD_CAPABILITY) 7505 + _IRQL_requires_(PASSIVE_LEVEL) 7506 + NTSTATUS 7507 + GET_D3COLD_CAPABILITY( 7508 + _In_reads_opt_(_Inexpressible_("varies")) PVOID Context, 7509 + _Out_ PBOOLEAN D3ColdSupported); 7510 + 7511 + typedef GET_D3COLD_CAPABILITY *PGET_D3COLD_CAPABILITY; 7512 + 7513 + typedef enum _D3COLD_LAST_TRANSITION_STATUS 7514 + { 7515 + LastDStateTransitionStatusUnknown = 0, 7516 + LastDStateTransitionD3hot, 7517 + LastDStateTransitionD3cold 7518 + } D3COLD_LAST_TRANSITION_STATUS, *PD3COLD_LAST_TRANSITION_STATUS; 7519 + 7520 + typedef 7521 + _Function_class_(GET_D3COLD_LAST_TRANSITION_STATUS) 7522 + _IRQL_requires_max_(DISPATCH_LEVEL) 7523 + VOID 7524 + GET_D3COLD_LAST_TRANSITION_STATUS( 7525 + _In_reads_opt_(_Inexpressible_("varies")) PVOID Context, 7526 + _Out_ PD3COLD_LAST_TRANSITION_STATUS LastTransitionStatus); 7527 + 7528 + typedef GET_D3COLD_LAST_TRANSITION_STATUS *PGET_D3COLD_LAST_TRANSITION_STATUS; 7529 + 7530 + typedef struct _D3COLD_SUPPORT_INTERFACE 7531 + { 7532 + USHORT Size; 7533 + USHORT Version; 7534 + PVOID Context; 7535 + PINTERFACE_REFERENCE InterfaceReference; 7536 + PINTERFACE_DEREFERENCE InterfaceDereference; 7537 + PSET_D3COLD_SUPPORT SetD3ColdSupport; 7538 + PGET_IDLE_WAKE_INFO GetIdleWakeInfo; 7539 + PGET_D3COLD_CAPABILITY GetD3ColdCapability; 7540 + PGET_D3COLD_CAPABILITY GetBusDriverD3ColdSupport; 7541 + PGET_D3COLD_LAST_TRANSITION_STATUS GetLastTransitionStatus; 7542 + } D3COLD_SUPPORT_INTERFACE, *PD3COLD_SUPPORT_INTERFACE; 7543 + 7544 + typedef 7545 + _Function_class_(D3COLD_REQUEST_CORE_POWER_RAIL) 7546 + _IRQL_requires_(PASSIVE_LEVEL) 7547 + VOID 7548 + D3COLD_REQUEST_CORE_POWER_RAIL( 7549 + _In_reads_opt_(_Inexpressible_("varies")) PVOID Context, 7550 + _In_ BOOLEAN CorePowerRailNeeded); 7551 + 7552 + typedef D3COLD_REQUEST_CORE_POWER_RAIL *PD3COLD_REQUEST_CORE_POWER_RAIL; 7553 + 7554 + typedef 7555 + _Function_class_(D3COLD_REQUEST_AUX_POWER) 7556 + _IRQL_requires_(PASSIVE_LEVEL) 7557 + NTSTATUS 7558 + D3COLD_REQUEST_AUX_POWER( 7559 + _In_reads_opt_(_Inexpressible_("varies")) PVOID Context, 7560 + _In_ ULONG AuxPowerInMilliWatts, 7561 + _Out_ PULONG RetryInSeconds); 7562 + 7563 + typedef D3COLD_REQUEST_AUX_POWER *PD3COLD_REQUEST_AUX_POWER; 7564 + 7565 + typedef 7566 + _Function_class_(D3COLD_REQUEST_PERST_DELAY) 7567 + _IRQL_requires_(PASSIVE_LEVEL) 7568 + NTSTATUS 7569 + D3COLD_REQUEST_PERST_DELAY( 7570 + _In_reads_opt_(_Inexpressible_("varies")) PVOID Context, 7571 + _In_ ULONG DelayInMicroSeconds); 7572 + 7573 + typedef D3COLD_REQUEST_PERST_DELAY *PD3COLD_REQUEST_PERST_DELAY; 7574 + 7575 + typedef struct _D3COLD_AUX_POWER_AND_TIMING_INTERFACE 7576 + { 7577 + USHORT Size; 7578 + USHORT Version; 7579 + PVOID Context; 7580 + PINTERFACE_REFERENCE InterfaceReference; 7581 + PINTERFACE_DEREFERENCE InterfaceDereference; 7582 + PD3COLD_REQUEST_CORE_POWER_RAIL RequestCorePowerRail; 7583 + PD3COLD_REQUEST_AUX_POWER RequestAuxPower; 7584 + PD3COLD_REQUEST_PERST_DELAY RequestPerstDelay; 7585 + } D3COLD_AUX_POWER_AND_TIMING_INTERFACE, *PD3COLD_AUX_POWER_AND_TIMING_INTERFACE; 7586 + $endif(_WDMDDK_)
+6
sdk/include/xdk/ketypes.h
··· 871 871 PagedPoolCacheAligned, 872 872 NonPagedPoolCacheAlignedMustS, 873 873 MaxPoolType, 874 + 875 + NonPagedPoolBase = 0, 876 + NonPagedPoolBaseMustSucceed = NonPagedPoolBase + 2, 877 + NonPagedPoolBaseCacheAligned = NonPagedPoolBase + 4, 878 + NonPagedPoolBaseCacheAlignedMustS = NonPagedPoolBase + 6, 879 + 874 880 NonPagedPoolSession = 32, 875 881 PagedPoolSession, 876 882 NonPagedPoolMustSucceedSession,
+3 -4
sdk/include/xdk/mmfuncs.h
··· 321 321 NTAPI 322 322 MmMapLockedPagesSpecifyCache( 323 323 _Inout_ PMDL MemoryDescriptorList, 324 - _In_ __drv_strictType(KPROCESSOR_MODE/enum _MODE,__drv_typeConst) 325 - KPROCESSOR_MODE AccessMode, 324 + _In_ __drv_strictType(KPROCESSOR_MODE/enum _MODE,__drv_typeConst) KPROCESSOR_MODE AccessMode, 326 325 _In_ __drv_strictTypeMatch(__drv_typeCond) MEMORY_CACHING_TYPE CacheType, 327 - _In_opt_ PVOID BaseAddress, 326 + _In_opt_ PVOID RequestedAddress, 328 327 _In_ ULONG BugCheckOnFailure, 329 - _In_ MM_PAGE_PRIORITY Priority); 328 + _In_ ULONG Priority); 330 329 331 330 _IRQL_requires_max_(APC_LEVEL) 332 331 NTKERNELAPI
+274 -2
sdk/include/xdk/potypes.h
··· 56 56 SetPowerSettingValue, 57 57 NotifyUserPowerSetting, 58 58 PowerInformationLevelUnused0, 59 - PowerInformationLevelUnused1, 59 + SystemMonitorHiberBootPowerOff, 60 60 SystemVideoState, 61 61 TraceApplicationPowerMessage, 62 62 TraceApplicationPowerMessageEnd, ··· 80 80 ProcessorIdleDomains, 81 81 WakeTimerList, 82 82 SystemHiberFileSize, 83 + ProcessorIdleStatesHv, 84 + ProcessorPerfStatesHv, 85 + ProcessorPerfCapHv, 86 + ProcessorSetIdle, 87 + LogicalProcessorIdling, 88 + UserPresence, 89 + PowerSettingNotificationName, 90 + GetPowerSettingValue, 91 + IdleResiliency, 92 + SessionRITState, 93 + SessionConnectNotification, 94 + SessionPowerCleanup, 95 + SessionLockState, 96 + SystemHiberbootState, 97 + PlatformInformation, 98 + PdcInvocation, 99 + MonitorInvocation, 100 + FirmwareTableInformationRegistered, 101 + SetShutdownSelectedTime, 102 + SuspendResumeInvocation, 103 + PlmPowerRequestCreate, 104 + ScreenOff, 105 + CsDeviceNotification, 106 + PlatformRole, 107 + LastResumePerformance, 108 + DisplayBurst, 109 + ExitLatencySamplingPercentage, 110 + RegisterSpmPowerSettings, 111 + PlatformIdleStates, 112 + ProcessorIdleVeto, // deprecated 113 + PlatformIdleVeto, // deprecated 114 + SystemBatteryStatePrecise, 115 + ThermalEvent, 116 + PowerRequestActionInternal, 117 + BatteryDeviceState, 118 + PowerInformationInternal, 119 + ThermalStandby, 120 + SystemHiberFileType, 121 + PhysicalPowerButtonPress, 122 + QueryPotentialDripsConstraint, 123 + EnergyTrackerCreate, 124 + EnergyTrackerQuery, 125 + UpdateBlackBoxRecorder, 126 + SessionAllowExternalDmaDevices, 83 127 PowerInformationLevelMaximum 84 128 } POWER_INFORMATION_LEVEL; 85 129 ··· 254 298 PlatformRoleSOHOServer, 255 299 PlatformRoleAppliancePC, 256 300 PlatformRolePerformanceServer, 301 + PlatformRoleSlate, 257 302 PlatformRoleMaximum 258 303 } POWER_PLATFORM_ROLE; 259 304 305 + #define POWER_PLATFORM_ROLE_V1 (0x00000001) 306 + #define POWER_PLATFORM_ROLE_V1_MAX (PlatformRolePerformanceServer + 1) 307 + 308 + #define POWER_PLATFORM_ROLE_V2 (0x00000002) 309 + #define POWER_PLATFORM_ROLE_V2_MAX (PlatformRoleSlate + 1) 310 + 311 + #if (NTDDI_VERSION >= NTDDI_WIN8) 312 + #define POWER_PLATFORM_ROLE_VERSION POWER_PLATFORM_ROLE_V2 313 + #define POWER_PLATFORM_ROLE_VERSION_MAX POWER_PLATFORM_ROLE_V2_MAX 314 + #else 315 + #define POWER_PLATFORM_ROLE_VERSION POWER_PLATFORM_ROLE_V1 316 + #define POWER_PLATFORM_ROLE_VERSION_MAX POWER_PLATFORM_ROLE_V1_MAX 317 + #endif 318 + 319 + typedef struct _POWER_PLATFORM_INFORMATION 320 + { 321 + BOOLEAN AoAc; 322 + } POWER_PLATFORM_INFORMATION, *PPOWER_PLATFORM_INFORMATION; 323 + 260 324 #if (NTDDI_VERSION >= NTDDI_WINXP) || !defined(_BATCLASS_) 261 325 typedef struct { 262 326 ULONG Granularity; ··· 413 477 _In_ ULONG ValueLength, 414 478 _Inout_opt_ PVOID Context); 415 479 typedef POWER_SETTING_CALLBACK *PPOWER_SETTING_CALLBACK; 480 + 481 + #if (NTDDI_VERSION >= NTDDI_WIN8) 482 + 483 + #define PO_FX_VERSION_V1 0x00000001 484 + #define PO_FX_VERSION_V2 0x00000002 485 + #define PO_FX_VERSION_V3 0x00000003 486 + #define PO_FX_VERSION PO_FX_VERSION_V1 487 + 488 + DECLARE_HANDLE(POHANDLE); 489 + 490 + typedef 491 + _Function_class_(PO_FX_COMPONENT_ACTIVE_CONDITION_CALLBACK) 492 + _IRQL_requires_max_(DISPATCH_LEVEL) 493 + VOID 494 + PO_FX_COMPONENT_ACTIVE_CONDITION_CALLBACK( 495 + _In_ PVOID Context, 496 + _In_ ULONG Component); 497 + 498 + typedef PO_FX_COMPONENT_ACTIVE_CONDITION_CALLBACK *PPO_FX_COMPONENT_ACTIVE_CONDITION_CALLBACK; 499 + 500 + typedef 501 + _Function_class_(PO_FX_COMPONENT_IDLE_CONDITION_CALLBACK) 502 + _IRQL_requires_max_(DISPATCH_LEVEL) 503 + VOID 504 + PO_FX_COMPONENT_IDLE_CONDITION_CALLBACK( 505 + _In_ PVOID Context, 506 + _In_ ULONG Component); 507 + 508 + typedef PO_FX_COMPONENT_IDLE_CONDITION_CALLBACK *PPO_FX_COMPONENT_IDLE_CONDITION_CALLBACK; 509 + 510 + typedef 511 + _Function_class_(PO_FX_COMPONENT_IDLE_STATE_CALLBACK) 512 + _IRQL_requires_max_(DISPATCH_LEVEL) 513 + VOID 514 + PO_FX_COMPONENT_IDLE_STATE_CALLBACK( 515 + _In_ PVOID Context, 516 + _In_ ULONG Component, 517 + _In_ ULONG State); 518 + 519 + typedef PO_FX_COMPONENT_IDLE_STATE_CALLBACK *PPO_FX_COMPONENT_IDLE_STATE_CALLBACK; 520 + 521 + typedef 522 + _Function_class_(PO_FX_DEVICE_POWER_REQUIRED_CALLBACK) 523 + _IRQL_requires_max_(DISPATCH_LEVEL) 524 + VOID 525 + PO_FX_DEVICE_POWER_REQUIRED_CALLBACK( 526 + _In_ PVOID Context); 527 + 528 + typedef PO_FX_DEVICE_POWER_REQUIRED_CALLBACK *PPO_FX_DEVICE_POWER_REQUIRED_CALLBACK; 529 + 530 + typedef 531 + _Function_class_(PO_FX_DEVICE_POWER_NOT_REQUIRED_CALLBACK) 532 + _IRQL_requires_max_(DISPATCH_LEVEL) 533 + VOID 534 + PO_FX_DEVICE_POWER_NOT_REQUIRED_CALLBACK( 535 + _In_ PVOID Context); 536 + 537 + typedef PO_FX_DEVICE_POWER_NOT_REQUIRED_CALLBACK *PPO_FX_DEVICE_POWER_NOT_REQUIRED_CALLBACK; 538 + 539 + typedef 540 + _Function_class_(PO_FX_POWER_CONTROL_CALLBACK) 541 + _IRQL_requires_max_(DISPATCH_LEVEL) 542 + NTSTATUS 543 + PO_FX_POWER_CONTROL_CALLBACK( 544 + _In_ PVOID DeviceContext, 545 + _In_ LPCGUID PowerControlCode, 546 + _In_reads_bytes_opt_(InBufferSize) PVOID InBuffer, 547 + _In_ SIZE_T InBufferSize, 548 + _Out_writes_bytes_opt_(OutBufferSize) PVOID OutBuffer, 549 + _In_ SIZE_T OutBufferSize, 550 + _Out_opt_ PSIZE_T BytesReturned); 551 + 552 + typedef PO_FX_POWER_CONTROL_CALLBACK *PPO_FX_POWER_CONTROL_CALLBACK; 553 + 554 + typedef 555 + _Function_class_(PO_FX_COMPONENT_CRITICAL_TRANSITION_CALLBACK) 556 + _IRQL_requires_max_(HIGH_LEVEL) 557 + VOID 558 + PO_FX_COMPONENT_CRITICAL_TRANSITION_CALLBACK( 559 + _In_ PVOID Context, 560 + _In_ ULONG Component, 561 + _In_ BOOLEAN Active); 562 + 563 + typedef PO_FX_COMPONENT_CRITICAL_TRANSITION_CALLBACK *PPO_FX_COMPONENT_CRITICAL_TRANSITION_CALLBACK; 564 + 565 + typedef struct _PO_FX_COMPONENT_IDLE_STATE 566 + { 567 + ULONGLONG TransitionLatency; 568 + ULONGLONG ResidencyRequirement; 569 + ULONG NominalPower; 570 + } PO_FX_COMPONENT_IDLE_STATE, *PPO_FX_COMPONENT_IDLE_STATE; 571 + 572 + typedef struct _PO_FX_COMPONENT_V1 573 + { 574 + GUID Id; 575 + ULONG IdleStateCount; 576 + ULONG DeepestWakeableIdleState; 577 + _Field_size_full_(IdleStateCount) PPO_FX_COMPONENT_IDLE_STATE IdleStates; 578 + } PO_FX_COMPONENT_V1, *PPO_FX_COMPONENT_V1; 579 + 580 + typedef struct _PO_FX_DEVICE_V1 581 + { 582 + ULONG Version; 583 + ULONG ComponentCount; 584 + PPO_FX_COMPONENT_ACTIVE_CONDITION_CALLBACK ComponentActiveConditionCallback; 585 + PPO_FX_COMPONENT_IDLE_CONDITION_CALLBACK ComponentIdleConditionCallback; 586 + PPO_FX_COMPONENT_IDLE_STATE_CALLBACK ComponentIdleStateCallback; 587 + PPO_FX_DEVICE_POWER_REQUIRED_CALLBACK DevicePowerRequiredCallback; 588 + PPO_FX_DEVICE_POWER_NOT_REQUIRED_CALLBACK DevicePowerNotRequiredCallback; 589 + PPO_FX_POWER_CONTROL_CALLBACK PowerControlCallback; 590 + PVOID DeviceContext; 591 + _Field_size_full_(ComponentCount) PO_FX_COMPONENT_V1 Components[ANYSIZE_ARRAY]; 592 + } PO_FX_DEVICE_V1, *PPO_FX_DEVICE_V1; 593 + 594 + #define PO_FX_COMPONENT_FLAG_F0_ON_DX 0x0000000000000001 595 + #define PO_FX_COMPONENT_FLAG_NO_DEBOUNCE 0x0000000000000002 596 + 597 + typedef struct _PO_FX_COMPONENT_V2 598 + { 599 + GUID Id; 600 + ULONGLONG Flags; 601 + ULONG DeepestWakeableIdleState; 602 + ULONG IdleStateCount; 603 + _Field_size_full_(IdleStateCount) PPO_FX_COMPONENT_IDLE_STATE IdleStates; 604 + ULONG ProviderCount; 605 + _Field_size_full_(ProviderCount) PULONG Providers; 606 + } PO_FX_COMPONENT_V2, *PPO_FX_COMPONENT_V2; 607 + 608 + typedef struct _PO_FX_DEVICE_V2 609 + { 610 + ULONG Version; 611 + ULONGLONG Flags; 612 + PPO_FX_COMPONENT_ACTIVE_CONDITION_CALLBACK ComponentActiveConditionCallback; 613 + PPO_FX_COMPONENT_IDLE_CONDITION_CALLBACK ComponentIdleConditionCallback; 614 + PPO_FX_COMPONENT_IDLE_STATE_CALLBACK ComponentIdleStateCallback; 615 + PPO_FX_DEVICE_POWER_REQUIRED_CALLBACK DevicePowerRequiredCallback; 616 + PPO_FX_DEVICE_POWER_NOT_REQUIRED_CALLBACK DevicePowerNotRequiredCallback; 617 + PPO_FX_POWER_CONTROL_CALLBACK PowerControlCallback; 618 + PVOID DeviceContext; 619 + ULONG ComponentCount; 620 + _Field_size_full_(ComponentCount) PO_FX_COMPONENT_V2 Components[ANYSIZE_ARRAY]; 621 + } PO_FX_DEVICE_V2, *PPO_FX_DEVICE_V2; 622 + 623 + #define PO_FX_DEVICE_FLAG_RESERVED_1 (0x0000000000000001ull) 624 + #define PO_FX_DEVICE_FLAG_DFX_DIRECT_CHILDREN_OPTIONAL (0x0000000000000002ull) 625 + #define PO_FX_DEVICE_FLAG_DFX_POWER_CHILDREN_OPTIONAL (0x0000000000000004ull) 626 + #define PO_FX_DEVICE_FLAG_DFX_CHILDREN_OPTIONAL \ 627 + (PO_FX_DEVICE_FLAG_DFX_DIRECT_CHILDREN_OPTIONAL | \ 628 + PO_FX_DEVICE_FLAG_DFX_POWER_CHILDREN_OPTIONAL) 629 + 630 + #define PO_FX_DIRECTED_FX_DEFAULT_IDLE_TIMEOUT (0ul) 631 + #define PO_FX_DIRECTED_FX_IMMEDIATE_IDLE_TIMEOUT ((ULONG)-1) 632 + #define PO_FX_DIRECTED_FX_MAX_IDLE_TIMEOUT (10ul * 60) 633 + 634 + typedef 635 + _Function_class_(PO_FX_DIRECTED_POWER_UP_CALLBACK) 636 + _IRQL_requires_max_(DISPATCH_LEVEL) 637 + _IRQL_requires_same_ 638 + VOID 639 + PO_FX_DIRECTED_POWER_UP_CALLBACK( 640 + _In_ PVOID Context, 641 + _In_ ULONG Flags); 642 + 643 + typedef PO_FX_DIRECTED_POWER_UP_CALLBACK *PPO_FX_DIRECTED_POWER_UP_CALLBACK; 644 + 645 + typedef 646 + _Function_class_(PO_FX_DIRECTED_POWER_DOWN_CALLBACK) 647 + _IRQL_requires_max_(DISPATCH_LEVEL) 648 + _IRQL_requires_same_ 649 + VOID 650 + PO_FX_DIRECTED_POWER_DOWN_CALLBACK( 651 + _In_ PVOID Context, 652 + _In_ ULONG Flags); 653 + 654 + typedef PO_FX_DIRECTED_POWER_DOWN_CALLBACK *PPO_FX_DIRECTED_POWER_DOWN_CALLBACK; 655 + 656 + typedef struct _PO_FX_DEVICE_V3 657 + { 658 + ULONG Version; 659 + ULONGLONG Flags; 660 + PPO_FX_COMPONENT_ACTIVE_CONDITION_CALLBACK ComponentActiveConditionCallback; 661 + PPO_FX_COMPONENT_IDLE_CONDITION_CALLBACK ComponentIdleConditionCallback; 662 + PPO_FX_COMPONENT_IDLE_STATE_CALLBACK ComponentIdleStateCallback; 663 + PPO_FX_DEVICE_POWER_REQUIRED_CALLBACK DevicePowerRequiredCallback; 664 + PPO_FX_DEVICE_POWER_NOT_REQUIRED_CALLBACK DevicePowerNotRequiredCallback; 665 + PPO_FX_POWER_CONTROL_CALLBACK PowerControlCallback; 666 + PPO_FX_DIRECTED_POWER_UP_CALLBACK DirectedPowerUpCallback; 667 + PPO_FX_DIRECTED_POWER_DOWN_CALLBACK DirectedPowerDownCallback; 668 + ULONG DirectedFxTimeoutInSeconds; 669 + PVOID DeviceContext; 670 + ULONG ComponentCount; 671 + _Field_size_full_(ComponentCount) PO_FX_COMPONENT_V2 Components[ANYSIZE_ARRAY]; 672 + } PO_FX_DEVICE_V3, *PPO_FX_DEVICE_V3; 673 + 674 + #if (PO_FX_VERSION == PO_FX_VERSION_V1) 675 + typedef PO_FX_COMPONENT_V1 PO_FX_COMPONENT, *PPO_FX_COMPONENT; 676 + typedef PO_FX_DEVICE_V1 PO_FX_DEVICE, *PPO_FX_DEVICE; 677 + #elif (PO_FX_VERSION == PO_FX_VERSION_V2) 678 + typedef PO_FX_COMPONENT_V2 PO_FX_COMPONENT, *PPO_FX_COMPONENT; 679 + typedef PO_FX_DEVICE_V2 PO_FX_DEVICE, *PPO_FX_DEVICE; 680 + #elif (PO_FX_VERSION == PO_FX_VERSION_V3) 681 + typedef PO_FX_COMPONENT_V2 PO_FX_COMPONENT, *PPO_FX_COMPONENT; 682 + typedef PO_FX_DEVICE_V3 PO_FX_DEVICE, *PPO_FX_DEVICE; 683 + #else 684 + #error PO_FX_VERSION undefined! 685 + #endif 686 + 687 + #endif // NTDDI_WIN8 688 + 416 689 $endif (_WDMDDK_) 417 690 $if (_NTIFS_) 418 691 ··· 423 696 #define PO_CB_LID_SWITCH_STATE 4 424 697 #define PO_CB_PROCESSOR_POWER_POLICY 5 425 698 $endif (_NTIFS_) 426 -