more building

.claude/settings.local.json

···
       "Bash(cargo tree:*)",
       "Bash(grep:*)",
       "Bash(1)",
-      "Bash(cargo clippy:*)"
+      "Bash(cargo clippy:*)",
+      "Bash(powershell -Command \"(Get-Content heartwood/src/attunement/idt.rs) -replace ''unsafe extern \"\"C\"\" fn'', ''extern \"\"C\"\" fn'' | Set-Content heartwood/src/attunement/idt.rs\")",
+      "Bash(powershell -Command \"\n$content = Get-Content idt.rs -Raw\n# Replace asm! with naked_asm! inside naked functions, but keep regular asm! elsewhere\n$content = $content -replace ''(?s)(#\\[unsafe\\(naked\\)\\].*?extern \"\"C\"\" fn.*?\\{.*?unsafe \\{)\\s*asm!'', ''$1 core::arch::naked_asm!''\nSet-Content idt.rs $content\n\")",
+      "Bash(powershell -Command \"(Get-Content idt_handlers.rs) -replace ''println!'', ''crate::println!'' | Set-Content idt_handlers.rs\")",
+      "Bash(powershell -Command \"(Get-Content idt_handlers.rs) -replace ''\\!'', ''!'' | Set-Content idt_handlers.rs\")",
+      "Bash(powershell -Command \"$content = (Get-Content idt_handlers.rs -Raw); $content = $content -replace ''\\\\!'', ''!''; Set-Content idt_handlers.rs $content\")"
     ],
     "deny": [],
     "ask": []

aethelos-source/heartwood/src/attunement/gdt.rs

···
+//! # Global Descriptor Table
+//!
+//! The GDT defines the privilege boundaries of AethelOS.
+//! Unlike traditional systems that enforce rigid hierarchies,
+//! our rings exist in symbiosis - Ring 0 (kernel) and Ring 3 (user)
+//! dance together in mutual respect.
+//!
+//! ## Philosophy
+//! Privilege is not dominion, but responsibility.
+//! The kernel serves userspace as much as userspace relies on the kernel.
+
+use core::arch::asm;
+use core::mem::size_of;
+
+/// GDT Entry - A segment descriptor
+#[derive(Debug, Clone, Copy)]
+#[repr(C, packed)]
+pub struct GdtEntry {
+    limit_low: u16,
+    base_low: u16,
+    base_middle: u8,
+    access: u8,
+    granularity: u8,
+    base_high: u8,
+}
+
+impl GdtEntry {
+    /// Create a null descriptor
+    pub const fn null() -> Self {
+        GdtEntry {
+            limit_low: 0,
+            base_low: 0,
+            base_middle: 0,
+            access: 0,
+            granularity: 0,
+            base_high: 0,
+        }
+    }
+
+    /// Create a kernel code segment (Ring 0, executable, readable)
+    pub const fn kernel_code() -> Self {
+        GdtEntry {
+            limit_low: 0xFFFF,
+            base_low: 0,
+            base_middle: 0,
+            access: 0b10011010,  // Present, Ring 0, Code, Execute/Read
+            granularity: 0b10101111,  // 4KB granularity, 64-bit, limit high = 0xF
+            base_high: 0,
+        }
+    }
+
+    /// Create a kernel data segment (Ring 0, writable)
+    pub const fn kernel_data() -> Self {
+        GdtEntry {
+            limit_low: 0xFFFF,
+            base_low: 0,
+            base_middle: 0,
+            access: 0b10010010,  // Present, Ring 0, Data, Read/Write
+            granularity: 0b11001111,  // 4KB granularity, 32-bit, limit high = 0xF
+            base_high: 0,
+        }
+    }
+
+    /// Create a user code segment (Ring 3, executable, readable)
+    pub const fn user_code() -> Self {
+        GdtEntry {
+            limit_low: 0xFFFF,
+            base_low: 0,
+            base_middle: 0,
+            access: 0b11111010,  // Present, Ring 3, Code, Execute/Read
+            granularity: 0b10101111,  // 4KB granularity, 64-bit, limit high = 0xF
+            base_high: 0,
+        }
+    }
+
+    /// Create a user data segment (Ring 3, writable)
+    pub const fn user_data() -> Self {
+        GdtEntry {
+            limit_low: 0xFFFF,
+            base_low: 0,
+            base_middle: 0,
+            access: 0b11110010,  // Present, Ring 3, Data, Read/Write
+            granularity: 0b11001111,  // 4KB granularity, 32-bit, limit high = 0xF
+            base_high: 0,
+        }
+    }
+
+    /// Create a TSS descriptor from a TSS reference
+    pub fn tss(tss: &'static TaskStateSegment) -> [GdtEntry; 2] {
+        let ptr = tss as *const _ as u64;
+        let limit = (size_of::<TaskStateSegment>() - 1) as u64;
+
+        let low = GdtEntry {
+            limit_low: (limit & 0xFFFF) as u16,
+            base_low: (ptr & 0xFFFF) as u16,
+            base_middle: ((ptr >> 16) & 0xFF) as u8,
+            access: 0b10001001,  // Present, Ring 0, TSS (available)
+            granularity: ((limit >> 16) & 0x0F) as u8,
+            base_high: ((ptr >> 24) & 0xFF) as u8,
+        };
+
+        let high = GdtEntry {
+            limit_low: ((ptr >> 32) & 0xFFFF) as u16,
+            base_low: ((ptr >> 48) & 0xFFFF) as u16,
+            base_middle: 0,
+            access: 0,
+            granularity: 0,
+            base_high: 0,
+        };
+
+        [low, high]
+    }
+}
+
+/// Task State Segment - Holds stack pointers for privilege transitions
+#[derive(Debug, Clone, Copy)]
+#[repr(C, packed)]
+pub struct TaskStateSegment {
+    reserved_1: u32,
+    /// Privilege stack pointers (RSP for rings 0-2)
+    pub rsp: [u64; 3],
+    reserved_2: u64,
+    /// Interrupt stack table (IST 1-7)
+    pub ist: [u64; 7],
+    reserved_3: u64,
+    reserved_4: u16,
+    /// I/O Map Base Address
+    pub iomap_base: u16,
+}
+
+impl TaskStateSegment {
+    /// Create a new TSS with default values
+    pub const fn new() -> Self {
+        TaskStateSegment {
+            reserved_1: 0,
+            rsp: [0; 3],
+            reserved_2: 0,
+            ist: [0; 7],
+            reserved_3: 0,
+            reserved_4: 0,
+            iomap_base: size_of::<TaskStateSegment>() as u16,
+        }
+    }
+
+    /// Set the kernel stack pointer (used when switching from Ring 3 to Ring 0)
+    pub fn set_kernel_stack(&mut self, stack_ptr: u64) {
+        self.rsp[0] = stack_ptr;
+    }
+
+    /// Set an interrupt stack (IST entry)
+    pub fn set_interrupt_stack(&mut self, index: usize, stack_ptr: u64) {
+        if index < 7 {
+            self.ist[index] = stack_ptr;
+        }
+    }
+}
+
+/// GDT Pointer structure for LGDT instruction
+#[repr(C, packed)]
+struct GdtPointer {
+    limit: u16,
+    base: u64,
+}
+
+/// The Global Descriptor Table
+#[repr(align(16))]
+pub struct GlobalDescriptorTable {
+    entries: [GdtEntry; 8],  // Null, K_Code, K_Data, U_Code, U_Data, TSS_Low, TSS_High, Reserved
+    len: usize,
+}
+
+impl GlobalDescriptorTable {
+    /// Create a new GDT with default segments
+    pub const fn new() -> Self {
+        GlobalDescriptorTable {
+            entries: [GdtEntry::null(); 8],
+            len: 1,  // Start with null descriptor
+        }
+    }
+
+    /// Initialize the GDT with kernel and user segments
+    pub fn initialize(&mut self, tss: &'static TaskStateSegment) {
+        self.len = 1;  // Reset to just null descriptor
+
+        // Add kernel code segment (index 1, selector 0x08)
+        self.entries[self.len] = GdtEntry::kernel_code();
+        self.len += 1;
+
+        // Add kernel data segment (index 2, selector 0x10)
+        self.entries[self.len] = GdtEntry::kernel_data();
+        self.len += 1;
+
+        // Add user code segment (index 3, selector 0x18)
+        self.entries[self.len] = GdtEntry::user_code();
+        self.len += 1;
+
+        // Add user data segment (index 4, selector 0x20)
+        self.entries[self.len] = GdtEntry::user_data();
+        self.len += 1;
+
+        // Add TSS (takes 2 entries in 64-bit mode)
+        let tss_entries = GdtEntry::tss(tss);
+        self.entries[self.len] = tss_entries[0];
+        self.len += 1;
+        self.entries[self.len] = tss_entries[1];
+        self.len += 1;
+    }
+
+    /// Load the GDT and reload segment registers
+    pub fn load(&'static self) {
+        let ptr = GdtPointer {
+            limit: (self.len * size_of::<GdtEntry>() - 1) as u16,
+            base: self.entries.as_ptr() as u64,
+        };
+
+        unsafe {
+            // Load GDT
+            asm!("lgdt [{}]", in(reg) &ptr, options(readonly, nostack, preserves_flags));
+
+            // Reload segment registers
+            // Code segment via far return
+            asm!(
+                "push 0x08",           // Push kernel code selector
+                "lea {tmp}, [rip + 2f]",
+                "push {tmp}",
+                "retfq",               // Far return to reload CS
+                "2:",
+                tmp = lateout(reg) _,
+                options(preserves_flags),
+            );
+
+            // Data segments
+            asm!(
+                "mov ax, 0x10",        // Kernel data selector
+                "mov ds, ax",
+                "mov es, ax",
+                "mov fs, ax",
+                "mov gs, ax",
+                "mov ss, ax",
+                out("ax") _,
+                options(preserves_flags, nostack),
+            );
+        }
+    }
+
+    /// Load the Task State Segment
+    pub fn load_tss(&self) {
+        unsafe {
+            // TSS selector is at index 5, so selector = 5 * 8 = 0x28
+            asm!("ltr ax", in("ax") 0x28u16, options(nostack, preserves_flags));
+        }
+    }
+}
+
+/// Segment selectors
+#[allow(dead_code)]
+pub mod selectors {
+    /// Kernel code segment selector (Ring 0)
+    pub const KERNEL_CODE: u16 = 0x08;
+
+    /// Kernel data segment selector (Ring 0)
+    pub const KERNEL_DATA: u16 = 0x10;
+
+    /// User code segment selector (Ring 3)
+    pub const USER_CODE: u16 = 0x18 | 3;  // RPL = 3
+
+    /// User data segment selector (Ring 3)
+    pub const USER_DATA: u16 = 0x20 | 3;  // RPL = 3
+
+    /// TSS selector
+    pub const TSS: u16 = 0x28;
+}

aethelos-source/heartwood/src/attunement/idt.rs

···
+//! # The Interrupt Conduit
+//!
+//! Where hardware whispers to the kernel.
+//! Interrupts are invitations, not intrusions.
+//! Each interrupt is a message from hardware seeking harmony.
+
+use core::arch::asm;
+use core::mem::size_of;
+
+#[path = "idt_handlers.rs"]
+pub(super) mod idt_handlers;
+
+/// The Interrupt Descriptor Table - 256 entries
+pub struct InterruptDescriptorTable {
+    entries: [IdtEntry; 256],
+}
+
+/// A single entry in the IDT
+#[derive(Clone, Copy)]
+#[repr(C, packed)]
+struct IdtEntry {
+    offset_low: u16,      // Lower 16 bits of handler address
+    selector: u16,        // Code segment selector
+    ist: u8,              // Interrupt Stack Table offset (0 = don't use)
+    flags: u8,            // Type and attributes
+    offset_mid: u16,      // Middle 16 bits of handler address
+    offset_high: u32,     // Upper 32 bits of handler address
+    reserved: u32,        // Must be zero
+}
+
+/// IDT Pointer structure for loading
+#[repr(C, packed)]
+struct IdtPointer {
+    limit: u16,
+    base: u64,
+}
+
+impl IdtEntry {
+    /// Create a null entry
+    const fn null() -> Self {
+        Self {
+            offset_low: 0,
+            selector: 0,
+            ist: 0,
+            flags: 0,
+            offset_mid: 0,
+            offset_high: 0,
+            reserved: 0,
+        }
+    }
+
+    /// Create an interrupt gate entry
+    fn new(handler: usize, selector: u16) -> Self {
+        Self {
+            offset_low: (handler & 0xFFFF) as u16,
+            selector,
+            ist: 0,
+            flags: 0x8E, // Present, DPL=0, Type=Interrupt Gate (0x8E)
+            offset_mid: ((handler >> 16) & 0xFFFF) as u16,
+            offset_high: ((handler >> 32) & 0xFFFFFFFF) as u32,
+            reserved: 0,
+        }
+    }
+
+    /// Create a trap gate entry (for exceptions)
+    fn new_trap(handler: usize, selector: u16) -> Self {
+        Self {
+            offset_low: (handler & 0xFFFF) as u16,
+            selector,
+            ist: 0,
+            flags: 0x8F, // Present, DPL=0, Type=Trap Gate (0x8F)
+            offset_mid: ((handler >> 16) & 0xFFFF) as u16,
+            offset_high: ((handler >> 32) & 0xFFFFFFFF) as u32,
+            reserved: 0,
+        }
+    }
+}
+
+impl InterruptDescriptorTable {
+    /// Create a new IDT with all null entries
+    pub const fn new() -> Self {
+        Self {
+            entries: [IdtEntry::null(); 256],
+        }
+    }
+
+    /// Attune to hardware interrupts and exceptions
+    pub fn initialize(&mut self) {
+        use idt_handlers::*;
+
+        // CPU Exceptions (0-31) - These are disharmony alerts
+        self.set_trap_handler(0, divide_by_zero_handler);
+        self.set_trap_handler(1, debug_handler);
+        self.set_trap_handler(2, nmi_handler);
+        self.set_trap_handler(3, breakpoint_handler);
+        self.set_trap_handler(4, overflow_handler);
+        self.set_trap_handler(5, bound_range_handler);
+        self.set_trap_handler(6, invalid_opcode_handler);
+        self.set_trap_handler(7, device_not_available_handler);
+        self.set_trap_handler(8, double_fault_handler);
+        // 9 is reserved (legacy)
+        self.set_trap_handler(10, invalid_tss_handler);
+        self.set_trap_handler(11, segment_not_present_handler);
+        self.set_trap_handler(12, stack_segment_fault_handler);
+        self.set_trap_handler(13, general_protection_fault_handler);
+        self.set_trap_handler(14, page_fault_handler);
+        // 15 is reserved
+        self.set_trap_handler(16, x87_floating_point_handler);
+        self.set_trap_handler(17, alignment_check_handler);
+        self.set_trap_handler(18, machine_check_handler);
+        self.set_trap_handler(19, simd_floating_point_handler);
+        self.set_trap_handler(20, virtualization_handler);
+        // 21-29 are reserved
+        self.set_trap_handler(30, security_exception_handler);
+        // 31 is reserved
+
+        // Hardware Interrupts (32-47) - IRQs remapped from PIC
+        // These are invitations from hardware
+        self.set_interrupt_handler(32, timer_handler);        // IRQ 0 - The Pulse of Time
+        self.set_interrupt_handler(33, keyboard_handler);     // IRQ 1 - The Voice of Intent
+        self.set_interrupt_handler(34, cascade_handler);      // IRQ 2 - PIC cascade
+        self.set_interrupt_handler(35, com2_handler);         // IRQ 3 - Serial port 2
+        self.set_interrupt_handler(36, com1_handler);         // IRQ 4 - Serial port 1
+        self.set_interrupt_handler(37, lpt2_handler);         // IRQ 5 - Parallel port 2
+        self.set_interrupt_handler(38, floppy_handler);       // IRQ 6 - Floppy disk
+        self.set_interrupt_handler(39, lpt1_handler);         // IRQ 7 - Parallel port 1
+        self.set_interrupt_handler(40, rtc_handler);          // IRQ 8 - Real-time clock
+        self.set_interrupt_handler(41, acpi_handler);         // IRQ 9 - ACPI
+        self.set_interrupt_handler(42, available1_handler);   // IRQ 10 - Available
+        self.set_interrupt_handler(43, available2_handler);   // IRQ 11 - Available
+        self.set_interrupt_handler(44, mouse_handler);        // IRQ 12 - PS/2 Mouse
+        self.set_interrupt_handler(45, fpu_handler);          // IRQ 13 - FPU
+        self.set_interrupt_handler(46, ata1_handler);         // IRQ 14 - Primary ATA
+        self.set_interrupt_handler(47, ata2_handler);         // IRQ 15 - Secondary ATA
+
+        // Software interrupts (48-255)
+        // Used for system calls and inter-process communication
+        self.set_interrupt_handler(128, syscall_handler);     // Int 0x80 - System call
+    }
+
+    /// Set a trap gate handler (for exceptions)
+    fn set_trap_handler(&mut self, index: u8, handler: extern "C" fn()) {
+        let handler_addr = handler as usize;
+        self.entries[index as usize] = IdtEntry::new_trap(handler_addr, 0x08); // 0x08 = kernel code segment
+    }
+
+    /// Set an interrupt gate handler (for hardware interrupts)
+    fn set_interrupt_handler(&mut self, index: u8, handler: extern "C" fn()) {
+        let handler_addr = handler as usize;
+        self.entries[index as usize] = IdtEntry::new(handler_addr, 0x08); // 0x08 = kernel code segment
+    }
+
+    /// Load this IDT into the CPU
+    pub fn load(&self) {
+        let ptr = IdtPointer {
+            limit: (size_of::<Self>() - 1) as u16,
+            base: self as *const _ as u64,
+        };
+
+        unsafe {
+            asm!(
+                "lidt [{}]",
+                in(reg) &ptr,
+                options(readonly, nostack, preserves_flags)
+            );
+        }
+    }
+}
+
+impl Default for InterruptDescriptorTable {
+    fn default() -> Self {
+        Self::new()
+    }
+}

aethelos-source/heartwood/src/attunement/idt_handlers.rs

···
+//! Interrupt handler implementations
+//!
+//! These handlers are called when hardware or CPU exceptions occur.
+
+use core::arch::{asm, naked_asm};
+
+//
+// Exception Handlers (0-31)
+// These are disharmony alerts from the CPU
+//
+
+/// Division by zero - mathematical disharmony
+#[unsafe(naked)]
+pub extern "C" fn divide_by_zero_handler() {
+    unsafe {
+        naked_asm!(
+            "push rax",
+            "push rcx",
+            "push rdx",
+            "push rsi",
+            "push rdi",
+            "push r8",
+            "push r9",
+            "push r10",
+            "push r11",
+            "call {inner}",
+            "pop r11",
+            "pop r10",
+            "pop r9",
+            "pop r8",
+            "pop rdi",
+            "pop rsi",
+            "pop rdx",
+            "pop rcx",
+            "pop rax",
+            "iretq",
+            inner = sym divide_by_zero_inner,
+        );
+    }
+}
+
+extern "C" fn divide_by_zero_inner() {
+    crate::println!("❖ Disharmony: Division by zero attempted");
+    crate::println!("❖ The void cannot be divided.");
+}
+
+/// General Protection Fault - privilege violation
+#[unsafe(naked)]
+pub extern "C" fn general_protection_fault_handler() {
+    unsafe {
+        naked_asm!(
+            "push rax",
+            "push rcx",
+            "push rdx",
+            "push rsi",
+            "push rdi",
+            "push r8",
+            "push r9",
+            "push r10",
+            "push r11",
+            "call {inner}",
+            "pop r11",
+            "pop r10",
+            "pop r9",
+            "pop r8",
+            "pop rdi",
+            "pop rsi",
+            "pop rdx",
+            "pop rcx",
+            "pop rax",
+            "add rsp, 8",
+            "iretq",
+            inner = sym general_protection_fault_inner,
+        );
+    }
+}
+
+extern "C" fn general_protection_fault_inner() {
+    crate::println!("❖ Disharmony: General protection fault");
+    crate::println!("❖ A boundary has been crossed without permission.");
+}
+
+/// Page Fault - memory seeking
+#[unsafe(naked)]
+pub extern "C" fn page_fault_handler() {
+    unsafe {
+        naked_asm!(
+            "push rax",
+            "push rcx",
+            "push rdx",
+            "push rsi",
+            "push rdi",
+            "push r8",
+            "push r9",
+            "push r10",
+            "push r11",
+            "call {inner}",
+            "pop r11",
+            "pop r10",
+            "pop r9",
+            "pop r8",
+            "pop rdi",
+            "pop rsi",
+            "pop rdx",
+            "pop rcx",
+            "pop rax",
+            "add rsp, 8",
+            "iretq",
+            inner = sym page_fault_inner,
+        );
+    }
+}
+
+extern "C" fn page_fault_inner() {
+    let faulting_address: u64;
+    unsafe {
+        asm!("mov {}, cr2", out(reg) faulting_address, options(nostack, preserves_flags));
+    }
+    crate::println!("❖ Disharmony: Page fault at address {:#x}", faulting_address);
+    crate::println!("❖ Memory seeks what has not been granted.");
+}
+
+/// Double Fault - cascade of disharmony
+#[unsafe(naked)]
+pub extern "C" fn double_fault_handler() {
+    unsafe {
+        naked_asm!(
+            "cli",
+            "call {inner}",
+            inner = sym double_fault_inner,
+        );
+    }
+}
+
+extern "C" fn double_fault_inner() -> ! {
+    crate::println!("❖❖❖ CRITICAL DISHARMONY: Double Fault ❖❖❖");
+    crate::println!("❖ The system has lost its balance.");
+    crate::println!("❖ The Heartwood must rest and be reborn.");
+    loop {
+        unsafe { asm!("hlt", options(nostack, nomem)) };
+    }
+}
+
+// Stub handlers for other exceptions
+macro_rules! stub_exception_handler {
+    ($name:ident, $message:expr) => {
+        #[unsafe(naked)]
+        pub extern "C" fn $name() {
+            unsafe {
+                naked_asm!(
+                    "iretq"
+                );
+            }
+        }
+    };
+}
+
+stub_exception_handler!(debug_handler, "Debug exception");
+stub_exception_handler!(nmi_handler, "Non-maskable interrupt");
+stub_exception_handler!(breakpoint_handler, "Breakpoint");
+stub_exception_handler!(overflow_handler, "Overflow");
+stub_exception_handler!(bound_range_handler, "Bound range exceeded");
+stub_exception_handler!(invalid_opcode_handler, "Invalid opcode");
+stub_exception_handler!(device_not_available_handler, "Device not available");
+stub_exception_handler!(invalid_tss_handler, "Invalid TSS");
+stub_exception_handler!(segment_not_present_handler, "Segment not present");
+stub_exception_handler!(stack_segment_fault_handler, "Stack segment fault");
+stub_exception_handler!(x87_floating_point_handler, "x87 FPU error");
+stub_exception_handler!(alignment_check_handler, "Alignment check");
+stub_exception_handler!(machine_check_handler, "Machine check");
+stub_exception_handler!(simd_floating_point_handler, "SIMD floating point");
+stub_exception_handler!(virtualization_handler, "Virtualization exception");
+stub_exception_handler!(security_exception_handler, "Security exception");
+
+//
+// Hardware Interrupt Handlers (32-47)
+// These are invitations from hardware
+//
+
+/// Timer interrupt - The Pulse of Time
+#[unsafe(naked)]
+pub extern "C" fn timer_handler() {
+    unsafe {
+        naked_asm!(
+            "push rax",
+            "push rcx",
+            "push rdx",
+            "push rsi",
+            "push rdi",
+            "push r8",
+            "push r9",
+            "push r10",
+            "push r11",
+            "call {inner}",
+            "mov al, 0x20",
+            "out 0x20, al",
+            "pop r11",
+            "pop r10",
+            "pop r9",
+            "pop r8",
+            "pop rdi",
+            "pop rsi",
+            "pop rdx",
+            "pop rcx",
+            "pop rax",
+            "iretq",
+            inner = sym timer_inner,
+        );
+    }
+}
+
+extern "C" fn timer_inner() {
+    // Will be connected to PIT driver
+    crate::attunement::timer::on_tick();
+}
+
+/// Keyboard interrupt - The Voice of Intent
+#[unsafe(naked)]
+pub extern "C" fn keyboard_handler() {
+    unsafe {
+        naked_asm!(
+            "push rax",
+            "push rcx",
+            "push rdx",
+            "push rsi",
+            "push rdi",
+            "push r8",
+            "push r9",
+            "push r10",
+            "push r11",
+            "call {inner}",
+            "mov al, 0x20",
+            "out 0x20, al",
+            "pop r11",
+            "pop r10",
+            "pop r9",
+            "pop r8",
+            "pop rdi",
+            "pop rsi",
+            "pop rdx",
+            "pop rcx",
+            "pop rax",
+            "iretq",
+            inner = sym keyboard_inner,
+        );
+    }
+}
+
+extern "C" fn keyboard_inner() {
+    // Will be connected to keyboard driver
+    // For now, just read and discard the scancode
+    unsafe {
+        let scancode: u8;
+        asm!("in al, 0x60", out("al") scancode, options(nostack, preserves_flags));
+        // TODO: Send to keyboard driver via Nexus
+    }
+}
+
+// Stub handlers for other hardware interrupts
+macro_rules! stub_irq_handler {
+    ($name:ident, $irq:expr) => {
+        #[unsafe(naked)]
+        pub extern "C" fn $name() {
+            unsafe {
+                naked_asm!(
+                    "push rax",
+                    "mov al, 0x20",
+                    "out 0x20, al",
+                    concat!(".if ", stringify!($irq), " >= 8"),
+                    "out 0xA0, al",
+                    ".endif",
+                    "pop rax",
+                    "iretq",
+                );
+            }
+        }
+    };
+}
+
+stub_irq_handler!(cascade_handler, 2);
+stub_irq_handler!(com2_handler, 3);
+stub_irq_handler!(com1_handler, 4);
+stub_irq_handler!(lpt2_handler, 5);
+stub_irq_handler!(floppy_handler, 6);
+stub_irq_handler!(lpt1_handler, 7);
+stub_irq_handler!(rtc_handler, 8);
+stub_irq_handler!(acpi_handler, 9);
+stub_irq_handler!(available1_handler, 10);
+stub_irq_handler!(available2_handler, 11);
+stub_irq_handler!(mouse_handler, 12);
+stub_irq_handler!(fpu_handler, 13);
+stub_irq_handler!(ata1_handler, 14);
+stub_irq_handler!(ata2_handler, 15);
+
+/// System call handler (Int 0x80)
+#[unsafe(naked)]
+pub extern "C" fn syscall_handler() {
+    unsafe {
+        naked_asm!(
+            "push rax",
+            "push rcx",
+            "push rdx",
+            "push rsi",
+            "push rdi",
+            "push r8",
+            "push r9",
+            "push r10",
+            "push r11",
+            "call {inner}",
+            "pop r11",
+            "pop r10",
+            "pop r9",
+            "pop r8",
+            "pop rdi",
+            "pop rsi",
+            "pop rdx",
+            "pop rcx",
+            "pop rax",
+            "iretq",
+            inner = sym syscall_inner,
+        );
+    }
+}
+
+extern "C" fn syscall_inner() {
+    crate::println!("❖ System call received (not yet implemented)");
+}

aethelos-source/heartwood/src/attunement/mod.rs

···
 //! The Attunement Layer speaks the language of the hardware, translating
 //! the Heartwood's intentions into signals the silicon can comprehend.
 
+pub mod gdt;
+pub mod idt;
+pub mod pic;
+pub mod pit;
+
+use lazy_static::lazy_static;
+use spin::Mutex;
+
+lazy_static! {
+    /// The global Task State Segment
+    static ref TSS: gdt::TaskStateSegment = gdt::TaskStateSegment::new();
+
+    /// The global Global Descriptor Table
+    static ref GDT: gdt::GlobalDescriptorTable = {
+        let mut gdt = gdt::GlobalDescriptorTable::new();
+        gdt.initialize(&TSS);
+        gdt
+    };
+
+    /// The global Interrupt Descriptor Table
+    static ref IDT: Mutex<idt::InterruptDescriptorTable> = {
+        let mut idt = idt::InterruptDescriptorTable::new();
+        idt.initialize();
+        Mutex::new(idt)
+    };
+
+    /// The global PIC configuration
+    static ref PIC: Mutex<pic::Pic> = Mutex::new(pic::Pic::new(32, 40));
+
+    /// The global PIT configuration
+    static ref PIT: pit::Pit = pit::Pit::new();
+}
+
 /// Initialize the Attunement Layer
 pub fn init() {
+    crate::println!("  ◈ Attuning to hardware...");
+
     // Initialize CPU features
     cpu::init();
 
+    // Load the Global Descriptor Table
+    crate::println!("    ∴ Loading privilege rings (GDT)...");
+    GDT.load();
+    GDT.load_tss();
+
+    // Initialize Programmable Interrupt Controller (PIC)
+    // Remap IRQs 0-15 to interrupts 32-47
+    crate::println!("    ∴ Remapping interrupt controller (PIC)...");
+    unsafe {
+        PIC.lock().initialize();
+        PIC.lock().disable_all(); // Start with all IRQs masked
+    }
+
+    // Load the Interrupt Descriptor Table
+    crate::println!("    ∴ Preparing interrupt handlers (IDT)...");
+    IDT.lock().load();
+
     // Initialize interrupt handling
     interrupts::init();
 
-    // Initialize system timer
+    // Initialize system timer (PIT)
+    crate::println!("    ∴ Starting system heartbeat (PIT @ {} Hz)...", PIT.frequency());
     timer::init();
+
+    crate::println!("  ◈ Hardware attunement complete");
 }
 
 /// CPU information and features
···
 
 /// Interrupt handling
 pub mod interrupts {
+    use core::arch::asm;
+
     /// Initialize interrupt handling
     pub fn init() {
-        // In a real implementation:
-        // - Set up IDT (Interrupt Descriptor Table)
-        // - Install interrupt handlers
-        // - Enable interrupts
+        // IDT is already loaded by main init()
+        // Enable interrupts
+        unsafe {
+            enable();
+        }
     }
 
     /// Disable interrupts
-    pub fn disable() {
-        // x86_64::instructions::interrupts::disable();
+    pub unsafe fn disable() {
+        asm!("cli", options(nostack, nomem));
     }
 
     /// Enable interrupts
-    pub fn enable() {
-        // x86_64::instructions::interrupts::enable();
+    pub unsafe fn enable() {
+        asm!("sti", options(nostack, nomem));
+    }
+
+    /// Check if interrupts are enabled
+    pub fn are_enabled() -> bool {
+        let flags: u64;
+        unsafe {
+            asm!("pushf; pop {}", out(reg) flags, options(nomem, preserves_flags));
+        }
+        (flags & 0x200) != 0 // IF flag is bit 9
     }
 }
 
···
 
     lazy_static! {
         static ref TICKS: Mutex<u64> = Mutex::new(0);
+        static ref UPTIME_MS: Mutex<u64> = Mutex::new(0);
     }
 
     /// Initialize the system timer
     pub fn init() {
-        // In a real implementation:
-        // - Configure PIT or APIC timer
-        // - Set up timer interrupt handler
+        // Enable timer IRQ (IRQ 0)
+        unsafe {
+            super::PIC.lock().enable_irq(0);
+        }
+
+        // Initialize the PIT to generate interrupts at 100 Hz
+        unsafe {
+            super::PIT.initialize();
+        }
     }
 
     /// Get the number of timer ticks since boot
···
         *TICKS.lock()
     }
 
+    /// Get uptime in milliseconds
+    pub fn uptime_ms() -> u64 {
+        *UPTIME_MS.lock()
+    }
+
+    /// Get uptime in seconds
+    pub fn uptime_seconds() -> u64 {
+        uptime_ms() / 1000
+    }
+
     /// Timer interrupt handler (called by interrupt)
     pub fn on_tick() {
         let mut ticks = TICKS.lock();
         *ticks += 1;
+
+        // Update uptime (100 Hz = 10ms per tick)
+        let mut uptime = UPTIME_MS.lock();
+        *uptime += super::pit::ms_per_tick(&super::PIT) as u64;
+    }
+
+    /// Sleep for approximately the given number of milliseconds
+    ///
+    /// # Note
+    /// This is a busy-wait implementation. In a real system, this would
+    /// yield to the scheduler.
+    pub fn sleep_ms(ms: u64) {
+        let start = uptime_ms();
+        while uptime_ms() - start < ms {
+            core::hint::spin_loop();
+        }
+    }
+
+    /// Sleep for approximately the given number of ticks
+    pub fn sleep_ticks(ticks_to_wait: u64) {
+        let start = ticks();
+        while ticks() - start < ticks_to_wait {
+            core::hint::spin_loop();
+        }
     }
 }

aethelos-source/heartwood/src/attunement/pic.rs

···
+//! # Programmable Interrupt Controller (PIC)
+//!
+//! The 8259 PIC manages hardware interrupts.
+//! We remap IRQs 0-15 to interrupts 32-47 to avoid conflicts with CPU exceptions.
+
+use core::arch::asm;
+
+/// I/O ports for the PICs
+const PIC1_COMMAND: u16 = 0x20;
+const PIC1_DATA: u16 = 0x21;
+const PIC2_COMMAND: u16 = 0xA0;
+const PIC2_DATA: u16 = 0xA1;
+
+/// PIC initialization command words
+const ICW1_INIT: u8 = 0x10;
+const ICW1_ICW4: u8 = 0x01;
+const ICW4_8086: u8 = 0x01;
+
+/// End of Interrupt command
+const EOI: u8 = 0x20;
+
+/// The dual 8259 PIC configuration
+pub struct Pic {
+    offset1: u8,  // Offset for PIC1 (usually 32)
+    offset2: u8,  // Offset for PIC2 (usually 40)
+}
+
+impl Pic {
+    /// Create a new PIC configuration
+    pub const fn new(offset1: u8, offset2: u8) -> Self {
+        Self { offset1, offset2 }
+    }
+
+    /// Initialize and remap the PICs
+    ///
+    /// # Safety
+    ///
+    /// This must be called exactly once during system initialization.
+    /// Incorrect PIC configuration can cause system instability.
+    pub unsafe fn initialize(&self) {
+        // Save masks
+        let mask1 = inb(PIC1_DATA);
+        let mask2 = inb(PIC2_DATA);
+
+        // Start initialization sequence
+        outb(PIC1_COMMAND, ICW1_INIT | ICW1_ICW4);
+        io_wait();
+        outb(PIC2_COMMAND, ICW1_INIT | ICW1_ICW4);
+        io_wait();
+
+        // Set vector offsets
+        outb(PIC1_DATA, self.offset1);
+        io_wait();
+        outb(PIC2_DATA, self.offset2);
+        io_wait();
+
+        // Tell PIC1 about PIC2 (cascade)
+        outb(PIC1_DATA, 4);  // PIC2 is at IRQ2
+        io_wait();
+        outb(PIC2_DATA, 2);  // Cascade identity
+        io_wait();
+
+        // Set 8086 mode
+        outb(PIC1_DATA, ICW4_8086);
+        io_wait();
+        outb(PIC2_DATA, ICW4_8086);
+        io_wait();
+
+        // Restore masks
+        outb(PIC1_DATA, mask1);
+        outb(PIC2_DATA, mask2);
+    }
+
+    /// Disable all interrupts (mask all IRQs)
+    pub unsafe fn disable_all(&self) {
+        outb(PIC1_DATA, 0xFF);
+        outb(PIC2_DATA, 0xFF);
+    }
+
+    /// Enable specific IRQ
+    pub unsafe fn enable_irq(&self, irq: u8) {
+        let port = if irq < 8 {
+            PIC1_DATA
+        } else {
+            PIC2_DATA
+        };
+
+        let value = inb(port);
+        let mask = !(1 << (irq % 8));
+        outb(port, value & mask);
+    }
+
+    /// Disable specific IRQ
+    pub unsafe fn disable_irq(&self, irq: u8) {
+        let port = if irq < 8 {
+            PIC1_DATA
+        } else {
+            PIC2_DATA
+        };
+
+        let value = inb(port);
+        let mask = 1 << (irq % 8);
+        outb(port, value | mask);
+    }
+
+    /// Send End of Interrupt signal
+    pub unsafe fn send_eoi(&self, irq: u8) {
+        if irq >= 8 {
+            outb(PIC2_COMMAND, EOI);
+        }
+        outb(PIC1_COMMAND, EOI);
+    }
+}
+
+/// Read a byte from an I/O port
+#[inline]
+unsafe fn inb(port: u16) -> u8 {
+    let value: u8;
+    asm!(
+        "in al, dx",
+        out("al") value,
+        in("dx") port,
+        options(nostack, preserves_flags)
+    );
+    value
+}
+
+/// Write a byte to an I/O port
+#[inline]
+unsafe fn outb(port: u16, value: u8) {
+    asm!(
+        "out dx, al",
+        in("dx") port,
+        in("al") value,
+        options(nostack, preserves_flags)
+    );
+}
+
+/// Wait for an I/O operation to complete
+/// Uses port 0x80 (POST diagnostic port) for a brief delay
+#[inline]
+unsafe fn io_wait() {
+    outb(0x80, 0);
+}

aethelos-source/heartwood/src/attunement/pit.rs

···
+//! # Programmable Interval Timer (PIT)
+//!
+//! The heartbeat of AethelOS - the system's sense of time's passage.
+//! The PIT provides rhythmic interrupts that drive scheduling, timeouts,
+//! and our awareness of temporal flow.
+//!
+//! ## Philosophy
+//! Time in AethelOS is not a tyrant demanding rigid adherence,
+//! but a gentle rhythm that guides cooperation.
+//! The PIT ticks not to command, but to remind us that moments pass.
+//!
+//! ## Technical Details
+//! The Intel 8253/8254 PIT has three channels:
+//! - Channel 0: System timer (IRQ 0)
+//! - Channel 1: DRAM refresh (legacy, unused)
+//! - Channel 2: PC speaker
+//!
+//! We use Channel 0 in mode 3 (square wave generator) for periodic interrupts.
+
+use core::arch::asm;
+
+/// PIT I/O ports
+const PIT_CHANNEL0: u16 = 0x40; // Channel 0 data port (system timer)
+const PIT_CHANNEL1: u16 = 0x41; // Channel 1 data port (unused)
+const PIT_CHANNEL2: u16 = 0x42; // Channel 2 data port (PC speaker)
+const PIT_COMMAND: u16 = 0x43;  // Mode/Command register
+
+/// PIT base frequency (Hz)
+const PIT_BASE_FREQ: u32 = 1193182;
+
+/// Default timer frequency (100 Hz = 10ms per tick)
+/// This provides a good balance between precision and overhead
+const DEFAULT_FREQ: u32 = 100;
+
+/// PIT command byte components
+/// Format: [Channel (2 bits)][Access mode (2 bits)][Operating mode (3 bits)][BCD (1 bit)]
+const CMD_CHANNEL0: u8 = 0b00_000000;      // Select channel 0
+const CMD_ACCESS_LOHI: u8 = 0b00_11_0000;  // Access mode: lobyte/hibyte
+const CMD_MODE3: u8 = 0b00_00_011_0;       // Operating mode 3: square wave
+const CMD_BINARY: u8 = 0b00_00_000_0;      // Binary mode (not BCD)
+
+/// Helper function to output a byte to an I/O port
+#[inline]
+unsafe fn outb(port: u16, value: u8) {
+    asm!("out dx, al", in("dx") port, in("al") value, options(nomem, nostack, preserves_flags));
+}
+
+/// Helper function to input a byte from an I/O port
+#[inline]
+unsafe fn inb(port: u16) -> u8 {
+    let value: u8;
+    asm!("in al, dx", out("al") value, in("dx") port, options(nomem, nostack, preserves_flags));
+    value
+}
+
+/// The Programmable Interval Timer
+pub struct Pit {
+    frequency: u32,
+    divisor: u16,
+    ticks_per_second: u32,
+}
+
+impl Pit {
+    /// Create a new PIT configuration with default frequency
+    pub const fn new() -> Self {
+        let divisor = (PIT_BASE_FREQ / DEFAULT_FREQ) as u16;
+        Pit {
+            frequency: DEFAULT_FREQ,
+            divisor,
+            ticks_per_second: DEFAULT_FREQ,
+        }
+    }
+
+    /// Create a PIT with custom frequency
+    ///
+    /// # Arguments
+    /// * `freq` - Desired frequency in Hz (18.2 Hz to 1.19 MHz)
+    ///
+    /// # Note
+    /// The actual frequency may differ slightly due to integer division.
+    pub fn with_frequency(freq: u32) -> Self {
+        let freq = freq.clamp(18, PIT_BASE_FREQ);
+        let divisor = (PIT_BASE_FREQ / freq) as u16;
+        let actual_freq = PIT_BASE_FREQ / divisor as u32;
+
+        Pit {
+            frequency: actual_freq,
+            divisor,
+            ticks_per_second: actual_freq,
+        }
+    }
+
+    /// Initialize the PIT and start generating interrupts
+    ///
+    /// # Safety
+    /// This function writes to I/O ports and should only be called once during boot.
+    pub unsafe fn initialize(&self) {
+        // Disable interrupts during PIT programming
+        asm!("cli", options(nomem, nostack));
+
+        // Send command byte: Channel 0, lobyte/hibyte, mode 3, binary
+        let command = CMD_CHANNEL0 | CMD_ACCESS_LOHI | CMD_MODE3 | CMD_BINARY;
+        outb(PIT_COMMAND, command);
+
+        // Send divisor (low byte, then high byte)
+        outb(PIT_CHANNEL0, (self.divisor & 0xFF) as u8);
+        outb(PIT_CHANNEL0, ((self.divisor >> 8) & 0xFF) as u8);
+
+        // Re-enable interrupts
+        asm!("sti", options(nomem, nostack));
+    }
+
+    /// Get the configured frequency in Hz
+    pub fn frequency(&self) -> u32 {
+        self.frequency
+    }
+
+    /// Get the divisor value
+    pub fn divisor(&self) -> u16 {
+        self.divisor
+    }
+
+    /// Get ticks per second (same as frequency)
+    pub fn ticks_per_second(&self) -> u32 {
+        self.ticks_per_second
+    }
+
+    /// Read the current counter value
+    ///
+    /// # Safety
+    /// Reads from I/O ports. The value may be unreliable if called during a count update.
+    pub unsafe fn read_count(&self) -> u16 {
+        // Send latch command
+        outb(PIT_COMMAND, 0b00_00_0000);
+
+        // Read count (low byte, then high byte)
+        let low = inb(PIT_CHANNEL0) as u16;
+        let high = inb(PIT_CHANNEL0) as u16;
+
+        (high << 8) | low
+    }
+}
+
+/// Calculate milliseconds per tick for the current PIT frequency
+pub fn ms_per_tick(pit: &Pit) -> u32 {
+    1000 / pit.frequency()
+}
+
+/// Calculate microseconds per tick for the current PIT frequency
+pub fn us_per_tick(pit: &Pit) -> u32 {
+    1_000_000 / pit.frequency()
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_divisor_calculation() {
+        let pit = Pit::new();
+        // For 100 Hz: 1193182 / 100 = 11931.82, should round to 11931
+        assert_eq!(pit.divisor(), 11931);
+    }
+
+    #[test]
+    fn test_frequency() {
+        let pit = Pit::new();
+        assert!(pit.frequency() >= 99 && pit.frequency() <= 101);
+    }
+
+    #[test]
+    fn test_custom_frequency() {
+        let pit = Pit::with_frequency(1000);
+        assert!(pit.frequency() >= 999 && pit.frequency() <= 1001);
+    }
+
+    #[test]
+    fn test_ms_per_tick() {
+        let pit = Pit::new();
+        let ms = ms_per_tick(&pit);
+        assert!(ms >= 9 && ms <= 11); // Should be ~10ms
+    }
+}