0007/0008 were gated on PCI 0x20C2 plus an exact VBIOS string, so only 8gb cards on the 300W 92.00.6D.00.0A build could clock. Device check is now 0x20C2 or 0x2082, and the stock NDIV is read out of the PLL instead of assumed. The post-GSP COEFF write hardcoded MDIV/PDIV for that one VBIOS and would have written wrong divisors anywhere else; it is a read-modify- write now, like the pre-GSP path already was. The NDIV literal is an XX placeholder, so a tree that build.sh did not substitute fails to compile instead of quietly running 1890 MHz. Rebased onto PCIe Gen2: upstream took 0007/0008 for its own patches, so the mclk pair is 0009/0010. Both it and Gen2 insert at the same anchor in kernel_gsp_tu102.c; the mclk block is placed after the Gen2 register writes. The three FBPA_PLL entries are merged into the plmTable that Gen2 also extended, and the loop bound is NV_ARRAY_ELEMENTS so the two additions cannot desync it again. install.sh warns when the PCI ID cannot clock and when a mixed 8gb+10gb inventory would get one multiplier, build.sh validates it and records it next to card_profile, and verify.sh reports it against dmesg.