tjh.dev
nixpkgs mirror (for testing)
github.com/NixOS/nixpkgs
nix
1{
2 lib,
3 buildPythonPackage,
4 fetchPypi,
5
6 # build-system
7 setuptools,
8
9 # tests
10 ghdl,
11 iverilog,
12 pytestCheckHook,
13}:
14
15buildPythonPackage rec {
16 pname = "myhdl";
17 version = "0.11.51";
18 pyproject = true;
19
20 # No recent tags on GitHub
21 src = fetchPypi {
22 inherit pname version;
23 hash = "sha256-nZEdYLRjk2rgS3byc4iu9oJazodnoNg63MBUMasGZiw=";
24 };
25
26 build-system = [
27 setuptools
28 ];
29
30 nativeCheckInputs = [
31 ghdl
32 iverilog
33 pytestCheckHook
34 ];
35
36 enabledTestPaths = [
37 "myhdl/test"
38 ];
39
40 disabledTestPaths = [
41 # myhdl.CosimulationError: Premature simulation end
42 # ----------------------------- Captured stdout call -----------------------------
43 # binaryOps.o: Program not runnable, 2 errors.
44 # ----------------------------- Captured stderr call -----------------------------
45 # ../../../../cosimulation/icarus/myhdl.vpi: Unable to find module file `../../../../cosimulation/icarus/myhdl.vpi' or `../../../../cosimulation/icarus/myhdl.vpi.vpi'.
46 # tb_binaryOps.v:24: Error: System task/function $from_myhdl() is not defined by any module.
47 # tb_binaryOps.v:29: Error: System task/function $to_myhdl() is not defined by any module.
48 "myhdl/test/conversion/toVerilog/test_GrayInc.py"
49 "myhdl/test/conversion/toVerilog/test_RandomScrambler.py"
50 "myhdl/test/conversion/toVerilog/test_always_comb.py"
51 "myhdl/test/conversion/toVerilog/test_beh.py"
52 "myhdl/test/conversion/toVerilog/test_bin2gray.py"
53 "myhdl/test/conversion/toVerilog/test_dec.py"
54 "myhdl/test/conversion/toVerilog/test_edge.py"
55 "myhdl/test/conversion/toVerilog/test_fsm.py"
56 "myhdl/test/conversion/toVerilog/test_hec.py"
57 "myhdl/test/conversion/toVerilog/test_inc.py"
58 "myhdl/test/conversion/toVerilog/test_loops.py"
59 "myhdl/test/conversion/toVerilog/test_misc.py"
60 "myhdl/test/conversion/toVerilog/test_ops.py"
61 "myhdl/test/conversion/toVerilog/test_ram.py"
62 "myhdl/test/conversion/toVerilog/test_rom.py"
63 ];
64
65 disabledTests = [
66 # myhdl.CosimulationError: Premature simulation end
67 # ----------------------------- Captured stdout call -----------------------------
68 # binaryOps.o: Program not runnable, 2 errors.
69 # ----------------------------- Captured stderr call -----------------------------
70 # ../../../../cosimulation/icarus/myhdl.vpi: Unable to find module file `../../../../cosimulation/icarus/myhdl.vpi' or `../../../../cosimulation/icarus/myhdl.vpi.vpi'.
71 # tb_binaryOps.v:24: Error: System task/function $from_myhdl() is not defined by any module.
72 # tb_binaryOps.v:29: Error: System task/function $to_myhdl() is not defined by any module.
73 "TestInc"
74 "TestInfer"
75 "testAugmOps"
76 "testBinaryOps"
77 "testUnaryOps"
78 ];
79
80 passthru = {
81 # If using myhdl as a dependency, use these if needed and not ghdl and
82 # verlog from all-packages.nix
83 inherit ghdl iverilog;
84 };
85
86 meta = {
87 description = "Free, open-source package for using Python as a hardware description and verification language";
88 homepage = "https://www.myhdl.org/";
89 license = lib.licenses.lgpl21;
90 maintainers = with lib.maintainers; [ doronbehar ];
91 };
92}