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1library IEEE;
2use IEEE.STD_LOGIC_1164.all;
3use IEEE.NUMERIC_STD.ALL;
4use IEEE.STD_LOGIC_MISC.or_reduce;
5
6entity simple is
7
8port (
9 CLK, RESET : in std_ulogic;
10 DATA_OUT : out std_ulogic_vector(7 downto 0);
11 DONE_OUT : out std_ulogic
12);
13end simple;
14
15architecture beh of simple is
16
17signal data : std_ulogic_vector(7 downto 0);
18signal done: std_ulogic;
19
20begin
21
22proc_ctr : process(CLK)
23begin
24if (CLK = '1' and CLK'event) then
25 if (RESET = '1') then
26 data <= "01011111";
27 done <= '0';
28 else
29 case data is
30 when "00100000" => data <= "01001110";
31 when "01001110" => data <= "01101001";
32 when "01101001" => data <= "01111000";
33 when "01111000" => data <= "01001111";
34 when "01001111" => data <= "01010011";
35 when others => data <= "00100000";
36 end case;
37 done <= not or_reduce(data xor "01010011");
38 end if;
39end if;
40end process;
41
42DATA_OUT <= data;
43DONE_OUT <= done;
44
45end beh;