Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * RISC-V processor specific defines
4 *
5 * Copyright (C) 2021 Western Digital Corporation or its affiliates.
6 */
7#ifndef SELFTEST_KVM_PROCESSOR_H
8#define SELFTEST_KVM_PROCESSOR_H
9
10#include "kvm_util.h"
11#include <linux/stringify.h>
12
13static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t subtype,
14 uint64_t idx, uint64_t size)
15{
16 return KVM_REG_RISCV | type | subtype | idx | size;
17}
18
19#if __riscv_xlen == 64
20#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U64
21#else
22#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U32
23#endif
24
25#define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, 0, \
26 KVM_REG_RISCV_CONFIG_REG(name), \
27 KVM_REG_SIZE_ULONG)
28
29#define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, 0, \
30 KVM_REG_RISCV_CORE_REG(name), \
31 KVM_REG_SIZE_ULONG)
32
33#define RISCV_GENERAL_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \
34 KVM_REG_RISCV_CSR_GENERAL, \
35 KVM_REG_RISCV_CSR_REG(name), \
36 KVM_REG_SIZE_ULONG)
37
38#define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, 0, \
39 KVM_REG_RISCV_TIMER_REG(name), \
40 KVM_REG_SIZE_U64)
41
42#define RISCV_ISA_EXT_REG(idx) __kvm_reg_id(KVM_REG_RISCV_ISA_EXT, \
43 KVM_REG_RISCV_ISA_SINGLE, \
44 idx, KVM_REG_SIZE_ULONG)
45
46#define RISCV_SBI_EXT_REG(idx) __kvm_reg_id(KVM_REG_RISCV_SBI_EXT, \
47 KVM_REG_RISCV_SBI_SINGLE, \
48 idx, KVM_REG_SIZE_ULONG)
49
50/* L3 index Bit[47:39] */
51#define PGTBL_L3_INDEX_MASK 0x0000FF8000000000ULL
52#define PGTBL_L3_INDEX_SHIFT 39
53#define PGTBL_L3_BLOCK_SHIFT 39
54#define PGTBL_L3_BLOCK_SIZE 0x0000008000000000ULL
55#define PGTBL_L3_MAP_MASK (~(PGTBL_L3_BLOCK_SIZE - 1))
56/* L2 index Bit[38:30] */
57#define PGTBL_L2_INDEX_MASK 0x0000007FC0000000ULL
58#define PGTBL_L2_INDEX_SHIFT 30
59#define PGTBL_L2_BLOCK_SHIFT 30
60#define PGTBL_L2_BLOCK_SIZE 0x0000000040000000ULL
61#define PGTBL_L2_MAP_MASK (~(PGTBL_L2_BLOCK_SIZE - 1))
62/* L1 index Bit[29:21] */
63#define PGTBL_L1_INDEX_MASK 0x000000003FE00000ULL
64#define PGTBL_L1_INDEX_SHIFT 21
65#define PGTBL_L1_BLOCK_SHIFT 21
66#define PGTBL_L1_BLOCK_SIZE 0x0000000000200000ULL
67#define PGTBL_L1_MAP_MASK (~(PGTBL_L1_BLOCK_SIZE - 1))
68/* L0 index Bit[20:12] */
69#define PGTBL_L0_INDEX_MASK 0x00000000001FF000ULL
70#define PGTBL_L0_INDEX_SHIFT 12
71#define PGTBL_L0_BLOCK_SHIFT 12
72#define PGTBL_L0_BLOCK_SIZE 0x0000000000001000ULL
73#define PGTBL_L0_MAP_MASK (~(PGTBL_L0_BLOCK_SIZE - 1))
74
75#define PGTBL_PTE_ADDR_MASK 0x003FFFFFFFFFFC00ULL
76#define PGTBL_PTE_ADDR_SHIFT 10
77#define PGTBL_PTE_RSW_MASK 0x0000000000000300ULL
78#define PGTBL_PTE_RSW_SHIFT 8
79#define PGTBL_PTE_DIRTY_MASK 0x0000000000000080ULL
80#define PGTBL_PTE_DIRTY_SHIFT 7
81#define PGTBL_PTE_ACCESSED_MASK 0x0000000000000040ULL
82#define PGTBL_PTE_ACCESSED_SHIFT 6
83#define PGTBL_PTE_GLOBAL_MASK 0x0000000000000020ULL
84#define PGTBL_PTE_GLOBAL_SHIFT 5
85#define PGTBL_PTE_USER_MASK 0x0000000000000010ULL
86#define PGTBL_PTE_USER_SHIFT 4
87#define PGTBL_PTE_EXECUTE_MASK 0x0000000000000008ULL
88#define PGTBL_PTE_EXECUTE_SHIFT 3
89#define PGTBL_PTE_WRITE_MASK 0x0000000000000004ULL
90#define PGTBL_PTE_WRITE_SHIFT 2
91#define PGTBL_PTE_READ_MASK 0x0000000000000002ULL
92#define PGTBL_PTE_READ_SHIFT 1
93#define PGTBL_PTE_PERM_MASK (PGTBL_PTE_ACCESSED_MASK | \
94 PGTBL_PTE_DIRTY_MASK | \
95 PGTBL_PTE_EXECUTE_MASK | \
96 PGTBL_PTE_WRITE_MASK | \
97 PGTBL_PTE_READ_MASK)
98#define PGTBL_PTE_VALID_MASK 0x0000000000000001ULL
99#define PGTBL_PTE_VALID_SHIFT 0
100
101#define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE
102#define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT
103
104#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
105#define SATP_MODE_39 _AC(0x8000000000000000, UL)
106#define SATP_MODE_48 _AC(0x9000000000000000, UL)
107#define SATP_ASID_BITS 16
108#define SATP_ASID_SHIFT 44
109#define SATP_ASID_MASK _AC(0xFFFF, UL)
110
111/* SBI return error codes */
112#define SBI_SUCCESS 0
113#define SBI_ERR_FAILURE -1
114#define SBI_ERR_NOT_SUPPORTED -2
115#define SBI_ERR_INVALID_PARAM -3
116#define SBI_ERR_DENIED -4
117#define SBI_ERR_INVALID_ADDRESS -5
118#define SBI_ERR_ALREADY_AVAILABLE -6
119#define SBI_ERR_ALREADY_STARTED -7
120#define SBI_ERR_ALREADY_STOPPED -8
121
122#define SBI_EXT_EXPERIMENTAL_START 0x08000000
123#define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF
124
125#define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END
126#define KVM_RISCV_SELFTESTS_SBI_UCALL 0
127#define KVM_RISCV_SELFTESTS_SBI_UNEXP 1
128
129enum sbi_ext_id {
130 SBI_EXT_BASE = 0x10,
131 SBI_EXT_STA = 0x535441,
132};
133
134enum sbi_ext_base_fid {
135 SBI_EXT_BASE_PROBE_EXT = 3,
136};
137
138struct sbiret {
139 long error;
140 long value;
141};
142
143struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
144 unsigned long arg1, unsigned long arg2,
145 unsigned long arg3, unsigned long arg4,
146 unsigned long arg5);
147
148bool guest_sbi_probe_extension(int extid, long *out_val);
149
150#endif /* SELFTEST_KVM_PROCESSOR_H */