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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3
4 Header file for stmmac platform data
5
6 Copyright (C) 2009 STMicroelectronics Ltd
7
8
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10*******************************************************************************/
11
12#ifndef __STMMAC_PLATFORM_DATA
13#define __STMMAC_PLATFORM_DATA
14
15#include <linux/platform_device.h>
16#include <linux/phy.h>
17
18#define MTL_MAX_RX_QUEUES 8
19#define MTL_MAX_TX_QUEUES 8
20#define STMMAC_CH_MAX 8
21
22#define STMMAC_RX_COE_NONE 0
23#define STMMAC_RX_COE_TYPE1 1
24#define STMMAC_RX_COE_TYPE2 2
25
26/* Define the macros for CSR clock range parameters to be passed by
27 * platform code.
28 * This could also be configured at run time using CPU freq framework. */
29
30/* MDC Clock Selection define*/
31#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
32#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
33#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
34#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
35#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
36#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
37
38/* MTL algorithms identifiers */
39#define MTL_TX_ALGORITHM_WRR 0x0
40#define MTL_TX_ALGORITHM_WFQ 0x1
41#define MTL_TX_ALGORITHM_DWRR 0x2
42#define MTL_TX_ALGORITHM_SP 0x3
43#define MTL_RX_ALGORITHM_SP 0x4
44#define MTL_RX_ALGORITHM_WSP 0x5
45
46/* RX/TX Queue Mode */
47#define MTL_QUEUE_AVB 0x0
48#define MTL_QUEUE_DCB 0x1
49
50/* The MDC clock could be set higher than the IEEE 802.3
51 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
52 * of value different than the above defined values. The resultant MDIO
53 * clock frequency of 12.5 MHz is applicable for the interfacing chips
54 * supporting higher MDC clocks.
55 * The MDC clock selection macros need to be defined for MDC clock rate
56 * of 12.5 MHz, corresponding to the following selection.
57 */
58#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
59#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
60#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
61#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
62#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
63#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
64#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
65#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
66
67/* AXI DMA Burst length supported */
68#define DMA_AXI_BLEN_4 (1 << 1)
69#define DMA_AXI_BLEN_8 (1 << 2)
70#define DMA_AXI_BLEN_16 (1 << 3)
71#define DMA_AXI_BLEN_32 (1 << 4)
72#define DMA_AXI_BLEN_64 (1 << 5)
73#define DMA_AXI_BLEN_128 (1 << 6)
74#define DMA_AXI_BLEN_256 (1 << 7)
75#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
76 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
77 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
78
79struct stmmac_priv;
80
81/* Platfrom data for platform device structure's platform_data field */
82
83struct stmmac_mdio_bus_data {
84 unsigned int phy_mask;
85 unsigned int has_xpcs;
86 unsigned int xpcs_an_inband;
87 int *irqs;
88 int probed_phy_irq;
89 bool needs_reset;
90};
91
92struct stmmac_dma_cfg {
93 int pbl;
94 int txpbl;
95 int rxpbl;
96 bool pblx8;
97 int fixed_burst;
98 int mixed_burst;
99 bool aal;
100 bool eame;
101 bool multi_msi_en;
102 bool dche;
103};
104
105#define AXI_BLEN 7
106struct stmmac_axi {
107 bool axi_lpi_en;
108 bool axi_xit_frm;
109 u32 axi_wr_osr_lmt;
110 u32 axi_rd_osr_lmt;
111 bool axi_kbbe;
112 u32 axi_blen[AXI_BLEN];
113 bool axi_fb;
114 bool axi_mb;
115 bool axi_rb;
116};
117
118#define EST_GCL 1024
119struct stmmac_est {
120 struct mutex lock;
121 int enable;
122 u32 btr_reserve[2];
123 u32 btr_offset[2];
124 u32 btr[2];
125 u32 ctr[2];
126 u32 ter;
127 u32 gcl_unaligned[EST_GCL];
128 u32 gcl[EST_GCL];
129 u32 gcl_size;
130};
131
132struct stmmac_rxq_cfg {
133 u8 mode_to_use;
134 u32 chan;
135 u8 pkt_route;
136 bool use_prio;
137 u32 prio;
138};
139
140struct stmmac_txq_cfg {
141 u32 weight;
142 bool coe_unsupported;
143 u8 mode_to_use;
144 /* Credit Base Shaper parameters */
145 u32 send_slope;
146 u32 idle_slope;
147 u32 high_credit;
148 u32 low_credit;
149 bool use_prio;
150 u32 prio;
151 int tbs_en;
152};
153
154/* FPE link state */
155enum stmmac_fpe_state {
156 FPE_STATE_OFF = 0,
157 FPE_STATE_CAPABLE = 1,
158 FPE_STATE_ENTERING_ON = 2,
159 FPE_STATE_ON = 3,
160};
161
162/* FPE link-partner hand-shaking mPacket type */
163enum stmmac_mpacket_type {
164 MPACKET_VERIFY = 0,
165 MPACKET_RESPONSE = 1,
166};
167
168enum stmmac_fpe_task_state_t {
169 __FPE_REMOVING,
170 __FPE_TASK_SCHED,
171};
172
173struct stmmac_fpe_cfg {
174 bool enable; /* FPE enable */
175 bool hs_enable; /* FPE handshake enable */
176 enum stmmac_fpe_state lp_fpe_state; /* Link Partner FPE state */
177 enum stmmac_fpe_state lo_fpe_state; /* Local station FPE state */
178 u32 fpe_csr; /* MAC_FPE_CTRL_STS reg cache */
179};
180
181struct stmmac_safety_feature_cfg {
182 u32 tsoee;
183 u32 mrxpee;
184 u32 mestee;
185 u32 mrxee;
186 u32 mtxee;
187 u32 epsi;
188 u32 edpp;
189 u32 prtyen;
190 u32 tmouten;
191};
192
193/* Addresses that may be customized by a platform */
194struct dwmac4_addrs {
195 u32 dma_chan;
196 u32 dma_chan_offset;
197 u32 mtl_chan;
198 u32 mtl_chan_offset;
199 u32 mtl_ets_ctrl;
200 u32 mtl_ets_ctrl_offset;
201 u32 mtl_txq_weight;
202 u32 mtl_txq_weight_offset;
203 u32 mtl_send_slp_cred;
204 u32 mtl_send_slp_cred_offset;
205 u32 mtl_high_cred;
206 u32 mtl_high_cred_offset;
207 u32 mtl_low_cred;
208 u32 mtl_low_cred_offset;
209};
210
211#define STMMAC_FLAG_HAS_INTEGRATED_PCS BIT(0)
212#define STMMAC_FLAG_SPH_DISABLE BIT(1)
213#define STMMAC_FLAG_USE_PHY_WOL BIT(2)
214#define STMMAC_FLAG_HAS_SUN8I BIT(3)
215#define STMMAC_FLAG_TSO_EN BIT(4)
216#define STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP BIT(5)
217#define STMMAC_FLAG_VLAN_FAIL_Q_EN BIT(6)
218#define STMMAC_FLAG_MULTI_MSI_EN BIT(7)
219#define STMMAC_FLAG_EXT_SNAPSHOT_EN BIT(8)
220#define STMMAC_FLAG_INT_SNAPSHOT_EN BIT(9)
221#define STMMAC_FLAG_RX_CLK_RUNS_IN_LPI BIT(10)
222#define STMMAC_FLAG_EN_TX_LPI_CLOCKGATING BIT(11)
223#define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY BIT(12)
224
225struct plat_stmmacenet_data {
226 int bus_id;
227 int phy_addr;
228 /* MAC ----- optional PCS ----- SerDes ----- optional PHY ----- Media
229 * ^ ^
230 * mac_interface phy_interface
231 *
232 * mac_interface is the MAC-side interface, which may be the same
233 * as phy_interface if there is no intervening PCS. If there is a
234 * PCS, then mac_interface describes the interface mode between the
235 * MAC and PCS, and phy_interface describes the interface mode
236 * between the PCS and PHY.
237 */
238 phy_interface_t mac_interface;
239 /* phy_interface is the PHY-side interface - the interface used by
240 * an attached PHY.
241 */
242 phy_interface_t phy_interface;
243 struct stmmac_mdio_bus_data *mdio_bus_data;
244 struct device_node *phy_node;
245 struct fwnode_handle *port_node;
246 struct device_node *mdio_node;
247 struct stmmac_dma_cfg *dma_cfg;
248 struct stmmac_est *est;
249 struct stmmac_fpe_cfg *fpe_cfg;
250 struct stmmac_safety_feature_cfg *safety_feat_cfg;
251 int clk_csr;
252 int has_gmac;
253 int enh_desc;
254 int tx_coe;
255 int rx_coe;
256 int bugged_jumbo;
257 int pmt;
258 int force_sf_dma_mode;
259 int force_thresh_dma_mode;
260 int riwt_off;
261 int max_speed;
262 int maxmtu;
263 int multicast_filter_bins;
264 int unicast_filter_entries;
265 int tx_fifo_size;
266 int rx_fifo_size;
267 u32 host_dma_width;
268 u32 rx_queues_to_use;
269 u32 tx_queues_to_use;
270 u8 rx_sched_algorithm;
271 u8 tx_sched_algorithm;
272 struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
273 struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
274 void (*fix_mac_speed)(void *priv, unsigned int speed, unsigned int mode);
275 int (*fix_soc_reset)(void *priv, void __iomem *ioaddr);
276 int (*serdes_powerup)(struct net_device *ndev, void *priv);
277 void (*serdes_powerdown)(struct net_device *ndev, void *priv);
278 void (*speed_mode_2500)(struct net_device *ndev, void *priv);
279 void (*ptp_clk_freq_config)(struct stmmac_priv *priv);
280 int (*init)(struct platform_device *pdev, void *priv);
281 void (*exit)(struct platform_device *pdev, void *priv);
282 struct mac_device_info *(*setup)(void *priv);
283 int (*clks_config)(void *priv, bool enabled);
284 int (*crosststamp)(ktime_t *device, struct system_counterval_t *system,
285 void *ctx);
286 void (*dump_debug_regs)(void *priv);
287 void *bsp_priv;
288 struct clk *stmmac_clk;
289 struct clk *pclk;
290 struct clk *clk_ptp_ref;
291 unsigned int clk_ptp_rate;
292 unsigned int clk_ref_rate;
293 unsigned int mult_fact_100ns;
294 s32 ptp_max_adj;
295 u32 cdc_error_adj;
296 struct reset_control *stmmac_rst;
297 struct reset_control *stmmac_ahb_rst;
298 struct stmmac_axi *axi;
299 int has_gmac4;
300 int rss_en;
301 int mac_port_sel_speed;
302 int has_xgmac;
303 u8 vlan_fail_q;
304 unsigned int eee_usecs_rate;
305 struct pci_dev *pdev;
306 int int_snapshot_num;
307 int msi_mac_vec;
308 int msi_wol_vec;
309 int msi_lpi_vec;
310 int msi_sfty_ce_vec;
311 int msi_sfty_ue_vec;
312 int msi_rx_base_vec;
313 int msi_tx_base_vec;
314 const struct dwmac4_addrs *dwmac4_addrs;
315 unsigned int flags;
316};
317#endif