Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * Copyright (C) 2019 Western Digital Corporation or its affiliates.
4 *
5 * Authors:
6 * Anup Patel <anup.patel@wdc.com>
7 */
8
9#ifndef __LINUX_KVM_RISCV_H
10#define __LINUX_KVM_RISCV_H
11
12#ifndef __ASSEMBLY__
13
14#include <linux/types.h>
15#include <asm/bitsperlong.h>
16#include <asm/ptrace.h>
17
18#define __KVM_HAVE_IRQ_LINE
19#define __KVM_HAVE_READONLY_MEM
20
21#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
22
23#define KVM_INTERRUPT_SET -1U
24#define KVM_INTERRUPT_UNSET -2U
25
26/* for KVM_GET_REGS and KVM_SET_REGS */
27struct kvm_regs {
28};
29
30/* for KVM_GET_FPU and KVM_SET_FPU */
31struct kvm_fpu {
32};
33
34/* KVM Debug exit structure */
35struct kvm_debug_exit_arch {
36};
37
38/* for KVM_SET_GUEST_DEBUG */
39struct kvm_guest_debug_arch {
40};
41
42/* definition of registers in kvm_run */
43struct kvm_sync_regs {
44};
45
46/* for KVM_GET_SREGS and KVM_SET_SREGS */
47struct kvm_sregs {
48};
49
50/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
51struct kvm_riscv_config {
52 unsigned long isa;
53 unsigned long zicbom_block_size;
54 unsigned long mvendorid;
55 unsigned long marchid;
56 unsigned long mimpid;
57 unsigned long zicboz_block_size;
58 unsigned long satp_mode;
59};
60
61/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
62struct kvm_riscv_core {
63 struct user_regs_struct regs;
64 unsigned long mode;
65};
66
67/* Possible privilege modes for kvm_riscv_core */
68#define KVM_RISCV_MODE_S 1
69#define KVM_RISCV_MODE_U 0
70
71/* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
72struct kvm_riscv_csr {
73 unsigned long sstatus;
74 unsigned long sie;
75 unsigned long stvec;
76 unsigned long sscratch;
77 unsigned long sepc;
78 unsigned long scause;
79 unsigned long stval;
80 unsigned long sip;
81 unsigned long satp;
82 unsigned long scounteren;
83 unsigned long senvcfg;
84};
85
86/* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
87struct kvm_riscv_aia_csr {
88 unsigned long siselect;
89 unsigned long iprio1;
90 unsigned long iprio2;
91 unsigned long sieh;
92 unsigned long siph;
93 unsigned long iprio1h;
94 unsigned long iprio2h;
95};
96
97/* Smstateen CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
98struct kvm_riscv_smstateen_csr {
99 unsigned long sstateen0;
100};
101
102/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
103struct kvm_riscv_timer {
104 __u64 frequency;
105 __u64 time;
106 __u64 compare;
107 __u64 state;
108};
109
110/*
111 * ISA extension IDs specific to KVM. This is not the same as the host ISA
112 * extension IDs as that is internal to the host and should not be exposed
113 * to the guest. This should always be contiguous to keep the mapping simple
114 * in KVM implementation.
115 */
116enum KVM_RISCV_ISA_EXT_ID {
117 KVM_RISCV_ISA_EXT_A = 0,
118 KVM_RISCV_ISA_EXT_C,
119 KVM_RISCV_ISA_EXT_D,
120 KVM_RISCV_ISA_EXT_F,
121 KVM_RISCV_ISA_EXT_H,
122 KVM_RISCV_ISA_EXT_I,
123 KVM_RISCV_ISA_EXT_M,
124 KVM_RISCV_ISA_EXT_SVPBMT,
125 KVM_RISCV_ISA_EXT_SSTC,
126 KVM_RISCV_ISA_EXT_SVINVAL,
127 KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
128 KVM_RISCV_ISA_EXT_ZICBOM,
129 KVM_RISCV_ISA_EXT_ZICBOZ,
130 KVM_RISCV_ISA_EXT_ZBB,
131 KVM_RISCV_ISA_EXT_SSAIA,
132 KVM_RISCV_ISA_EXT_V,
133 KVM_RISCV_ISA_EXT_SVNAPOT,
134 KVM_RISCV_ISA_EXT_ZBA,
135 KVM_RISCV_ISA_EXT_ZBS,
136 KVM_RISCV_ISA_EXT_ZICNTR,
137 KVM_RISCV_ISA_EXT_ZICSR,
138 KVM_RISCV_ISA_EXT_ZIFENCEI,
139 KVM_RISCV_ISA_EXT_ZIHPM,
140 KVM_RISCV_ISA_EXT_SMSTATEEN,
141 KVM_RISCV_ISA_EXT_ZICOND,
142 KVM_RISCV_ISA_EXT_ZBC,
143 KVM_RISCV_ISA_EXT_ZBKB,
144 KVM_RISCV_ISA_EXT_ZBKC,
145 KVM_RISCV_ISA_EXT_ZBKX,
146 KVM_RISCV_ISA_EXT_ZKND,
147 KVM_RISCV_ISA_EXT_ZKNE,
148 KVM_RISCV_ISA_EXT_ZKNH,
149 KVM_RISCV_ISA_EXT_ZKR,
150 KVM_RISCV_ISA_EXT_ZKSED,
151 KVM_RISCV_ISA_EXT_ZKSH,
152 KVM_RISCV_ISA_EXT_ZKT,
153 KVM_RISCV_ISA_EXT_ZVBB,
154 KVM_RISCV_ISA_EXT_ZVBC,
155 KVM_RISCV_ISA_EXT_ZVKB,
156 KVM_RISCV_ISA_EXT_ZVKG,
157 KVM_RISCV_ISA_EXT_ZVKNED,
158 KVM_RISCV_ISA_EXT_ZVKNHA,
159 KVM_RISCV_ISA_EXT_ZVKNHB,
160 KVM_RISCV_ISA_EXT_ZVKSED,
161 KVM_RISCV_ISA_EXT_ZVKSH,
162 KVM_RISCV_ISA_EXT_ZVKT,
163 KVM_RISCV_ISA_EXT_ZFH,
164 KVM_RISCV_ISA_EXT_ZFHMIN,
165 KVM_RISCV_ISA_EXT_ZIHINTNTL,
166 KVM_RISCV_ISA_EXT_ZVFH,
167 KVM_RISCV_ISA_EXT_ZVFHMIN,
168 KVM_RISCV_ISA_EXT_ZFA,
169 KVM_RISCV_ISA_EXT_MAX,
170};
171
172/*
173 * SBI extension IDs specific to KVM. This is not the same as the SBI
174 * extension IDs defined by the RISC-V SBI specification.
175 */
176enum KVM_RISCV_SBI_EXT_ID {
177 KVM_RISCV_SBI_EXT_V01 = 0,
178 KVM_RISCV_SBI_EXT_TIME,
179 KVM_RISCV_SBI_EXT_IPI,
180 KVM_RISCV_SBI_EXT_RFENCE,
181 KVM_RISCV_SBI_EXT_SRST,
182 KVM_RISCV_SBI_EXT_HSM,
183 KVM_RISCV_SBI_EXT_PMU,
184 KVM_RISCV_SBI_EXT_EXPERIMENTAL,
185 KVM_RISCV_SBI_EXT_VENDOR,
186 KVM_RISCV_SBI_EXT_DBCN,
187 KVM_RISCV_SBI_EXT_STA,
188 KVM_RISCV_SBI_EXT_MAX,
189};
190
191/* SBI STA extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
192struct kvm_riscv_sbi_sta {
193 unsigned long shmem_lo;
194 unsigned long shmem_hi;
195};
196
197/* Possible states for kvm_riscv_timer */
198#define KVM_RISCV_TIMER_STATE_OFF 0
199#define KVM_RISCV_TIMER_STATE_ON 1
200
201#define KVM_REG_SIZE(id) \
202 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
203
204/* If you need to interpret the index values, here is the key: */
205#define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000
206#define KVM_REG_RISCV_TYPE_SHIFT 24
207#define KVM_REG_RISCV_SUBTYPE_MASK 0x0000000000FF0000
208#define KVM_REG_RISCV_SUBTYPE_SHIFT 16
209
210/* Config registers are mapped as type 1 */
211#define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
212#define KVM_REG_RISCV_CONFIG_REG(name) \
213 (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
214
215/* Core registers are mapped as type 2 */
216#define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
217#define KVM_REG_RISCV_CORE_REG(name) \
218 (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
219
220/* Control and status registers are mapped as type 3 */
221#define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
222#define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
223#define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
224#define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
225#define KVM_REG_RISCV_CSR_REG(name) \
226 (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
227#define KVM_REG_RISCV_CSR_AIA_REG(name) \
228 (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long))
229#define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) \
230 (offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long))
231
232/* Timer registers are mapped as type 4 */
233#define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
234#define KVM_REG_RISCV_TIMER_REG(name) \
235 (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
236
237/* F extension registers are mapped as type 5 */
238#define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT)
239#define KVM_REG_RISCV_FP_F_REG(name) \
240 (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
241
242/* D extension registers are mapped as type 6 */
243#define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
244#define KVM_REG_RISCV_FP_D_REG(name) \
245 (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
246
247/* ISA Extension registers are mapped as type 7 */
248#define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
249#define KVM_REG_RISCV_ISA_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
250#define KVM_REG_RISCV_ISA_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
251#define KVM_REG_RISCV_ISA_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
252#define KVM_REG_RISCV_ISA_MULTI_REG(__ext_id) \
253 ((__ext_id) / __BITS_PER_LONG)
254#define KVM_REG_RISCV_ISA_MULTI_MASK(__ext_id) \
255 (1UL << ((__ext_id) % __BITS_PER_LONG))
256#define KVM_REG_RISCV_ISA_MULTI_REG_LAST \
257 KVM_REG_RISCV_ISA_MULTI_REG(KVM_RISCV_ISA_EXT_MAX - 1)
258
259/* SBI extension registers are mapped as type 8 */
260#define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT)
261#define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
262#define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
263#define KVM_REG_RISCV_SBI_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
264#define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) \
265 ((__ext_id) / __BITS_PER_LONG)
266#define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) \
267 (1UL << ((__ext_id) % __BITS_PER_LONG))
268#define KVM_REG_RISCV_SBI_MULTI_REG_LAST \
269 KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1)
270
271/* V extension registers are mapped as type 9 */
272#define KVM_REG_RISCV_VECTOR (0x09 << KVM_REG_RISCV_TYPE_SHIFT)
273#define KVM_REG_RISCV_VECTOR_CSR_REG(name) \
274 (offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long))
275#define KVM_REG_RISCV_VECTOR_REG(n) \
276 ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long))
277
278/* Registers for specific SBI extensions are mapped as type 10 */
279#define KVM_REG_RISCV_SBI_STATE (0x0a << KVM_REG_RISCV_TYPE_SHIFT)
280#define KVM_REG_RISCV_SBI_STA (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
281#define KVM_REG_RISCV_SBI_STA_REG(name) \
282 (offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long))
283
284/* Device Control API: RISC-V AIA */
285#define KVM_DEV_RISCV_APLIC_ALIGN 0x1000
286#define KVM_DEV_RISCV_APLIC_SIZE 0x4000
287#define KVM_DEV_RISCV_APLIC_MAX_HARTS 0x4000
288#define KVM_DEV_RISCV_IMSIC_ALIGN 0x1000
289#define KVM_DEV_RISCV_IMSIC_SIZE 0x1000
290
291#define KVM_DEV_RISCV_AIA_GRP_CONFIG 0
292#define KVM_DEV_RISCV_AIA_CONFIG_MODE 0
293#define KVM_DEV_RISCV_AIA_CONFIG_IDS 1
294#define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2
295#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3
296#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4
297#define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5
298#define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6
299
300/*
301 * Modes of RISC-V AIA device:
302 * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC
303 * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files
304 * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever
305 * available otherwise fallback to trap-n-emulation
306 */
307#define KVM_DEV_RISCV_AIA_MODE_EMUL 0
308#define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1
309#define KVM_DEV_RISCV_AIA_MODE_AUTO 2
310
311#define KVM_DEV_RISCV_AIA_IDS_MIN 63
312#define KVM_DEV_RISCV_AIA_IDS_MAX 2048
313#define KVM_DEV_RISCV_AIA_SRCS_MAX 1024
314#define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8
315#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24
316#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56
317#define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16
318#define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8
319
320#define KVM_DEV_RISCV_AIA_GRP_ADDR 1
321#define KVM_DEV_RISCV_AIA_ADDR_APLIC 0
322#define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu))
323#define KVM_DEV_RISCV_AIA_ADDR_MAX \
324 (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS)
325
326#define KVM_DEV_RISCV_AIA_GRP_CTRL 2
327#define KVM_DEV_RISCV_AIA_CTRL_INIT 0
328
329/*
330 * The device attribute type contains the memory mapped offset of the
331 * APLIC register (range 0x0000-0x3FFF) and it must be 4-byte aligned.
332 */
333#define KVM_DEV_RISCV_AIA_GRP_APLIC 3
334
335/*
336 * The lower 12-bits of the device attribute type contains the iselect
337 * value of the IMSIC register (range 0x70-0xFF) whereas the higher order
338 * bits contains the VCPU id.
339 */
340#define KVM_DEV_RISCV_AIA_GRP_IMSIC 4
341#define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS 12
342#define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK \
343 ((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1)
344#define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel) \
345 (((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \
346 ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK))
347#define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr) \
348 ((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)
349#define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr) \
350 ((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS)
351
352/* One single KVM irqchip, ie. the AIA */
353#define KVM_NR_IRQCHIPS 1
354
355#endif
356
357#endif /* __LINUX_KVM_RISCV_H */