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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
4 * - BMI088
5 * - BMI085
6 * - BMI090L
7 *
8 * Copyright (c) 2018-2021, Topic Embedded Products
9 */
10
11#include <linux/bitfield.h>
12#include <linux/delay.h>
13#include <linux/iio/iio.h>
14#include <linux/iio/sysfs.h>
15#include <linux/interrupt.h>
16#include <linux/module.h>
17#include <linux/pm.h>
18#include <linux/pm_runtime.h>
19#include <linux/regmap.h>
20#include <linux/slab.h>
21#include <asm/unaligned.h>
22
23#include "bmi088-accel.h"
24
25#define BMI088_ACCEL_REG_CHIP_ID 0x00
26#define BMI088_ACCEL_REG_ERROR 0x02
27
28#define BMI088_ACCEL_REG_INT_STATUS 0x1D
29#define BMI088_ACCEL_INT_STATUS_BIT_DRDY BIT(7)
30
31#define BMI088_ACCEL_REG_RESET 0x7E
32#define BMI088_ACCEL_RESET_VAL 0xB6
33
34#define BMI088_ACCEL_REG_PWR_CTRL 0x7D
35#define BMI088_ACCEL_REG_PWR_CONF 0x7C
36
37#define BMI088_ACCEL_REG_INT_MAP_DATA 0x58
38#define BMI088_ACCEL_INT_MAP_DATA_BIT_INT1_DRDY BIT(2)
39#define BMI088_ACCEL_INT_MAP_DATA_BIT_INT2_FWM BIT(5)
40
41#define BMI088_ACCEL_REG_INT1_IO_CONF 0x53
42#define BMI088_ACCEL_INT1_IO_CONF_BIT_ENABLE_OUT BIT(3)
43#define BMI088_ACCEL_INT1_IO_CONF_BIT_LVL BIT(1)
44
45#define BMI088_ACCEL_REG_INT2_IO_CONF 0x54
46#define BMI088_ACCEL_INT2_IO_CONF_BIT_ENABLE_OUT BIT(3)
47#define BMI088_ACCEL_INT2_IO_CONF_BIT_LVL BIT(1)
48
49#define BMI088_ACCEL_REG_ACC_CONF 0x40
50#define BMI088_ACCEL_MODE_ODR_MASK 0x0f
51
52#define BMI088_ACCEL_REG_ACC_RANGE 0x41
53#define BMI088_ACCEL_RANGE_3G 0x00
54#define BMI088_ACCEL_RANGE_6G 0x01
55#define BMI088_ACCEL_RANGE_12G 0x02
56#define BMI088_ACCEL_RANGE_24G 0x03
57
58#define BMI088_ACCEL_REG_TEMP 0x22
59#define BMI088_ACCEL_REG_TEMP_SHIFT 5
60#define BMI088_ACCEL_TEMP_UNIT 125
61#define BMI088_ACCEL_TEMP_OFFSET 23000
62
63#define BMI088_ACCEL_REG_XOUT_L 0x12
64#define BMI088_ACCEL_AXIS_TO_REG(axis) \
65 (BMI088_ACCEL_REG_XOUT_L + (axis * 2))
66
67#define BMI088_ACCEL_MAX_STARTUP_TIME_US 1000
68#define BMI088_AUTO_SUSPEND_DELAY_MS 2000
69
70#define BMI088_ACCEL_REG_FIFO_STATUS 0x0E
71#define BMI088_ACCEL_REG_FIFO_CONFIG0 0x48
72#define BMI088_ACCEL_REG_FIFO_CONFIG1 0x49
73#define BMI088_ACCEL_REG_FIFO_DATA 0x3F
74#define BMI088_ACCEL_FIFO_LENGTH 100
75
76#define BMI088_ACCEL_FIFO_MODE_FIFO 0x40
77#define BMI088_ACCEL_FIFO_MODE_STREAM 0x80
78
79#define BMIO088_ACCEL_ACC_RANGE_MSK GENMASK(1, 0)
80
81enum bmi088_accel_axis {
82 AXIS_X,
83 AXIS_Y,
84 AXIS_Z,
85};
86
87static const int bmi088_sample_freqs[] = {
88 12, 500000,
89 25, 0,
90 50, 0,
91 100, 0,
92 200, 0,
93 400, 0,
94 800, 0,
95 1600, 0,
96};
97
98/* Available OSR (over sampling rate) sets the 3dB cut-off frequency */
99enum bmi088_osr_modes {
100 BMI088_ACCEL_MODE_OSR_NORMAL = 0xA,
101 BMI088_ACCEL_MODE_OSR_2 = 0x9,
102 BMI088_ACCEL_MODE_OSR_4 = 0x8,
103};
104
105/* Available ODR (output data rates) in Hz */
106enum bmi088_odr_modes {
107 BMI088_ACCEL_MODE_ODR_12_5 = 0x5,
108 BMI088_ACCEL_MODE_ODR_25 = 0x6,
109 BMI088_ACCEL_MODE_ODR_50 = 0x7,
110 BMI088_ACCEL_MODE_ODR_100 = 0x8,
111 BMI088_ACCEL_MODE_ODR_200 = 0x9,
112 BMI088_ACCEL_MODE_ODR_400 = 0xa,
113 BMI088_ACCEL_MODE_ODR_800 = 0xb,
114 BMI088_ACCEL_MODE_ODR_1600 = 0xc,
115};
116
117struct bmi088_scale_info {
118 int scale;
119 u8 reg_range;
120};
121
122struct bmi088_accel_chip_info {
123 const char *name;
124 u8 chip_id;
125 const struct iio_chan_spec *channels;
126 int num_channels;
127 const int scale_table[4][2];
128};
129
130struct bmi088_accel_data {
131 struct regmap *regmap;
132 const struct bmi088_accel_chip_info *chip_info;
133 u8 buffer[2] __aligned(IIO_DMA_MINALIGN); /* shared DMA safe buffer */
134};
135
136static const struct regmap_range bmi088_volatile_ranges[] = {
137 /* All registers below 0x40 are volatile, except the CHIP ID. */
138 regmap_reg_range(BMI088_ACCEL_REG_ERROR, 0x3f),
139 /* Mark the RESET as volatile too, it is self-clearing */
140 regmap_reg_range(BMI088_ACCEL_REG_RESET, BMI088_ACCEL_REG_RESET),
141};
142
143static const struct regmap_access_table bmi088_volatile_table = {
144 .yes_ranges = bmi088_volatile_ranges,
145 .n_yes_ranges = ARRAY_SIZE(bmi088_volatile_ranges),
146};
147
148const struct regmap_config bmi088_regmap_conf = {
149 .reg_bits = 8,
150 .val_bits = 8,
151 .max_register = 0x7E,
152 .volatile_table = &bmi088_volatile_table,
153 .cache_type = REGCACHE_RBTREE,
154};
155EXPORT_SYMBOL_NS_GPL(bmi088_regmap_conf, IIO_BMI088);
156
157static int bmi088_accel_power_up(struct bmi088_accel_data *data)
158{
159 int ret;
160
161 /* Enable accelerometer and temperature sensor */
162 ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CTRL, 0x4);
163 if (ret)
164 return ret;
165
166 /* Datasheet recommends to wait at least 5ms before communication */
167 usleep_range(5000, 6000);
168
169 /* Disable suspend mode */
170 ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CONF, 0x0);
171 if (ret)
172 return ret;
173
174 /* Recommended at least 1ms before further communication */
175 usleep_range(1000, 1200);
176
177 return 0;
178}
179
180static int bmi088_accel_power_down(struct bmi088_accel_data *data)
181{
182 int ret;
183
184 /* Enable suspend mode */
185 ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CONF, 0x3);
186 if (ret)
187 return ret;
188
189 /* Recommended at least 1ms before further communication */
190 usleep_range(1000, 1200);
191
192 /* Disable accelerometer and temperature sensor */
193 ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CTRL, 0x0);
194 if (ret)
195 return ret;
196
197 /* Datasheet recommends to wait at least 5ms before communication */
198 usleep_range(5000, 6000);
199
200 return 0;
201}
202
203static int bmi088_accel_get_sample_freq(struct bmi088_accel_data *data,
204 int *val, int *val2)
205{
206 unsigned int value;
207 int ret;
208
209 ret = regmap_read(data->regmap, BMI088_ACCEL_REG_ACC_CONF,
210 &value);
211 if (ret)
212 return ret;
213
214 value &= BMI088_ACCEL_MODE_ODR_MASK;
215 value -= BMI088_ACCEL_MODE_ODR_12_5;
216 value <<= 1;
217
218 if (value >= ARRAY_SIZE(bmi088_sample_freqs) - 1)
219 return -EINVAL;
220
221 *val = bmi088_sample_freqs[value];
222 *val2 = bmi088_sample_freqs[value + 1];
223
224 return IIO_VAL_INT_PLUS_MICRO;
225}
226
227static int bmi088_accel_set_sample_freq(struct bmi088_accel_data *data, int val)
228{
229 unsigned int regval;
230 int index = 0;
231
232 while (index < ARRAY_SIZE(bmi088_sample_freqs) &&
233 bmi088_sample_freqs[index] != val)
234 index += 2;
235
236 if (index >= ARRAY_SIZE(bmi088_sample_freqs))
237 return -EINVAL;
238
239 regval = (index >> 1) + BMI088_ACCEL_MODE_ODR_12_5;
240
241 return regmap_update_bits(data->regmap, BMI088_ACCEL_REG_ACC_CONF,
242 BMI088_ACCEL_MODE_ODR_MASK, regval);
243}
244
245static int bmi088_accel_set_scale(struct bmi088_accel_data *data, int val, int val2)
246{
247 unsigned int i;
248
249 for (i = 0; i < 4; i++)
250 if (val == data->chip_info->scale_table[i][0] &&
251 val2 == data->chip_info->scale_table[i][1])
252 break;
253
254 if (i == 4)
255 return -EINVAL;
256
257 return regmap_write(data->regmap, BMI088_ACCEL_REG_ACC_RANGE, i);
258}
259
260static int bmi088_accel_get_temp(struct bmi088_accel_data *data, int *val)
261{
262 int ret;
263 s16 temp;
264
265 ret = regmap_bulk_read(data->regmap, BMI088_ACCEL_REG_TEMP,
266 &data->buffer, sizeof(__be16));
267 if (ret)
268 return ret;
269
270 /* data->buffer is cacheline aligned */
271 temp = be16_to_cpu(*(__be16 *)data->buffer);
272
273 *val = temp >> BMI088_ACCEL_REG_TEMP_SHIFT;
274
275 return IIO_VAL_INT;
276}
277
278static int bmi088_accel_get_axis(struct bmi088_accel_data *data,
279 struct iio_chan_spec const *chan,
280 int *val)
281{
282 int ret;
283 s16 raw_val;
284
285 ret = regmap_bulk_read(data->regmap,
286 BMI088_ACCEL_AXIS_TO_REG(chan->scan_index),
287 data->buffer, sizeof(__le16));
288 if (ret)
289 return ret;
290
291 raw_val = le16_to_cpu(*(__le16 *)data->buffer);
292 *val = raw_val;
293
294 return IIO_VAL_INT;
295}
296
297static int bmi088_accel_read_raw(struct iio_dev *indio_dev,
298 struct iio_chan_spec const *chan,
299 int *val, int *val2, long mask)
300{
301 struct bmi088_accel_data *data = iio_priv(indio_dev);
302 struct device *dev = regmap_get_device(data->regmap);
303 int ret;
304 int reg;
305
306 switch (mask) {
307 case IIO_CHAN_INFO_RAW:
308 switch (chan->type) {
309 case IIO_TEMP:
310 ret = pm_runtime_resume_and_get(dev);
311 if (ret)
312 return ret;
313
314 ret = bmi088_accel_get_temp(data, val);
315 goto out_read_raw_pm_put;
316 case IIO_ACCEL:
317 ret = pm_runtime_resume_and_get(dev);
318 if (ret)
319 return ret;
320
321 ret = iio_device_claim_direct_mode(indio_dev);
322 if (ret)
323 goto out_read_raw_pm_put;
324
325 ret = bmi088_accel_get_axis(data, chan, val);
326 iio_device_release_direct_mode(indio_dev);
327 if (!ret)
328 ret = IIO_VAL_INT;
329
330 goto out_read_raw_pm_put;
331 default:
332 return -EINVAL;
333 }
334 case IIO_CHAN_INFO_OFFSET:
335 switch (chan->type) {
336 case IIO_TEMP:
337 /* Offset applies before scale */
338 *val = BMI088_ACCEL_TEMP_OFFSET/BMI088_ACCEL_TEMP_UNIT;
339 return IIO_VAL_INT;
340 default:
341 return -EINVAL;
342 }
343 case IIO_CHAN_INFO_SCALE:
344 switch (chan->type) {
345 case IIO_TEMP:
346 /* 0.125 degrees per LSB */
347 *val = BMI088_ACCEL_TEMP_UNIT;
348 return IIO_VAL_INT;
349 case IIO_ACCEL:
350 ret = pm_runtime_resume_and_get(dev);
351 if (ret)
352 return ret;
353
354 ret = regmap_read(data->regmap,
355 BMI088_ACCEL_REG_ACC_RANGE, ®);
356 if (ret)
357 goto out_read_raw_pm_put;
358
359 reg = FIELD_GET(BMIO088_ACCEL_ACC_RANGE_MSK, reg);
360 *val = data->chip_info->scale_table[reg][0];
361 *val2 = data->chip_info->scale_table[reg][1];
362 ret = IIO_VAL_INT_PLUS_MICRO;
363
364 goto out_read_raw_pm_put;
365 default:
366 return -EINVAL;
367 }
368 case IIO_CHAN_INFO_SAMP_FREQ:
369 ret = pm_runtime_resume_and_get(dev);
370 if (ret)
371 return ret;
372
373 ret = bmi088_accel_get_sample_freq(data, val, val2);
374 goto out_read_raw_pm_put;
375 default:
376 break;
377 }
378
379 return -EINVAL;
380
381out_read_raw_pm_put:
382 pm_runtime_mark_last_busy(dev);
383 pm_runtime_put_autosuspend(dev);
384
385 return ret;
386}
387
388static int bmi088_accel_read_avail(struct iio_dev *indio_dev,
389 struct iio_chan_spec const *chan,
390 const int **vals, int *type, int *length,
391 long mask)
392{
393 struct bmi088_accel_data *data = iio_priv(indio_dev);
394
395 switch (mask) {
396 case IIO_CHAN_INFO_SCALE:
397 *vals = (const int *)data->chip_info->scale_table;
398 *length = 8;
399 *type = IIO_VAL_INT_PLUS_MICRO;
400 return IIO_AVAIL_LIST;
401 case IIO_CHAN_INFO_SAMP_FREQ:
402 *type = IIO_VAL_INT_PLUS_MICRO;
403 *vals = bmi088_sample_freqs;
404 *length = ARRAY_SIZE(bmi088_sample_freqs);
405 return IIO_AVAIL_LIST;
406 default:
407 return -EINVAL;
408 }
409}
410
411static int bmi088_accel_write_raw(struct iio_dev *indio_dev,
412 struct iio_chan_spec const *chan,
413 int val, int val2, long mask)
414{
415 struct bmi088_accel_data *data = iio_priv(indio_dev);
416 struct device *dev = regmap_get_device(data->regmap);
417 int ret;
418
419 switch (mask) {
420 case IIO_CHAN_INFO_SCALE:
421 ret = pm_runtime_resume_and_get(dev);
422 if (ret)
423 return ret;
424
425 ret = bmi088_accel_set_scale(data, val, val2);
426 pm_runtime_mark_last_busy(dev);
427 pm_runtime_put_autosuspend(dev);
428 return ret;
429 case IIO_CHAN_INFO_SAMP_FREQ:
430 ret = pm_runtime_resume_and_get(dev);
431 if (ret)
432 return ret;
433
434 ret = bmi088_accel_set_sample_freq(data, val);
435 pm_runtime_mark_last_busy(dev);
436 pm_runtime_put_autosuspend(dev);
437 return ret;
438 default:
439 return -EINVAL;
440 }
441}
442
443#define BMI088_ACCEL_CHANNEL(_axis) { \
444 .type = IIO_ACCEL, \
445 .modified = 1, \
446 .channel2 = IIO_MOD_##_axis, \
447 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
448 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
449 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
450 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
451 BIT(IIO_CHAN_INFO_SCALE), \
452 .scan_index = AXIS_##_axis, \
453}
454
455static const struct iio_chan_spec bmi088_accel_channels[] = {
456 {
457 .type = IIO_TEMP,
458 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
459 BIT(IIO_CHAN_INFO_SCALE) |
460 BIT(IIO_CHAN_INFO_OFFSET),
461 .scan_index = -1,
462 },
463 BMI088_ACCEL_CHANNEL(X),
464 BMI088_ACCEL_CHANNEL(Y),
465 BMI088_ACCEL_CHANNEL(Z),
466 IIO_CHAN_SOFT_TIMESTAMP(3),
467};
468
469static const struct bmi088_accel_chip_info bmi088_accel_chip_info_tbl[] = {
470 [BOSCH_BMI085] = {
471 .name = "bmi085-accel",
472 .chip_id = 0x1F,
473 .channels = bmi088_accel_channels,
474 .num_channels = ARRAY_SIZE(bmi088_accel_channels),
475 .scale_table = {{0, 598}, {0, 1196}, {0, 2393}, {0, 4785}},
476 },
477 [BOSCH_BMI088] = {
478 .name = "bmi088-accel",
479 .chip_id = 0x1E,
480 .channels = bmi088_accel_channels,
481 .num_channels = ARRAY_SIZE(bmi088_accel_channels),
482 .scale_table = {{0, 897}, {0, 1794}, {0, 3589}, {0, 7178}},
483 },
484 [BOSCH_BMI090L] = {
485 .name = "bmi090l-accel",
486 .chip_id = 0x1A,
487 .channels = bmi088_accel_channels,
488 .num_channels = ARRAY_SIZE(bmi088_accel_channels),
489 .scale_table = {{0, 897}, {0, 1794}, {0, 3589}, {0, 7178}},
490 },
491};
492
493static const struct iio_info bmi088_accel_info = {
494 .read_raw = bmi088_accel_read_raw,
495 .write_raw = bmi088_accel_write_raw,
496 .read_avail = bmi088_accel_read_avail,
497};
498
499static const unsigned long bmi088_accel_scan_masks[] = {
500 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
501 0
502};
503
504static int bmi088_accel_chip_init(struct bmi088_accel_data *data, enum bmi_device_type type)
505{
506 struct device *dev = regmap_get_device(data->regmap);
507 int ret, i;
508 unsigned int val;
509
510 if (type >= BOSCH_UNKNOWN)
511 return -ENODEV;
512
513 /* Do a dummy read to enable SPI interface, won't harm I2C */
514 regmap_read(data->regmap, BMI088_ACCEL_REG_INT_STATUS, &val);
515
516 /*
517 * Reset chip to get it in a known good state. A delay of 1ms after
518 * reset is required according to the data sheet
519 */
520 ret = regmap_write(data->regmap, BMI088_ACCEL_REG_RESET,
521 BMI088_ACCEL_RESET_VAL);
522 if (ret)
523 return ret;
524
525 usleep_range(1000, 2000);
526
527 /* Do a dummy read again after a reset to enable the SPI interface */
528 regmap_read(data->regmap, BMI088_ACCEL_REG_INT_STATUS, &val);
529
530 /* Read chip ID */
531 ret = regmap_read(data->regmap, BMI088_ACCEL_REG_CHIP_ID, &val);
532 if (ret) {
533 dev_err(dev, "Error: Reading chip id\n");
534 return ret;
535 }
536
537 /* Validate chip ID */
538 for (i = 0; i < ARRAY_SIZE(bmi088_accel_chip_info_tbl); i++)
539 if (bmi088_accel_chip_info_tbl[i].chip_id == val)
540 break;
541
542 if (i == ARRAY_SIZE(bmi088_accel_chip_info_tbl))
543 data->chip_info = &bmi088_accel_chip_info_tbl[type];
544 else
545 data->chip_info = &bmi088_accel_chip_info_tbl[i];
546
547 if (i != type)
548 dev_warn(dev, "unexpected chip id 0x%X\n", val);
549
550 return 0;
551}
552
553int bmi088_accel_core_probe(struct device *dev, struct regmap *regmap,
554 int irq, enum bmi_device_type type)
555{
556 struct bmi088_accel_data *data;
557 struct iio_dev *indio_dev;
558 int ret;
559
560 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
561 if (!indio_dev)
562 return -ENOMEM;
563
564 data = iio_priv(indio_dev);
565 dev_set_drvdata(dev, indio_dev);
566
567 data->regmap = regmap;
568
569 ret = bmi088_accel_chip_init(data, type);
570 if (ret)
571 return ret;
572
573 indio_dev->channels = data->chip_info->channels;
574 indio_dev->num_channels = data->chip_info->num_channels;
575 indio_dev->name = data->chip_info->name;
576 indio_dev->available_scan_masks = bmi088_accel_scan_masks;
577 indio_dev->modes = INDIO_DIRECT_MODE;
578 indio_dev->info = &bmi088_accel_info;
579
580 /* Enable runtime PM */
581 pm_runtime_get_noresume(dev);
582 pm_runtime_set_suspended(dev);
583 pm_runtime_enable(dev);
584 /* We need ~6ms to startup, so set the delay to 6 seconds */
585 pm_runtime_set_autosuspend_delay(dev, 6000);
586 pm_runtime_use_autosuspend(dev);
587 pm_runtime_put(dev);
588
589 ret = iio_device_register(indio_dev);
590 if (ret)
591 dev_err(dev, "Unable to register iio device\n");
592
593 return ret;
594}
595EXPORT_SYMBOL_NS_GPL(bmi088_accel_core_probe, IIO_BMI088);
596
597
598void bmi088_accel_core_remove(struct device *dev)
599{
600 struct iio_dev *indio_dev = dev_get_drvdata(dev);
601 struct bmi088_accel_data *data = iio_priv(indio_dev);
602
603 iio_device_unregister(indio_dev);
604
605 pm_runtime_disable(dev);
606 pm_runtime_set_suspended(dev);
607 bmi088_accel_power_down(data);
608}
609EXPORT_SYMBOL_NS_GPL(bmi088_accel_core_remove, IIO_BMI088);
610
611static int bmi088_accel_runtime_suspend(struct device *dev)
612{
613 struct iio_dev *indio_dev = dev_get_drvdata(dev);
614 struct bmi088_accel_data *data = iio_priv(indio_dev);
615
616 return bmi088_accel_power_down(data);
617}
618
619static int bmi088_accel_runtime_resume(struct device *dev)
620{
621 struct iio_dev *indio_dev = dev_get_drvdata(dev);
622 struct bmi088_accel_data *data = iio_priv(indio_dev);
623
624 return bmi088_accel_power_up(data);
625}
626
627EXPORT_NS_GPL_RUNTIME_DEV_PM_OPS(bmi088_accel_pm_ops,
628 bmi088_accel_runtime_suspend,
629 bmi088_accel_runtime_resume, NULL,
630 IIO_BMI088);
631
632MODULE_AUTHOR("Niek van Agt <niek.van.agt@topicproducts.com>");
633MODULE_LICENSE("GPL v2");
634MODULE_DESCRIPTION("BMI088 accelerometer driver (core)");