tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#ifdef pr_fmt
32#undef pr_fmt
33#endif
34
35#define pr_fmt(fmt) "amdgpu: " fmt
36
37#ifdef dev_fmt
38#undef dev_fmt
39#endif
40
41#define dev_fmt(fmt) "amdgpu: " fmt
42
43#include "amdgpu_ctx.h"
44
45#include <linux/atomic.h>
46#include <linux/wait.h>
47#include <linux/list.h>
48#include <linux/kref.h>
49#include <linux/rbtree.h>
50#include <linux/hashtable.h>
51#include <linux/dma-fence.h>
52#include <linux/pci.h>
53
54#include <drm/ttm/ttm_bo.h>
55#include <drm/ttm/ttm_placement.h>
56
57#include <drm/amdgpu_drm.h>
58#include <drm/drm_gem.h>
59#include <drm/drm_ioctl.h>
60
61#include <kgd_kfd_interface.h>
62#include "dm_pp_interface.h"
63#include "kgd_pp_interface.h"
64
65#include "amd_shared.h"
66#include "amdgpu_mode.h"
67#include "amdgpu_ih.h"
68#include "amdgpu_irq.h"
69#include "amdgpu_ucode.h"
70#include "amdgpu_ttm.h"
71#include "amdgpu_psp.h"
72#include "amdgpu_gds.h"
73#include "amdgpu_sync.h"
74#include "amdgpu_ring.h"
75#include "amdgpu_vm.h"
76#include "amdgpu_dpm.h"
77#include "amdgpu_acp.h"
78#include "amdgpu_uvd.h"
79#include "amdgpu_vce.h"
80#include "amdgpu_vcn.h"
81#include "amdgpu_jpeg.h"
82#include "amdgpu_vpe.h"
83#include "amdgpu_umsch_mm.h"
84#include "amdgpu_gmc.h"
85#include "amdgpu_gfx.h"
86#include "amdgpu_sdma.h"
87#include "amdgpu_lsdma.h"
88#include "amdgpu_nbio.h"
89#include "amdgpu_hdp.h"
90#include "amdgpu_dm.h"
91#include "amdgpu_virt.h"
92#include "amdgpu_csa.h"
93#include "amdgpu_mes_ctx.h"
94#include "amdgpu_gart.h"
95#include "amdgpu_debugfs.h"
96#include "amdgpu_job.h"
97#include "amdgpu_bo_list.h"
98#include "amdgpu_gem.h"
99#include "amdgpu_doorbell.h"
100#include "amdgpu_amdkfd.h"
101#include "amdgpu_discovery.h"
102#include "amdgpu_mes.h"
103#include "amdgpu_umc.h"
104#include "amdgpu_mmhub.h"
105#include "amdgpu_gfxhub.h"
106#include "amdgpu_df.h"
107#include "amdgpu_smuio.h"
108#include "amdgpu_fdinfo.h"
109#include "amdgpu_mca.h"
110#include "amdgpu_ras.h"
111#include "amdgpu_xcp.h"
112#include "amdgpu_seq64.h"
113#include "amdgpu_reg_state.h"
114
115#define MAX_GPU_INSTANCE 64
116
117struct amdgpu_gpu_instance
118{
119 struct amdgpu_device *adev;
120 int mgpu_fan_enabled;
121};
122
123struct amdgpu_mgpu_info
124{
125 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
126 struct mutex mutex;
127 uint32_t num_gpu;
128 uint32_t num_dgpu;
129 uint32_t num_apu;
130
131 /* delayed reset_func for XGMI configuration if necessary */
132 struct delayed_work delayed_reset_work;
133 bool pending_reset;
134};
135
136enum amdgpu_ss {
137 AMDGPU_SS_DRV_LOAD,
138 AMDGPU_SS_DEV_D0,
139 AMDGPU_SS_DEV_D3,
140 AMDGPU_SS_DRV_UNLOAD
141};
142
143struct amdgpu_watchdog_timer
144{
145 bool timeout_fatal_disable;
146 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
147};
148
149#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
150
151/*
152 * Modules parameters.
153 */
154extern int amdgpu_modeset;
155extern unsigned int amdgpu_vram_limit;
156extern int amdgpu_vis_vram_limit;
157extern int amdgpu_gart_size;
158extern int amdgpu_gtt_size;
159extern int amdgpu_moverate;
160extern int amdgpu_audio;
161extern int amdgpu_disp_priority;
162extern int amdgpu_hw_i2c;
163extern int amdgpu_pcie_gen2;
164extern int amdgpu_msi;
165extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
166extern int amdgpu_dpm;
167extern int amdgpu_fw_load_type;
168extern int amdgpu_aspm;
169extern int amdgpu_runtime_pm;
170extern uint amdgpu_ip_block_mask;
171extern int amdgpu_bapm;
172extern int amdgpu_deep_color;
173extern int amdgpu_vm_size;
174extern int amdgpu_vm_block_size;
175extern int amdgpu_vm_fragment_size;
176extern int amdgpu_vm_fault_stop;
177extern int amdgpu_vm_debug;
178extern int amdgpu_vm_update_mode;
179extern int amdgpu_exp_hw_support;
180extern int amdgpu_dc;
181extern int amdgpu_sched_jobs;
182extern int amdgpu_sched_hw_submission;
183extern uint amdgpu_pcie_gen_cap;
184extern uint amdgpu_pcie_lane_cap;
185extern u64 amdgpu_cg_mask;
186extern uint amdgpu_pg_mask;
187extern uint amdgpu_sdma_phase_quantum;
188extern char *amdgpu_disable_cu;
189extern char *amdgpu_virtual_display;
190extern uint amdgpu_pp_feature_mask;
191extern uint amdgpu_force_long_training;
192extern int amdgpu_lbpw;
193extern int amdgpu_compute_multipipe;
194extern int amdgpu_gpu_recovery;
195extern int amdgpu_emu_mode;
196extern uint amdgpu_smu_memory_pool_size;
197extern int amdgpu_smu_pptable_id;
198extern uint amdgpu_dc_feature_mask;
199extern uint amdgpu_dc_debug_mask;
200extern uint amdgpu_dc_visual_confirm;
201extern uint amdgpu_dm_abm_level;
202extern int amdgpu_backlight;
203extern struct amdgpu_mgpu_info mgpu_info;
204extern int amdgpu_ras_enable;
205extern uint amdgpu_ras_mask;
206extern int amdgpu_bad_page_threshold;
207extern bool amdgpu_ignore_bad_page_threshold;
208extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
209extern int amdgpu_async_gfx_ring;
210extern int amdgpu_mcbp;
211extern int amdgpu_discovery;
212extern int amdgpu_mes;
213extern int amdgpu_mes_kiq;
214extern int amdgpu_noretry;
215extern int amdgpu_force_asic_type;
216extern int amdgpu_smartshift_bias;
217extern int amdgpu_use_xgmi_p2p;
218extern int amdgpu_mtype_local;
219extern bool enforce_isolation;
220#ifdef CONFIG_HSA_AMD
221extern int sched_policy;
222extern bool debug_evictions;
223extern bool no_system_mem_limit;
224extern int halt_if_hws_hang;
225#else
226static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
227static const bool __maybe_unused debug_evictions; /* = false */
228static const bool __maybe_unused no_system_mem_limit;
229static const int __maybe_unused halt_if_hws_hang;
230#endif
231#ifdef CONFIG_HSA_AMD_P2P
232extern bool pcie_p2p;
233#endif
234
235extern int amdgpu_tmz;
236extern int amdgpu_reset_method;
237
238#ifdef CONFIG_DRM_AMDGPU_SI
239extern int amdgpu_si_support;
240#endif
241#ifdef CONFIG_DRM_AMDGPU_CIK
242extern int amdgpu_cik_support;
243#endif
244extern int amdgpu_num_kcq;
245
246#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
247extern int amdgpu_vcnfw_log;
248extern int amdgpu_sg_display;
249extern int amdgpu_umsch_mm;
250extern int amdgpu_seamless;
251
252extern int amdgpu_user_partt_mode;
253extern int amdgpu_agp;
254
255extern int amdgpu_wbrf;
256
257#define AMDGPU_VM_MAX_NUM_CTX 4096
258#define AMDGPU_SG_THRESHOLD (256*1024*1024)
259#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
260#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
261#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
262#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
263#define AMDGPUFB_CONN_LIMIT 4
264#define AMDGPU_BIOS_NUM_SCRATCH 16
265
266#define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
267
268/* hard reset data */
269#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
270
271/* reset flags */
272#define AMDGPU_RESET_GFX (1 << 0)
273#define AMDGPU_RESET_COMPUTE (1 << 1)
274#define AMDGPU_RESET_DMA (1 << 2)
275#define AMDGPU_RESET_CP (1 << 3)
276#define AMDGPU_RESET_GRBM (1 << 4)
277#define AMDGPU_RESET_DMA1 (1 << 5)
278#define AMDGPU_RESET_RLC (1 << 6)
279#define AMDGPU_RESET_SEM (1 << 7)
280#define AMDGPU_RESET_IH (1 << 8)
281#define AMDGPU_RESET_VMC (1 << 9)
282#define AMDGPU_RESET_MC (1 << 10)
283#define AMDGPU_RESET_DISPLAY (1 << 11)
284#define AMDGPU_RESET_UVD (1 << 12)
285#define AMDGPU_RESET_VCE (1 << 13)
286#define AMDGPU_RESET_VCE1 (1 << 14)
287
288/* max cursor sizes (in pixels) */
289#define CIK_CURSOR_WIDTH 128
290#define CIK_CURSOR_HEIGHT 128
291
292/* smart shift bias level limits */
293#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
294#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
295
296/* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */
297#define AMDGPU_SWCTF_EXTRA_DELAY 50
298
299struct amdgpu_xcp_mgr;
300struct amdgpu_device;
301struct amdgpu_irq_src;
302struct amdgpu_fpriv;
303struct amdgpu_bo_va_mapping;
304struct kfd_vm_fault_info;
305struct amdgpu_hive_info;
306struct amdgpu_reset_context;
307struct amdgpu_reset_control;
308
309enum amdgpu_cp_irq {
310 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
311 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
312 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
313 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
314 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
315 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
316 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
317 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
318 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
319 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
320
321 AMDGPU_CP_IRQ_LAST
322};
323
324enum amdgpu_thermal_irq {
325 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
326 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
327
328 AMDGPU_THERMAL_IRQ_LAST
329};
330
331enum amdgpu_kiq_irq {
332 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
333 AMDGPU_CP_KIQ_IRQ_LAST
334};
335#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
336#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
337#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
338#define MAX_KIQ_REG_TRY 1000
339
340int amdgpu_device_ip_set_clockgating_state(void *dev,
341 enum amd_ip_block_type block_type,
342 enum amd_clockgating_state state);
343int amdgpu_device_ip_set_powergating_state(void *dev,
344 enum amd_ip_block_type block_type,
345 enum amd_powergating_state state);
346void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
347 u64 *flags);
348int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
349 enum amd_ip_block_type block_type);
350bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
351 enum amd_ip_block_type block_type);
352
353#define AMDGPU_MAX_IP_NUM 16
354
355struct amdgpu_ip_block_status {
356 bool valid;
357 bool sw;
358 bool hw;
359 bool late_initialized;
360 bool hang;
361};
362
363struct amdgpu_ip_block_version {
364 const enum amd_ip_block_type type;
365 const u32 major;
366 const u32 minor;
367 const u32 rev;
368 const struct amd_ip_funcs *funcs;
369};
370
371struct amdgpu_ip_block {
372 struct amdgpu_ip_block_status status;
373 const struct amdgpu_ip_block_version *version;
374};
375
376int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
377 enum amd_ip_block_type type,
378 u32 major, u32 minor);
379
380struct amdgpu_ip_block *
381amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
382 enum amd_ip_block_type type);
383
384int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
385 const struct amdgpu_ip_block_version *ip_block_version);
386
387/*
388 * BIOS.
389 */
390bool amdgpu_get_bios(struct amdgpu_device *adev);
391bool amdgpu_read_bios(struct amdgpu_device *adev);
392bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
393 u8 *bios, u32 length_bytes);
394/*
395 * Clocks
396 */
397
398#define AMDGPU_MAX_PPLL 3
399
400struct amdgpu_clock {
401 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
402 struct amdgpu_pll spll;
403 struct amdgpu_pll mpll;
404 /* 10 Khz units */
405 uint32_t default_mclk;
406 uint32_t default_sclk;
407 uint32_t default_dispclk;
408 uint32_t current_dispclk;
409 uint32_t dp_extclk;
410 uint32_t max_pixel_clock;
411};
412
413/* sub-allocation manager, it has to be protected by another lock.
414 * By conception this is an helper for other part of the driver
415 * like the indirect buffer or semaphore, which both have their
416 * locking.
417 *
418 * Principe is simple, we keep a list of sub allocation in offset
419 * order (first entry has offset == 0, last entry has the highest
420 * offset).
421 *
422 * When allocating new object we first check if there is room at
423 * the end total_size - (last_object_offset + last_object_size) >=
424 * alloc_size. If so we allocate new object there.
425 *
426 * When there is not enough room at the end, we start waiting for
427 * each sub object until we reach object_offset+object_size >=
428 * alloc_size, this object then become the sub object we return.
429 *
430 * Alignment can't be bigger than page size.
431 *
432 * Hole are not considered for allocation to keep things simple.
433 * Assumption is that there won't be hole (all object on same
434 * alignment).
435 */
436
437struct amdgpu_sa_manager {
438 struct drm_suballoc_manager base;
439 struct amdgpu_bo *bo;
440 uint64_t gpu_addr;
441 void *cpu_ptr;
442};
443
444int amdgpu_fence_slab_init(void);
445void amdgpu_fence_slab_fini(void);
446
447/*
448 * IRQS.
449 */
450
451struct amdgpu_flip_work {
452 struct delayed_work flip_work;
453 struct work_struct unpin_work;
454 struct amdgpu_device *adev;
455 int crtc_id;
456 u32 target_vblank;
457 uint64_t base;
458 struct drm_pending_vblank_event *event;
459 struct amdgpu_bo *old_abo;
460 unsigned shared_count;
461 struct dma_fence **shared;
462 struct dma_fence_cb cb;
463 bool async;
464};
465
466
467/*
468 * file private structure
469 */
470
471struct amdgpu_fpriv {
472 struct amdgpu_vm vm;
473 struct amdgpu_bo_va *prt_va;
474 struct amdgpu_bo_va *csa_va;
475 struct amdgpu_bo_va *seq64_va;
476 struct mutex bo_list_lock;
477 struct idr bo_list_handles;
478 struct amdgpu_ctx_mgr ctx_mgr;
479 /** GPU partition selection */
480 uint32_t xcp_id;
481};
482
483int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
484
485/*
486 * Writeback
487 */
488#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
489
490struct amdgpu_wb {
491 struct amdgpu_bo *wb_obj;
492 volatile uint32_t *wb;
493 uint64_t gpu_addr;
494 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
495 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
496};
497
498int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
499void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
500
501/*
502 * Benchmarking
503 */
504int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
505
506/*
507 * ASIC specific register table accessible by UMD
508 */
509struct amdgpu_allowed_register_entry {
510 uint32_t reg_offset;
511 bool grbm_indexed;
512};
513
514/**
515 * enum amd_reset_method - Methods for resetting AMD GPU devices
516 *
517 * @AMD_RESET_METHOD_NONE: The device will not be reset.
518 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs.
519 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the
520 * any device.
521 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.)
522 * individually. Suitable only for some discrete GPU, not
523 * available for all ASICs.
524 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs
525 * are reset depends on the ASIC. Notably doesn't reset IPs
526 * shared with the CPU on APUs or the memory controllers (so
527 * VRAM is not lost). Not available on all ASICs.
528 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card
529 * but without powering off the PCI bus. Suitable only for
530 * discrete GPUs.
531 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset
532 * and does a secondary bus reset or FLR, depending on what the
533 * underlying hardware supports.
534 *
535 * Methods available for AMD GPU driver for resetting the device. Not all
536 * methods are suitable for every device. User can override the method using
537 * module parameter `reset_method`.
538 */
539enum amd_reset_method {
540 AMD_RESET_METHOD_NONE = -1,
541 AMD_RESET_METHOD_LEGACY = 0,
542 AMD_RESET_METHOD_MODE0,
543 AMD_RESET_METHOD_MODE1,
544 AMD_RESET_METHOD_MODE2,
545 AMD_RESET_METHOD_BACO,
546 AMD_RESET_METHOD_PCI,
547};
548
549struct amdgpu_video_codec_info {
550 u32 codec_type;
551 u32 max_width;
552 u32 max_height;
553 u32 max_pixels_per_frame;
554 u32 max_level;
555};
556
557#define codec_info_build(type, width, height, level) \
558 .codec_type = type,\
559 .max_width = width,\
560 .max_height = height,\
561 .max_pixels_per_frame = height * width,\
562 .max_level = level,
563
564struct amdgpu_video_codecs {
565 const u32 codec_count;
566 const struct amdgpu_video_codec_info *codec_array;
567};
568
569/*
570 * ASIC specific functions.
571 */
572struct amdgpu_asic_funcs {
573 bool (*read_disabled_bios)(struct amdgpu_device *adev);
574 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
575 u8 *bios, u32 length_bytes);
576 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
577 u32 sh_num, u32 reg_offset, u32 *value);
578 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
579 int (*reset)(struct amdgpu_device *adev);
580 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
581 /* get the reference clock */
582 u32 (*get_xclk)(struct amdgpu_device *adev);
583 /* MM block clocks */
584 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
585 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
586 /* static power management */
587 int (*get_pcie_lanes)(struct amdgpu_device *adev);
588 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
589 /* get config memsize register */
590 u32 (*get_config_memsize)(struct amdgpu_device *adev);
591 /* flush hdp write queue */
592 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
593 /* invalidate hdp read cache */
594 void (*invalidate_hdp)(struct amdgpu_device *adev,
595 struct amdgpu_ring *ring);
596 /* check if the asic needs a full reset of if soft reset will work */
597 bool (*need_full_reset)(struct amdgpu_device *adev);
598 /* initialize doorbell layout for specific asic*/
599 void (*init_doorbell_index)(struct amdgpu_device *adev);
600 /* PCIe bandwidth usage */
601 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
602 uint64_t *count1);
603 /* do we need to reset the asic at init time (e.g., kexec) */
604 bool (*need_reset_on_init)(struct amdgpu_device *adev);
605 /* PCIe replay counter */
606 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
607 /* device supports BACO */
608 bool (*supports_baco)(struct amdgpu_device *adev);
609 /* pre asic_init quirks */
610 void (*pre_asic_init)(struct amdgpu_device *adev);
611 /* enter/exit umd stable pstate */
612 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
613 /* query video codecs */
614 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
615 const struct amdgpu_video_codecs **codecs);
616 /* encode "> 32bits" smn addressing */
617 u64 (*encode_ext_smn_addressing)(int ext_id);
618
619 ssize_t (*get_reg_state)(struct amdgpu_device *adev,
620 enum amdgpu_reg_state reg_state, void *buf,
621 size_t max_size);
622};
623
624/*
625 * IOCTL.
626 */
627int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
628 struct drm_file *filp);
629
630int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
631int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
632 struct drm_file *filp);
633int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
634int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
635 struct drm_file *filp);
636
637/* VRAM scratch page for HDP bug, default vram page */
638struct amdgpu_mem_scratch {
639 struct amdgpu_bo *robj;
640 volatile uint32_t *ptr;
641 u64 gpu_addr;
642};
643
644/*
645 * CGS
646 */
647struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
648void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
649
650/*
651 * Core structure, functions and helpers.
652 */
653typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
654typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
655
656typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t);
657typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t);
658
659typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
660typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
661
662typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t);
663typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t);
664
665typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
666typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
667
668struct amdgpu_mmio_remap {
669 u32 reg_offset;
670 resource_size_t bus_addr;
671};
672
673/* Define the HW IP blocks will be used in driver , add more if necessary */
674enum amd_hw_ip_block_type {
675 GC_HWIP = 1,
676 HDP_HWIP,
677 SDMA0_HWIP,
678 SDMA1_HWIP,
679 SDMA2_HWIP,
680 SDMA3_HWIP,
681 SDMA4_HWIP,
682 SDMA5_HWIP,
683 SDMA6_HWIP,
684 SDMA7_HWIP,
685 LSDMA_HWIP,
686 MMHUB_HWIP,
687 ATHUB_HWIP,
688 NBIO_HWIP,
689 MP0_HWIP,
690 MP1_HWIP,
691 UVD_HWIP,
692 VCN_HWIP = UVD_HWIP,
693 JPEG_HWIP = VCN_HWIP,
694 VCN1_HWIP,
695 VCE_HWIP,
696 VPE_HWIP,
697 DF_HWIP,
698 DCE_HWIP,
699 OSSSYS_HWIP,
700 SMUIO_HWIP,
701 PWR_HWIP,
702 NBIF_HWIP,
703 THM_HWIP,
704 CLK_HWIP,
705 UMC_HWIP,
706 RSMU_HWIP,
707 XGMI_HWIP,
708 DCI_HWIP,
709 PCIE_HWIP,
710 MAX_HWIP
711};
712
713#define HWIP_MAX_INSTANCE 44
714
715#define HW_ID_MAX 300
716#define IP_VERSION_FULL(mj, mn, rv, var, srev) \
717 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev))
718#define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0)
719#define IP_VERSION_MAJ(ver) ((ver) >> 24)
720#define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF)
721#define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF)
722#define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF)
723#define IP_VERSION_SUBREV(ver) ((ver) & 0xF)
724#define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8)
725
726struct amdgpu_ip_map_info {
727 /* Map of logical to actual dev instances/mask */
728 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE];
729 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev,
730 enum amd_hw_ip_block_type block,
731 int8_t inst);
732 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,
733 enum amd_hw_ip_block_type block,
734 uint32_t mask);
735};
736
737struct amd_powerplay {
738 void *pp_handle;
739 const struct amd_pm_funcs *pp_funcs;
740};
741
742struct ip_discovery_top;
743
744/* polaris10 kickers */
745#define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
746 ((rid == 0xE3) || \
747 (rid == 0xE4) || \
748 (rid == 0xE5) || \
749 (rid == 0xE7) || \
750 (rid == 0xEF))) || \
751 ((did == 0x6FDF) && \
752 ((rid == 0xE7) || \
753 (rid == 0xEF) || \
754 (rid == 0xFF))))
755
756#define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
757 ((rid == 0xE1) || \
758 (rid == 0xF7)))
759
760/* polaris11 kickers */
761#define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
762 ((rid == 0xE0) || \
763 (rid == 0xE5))) || \
764 ((did == 0x67FF) && \
765 ((rid == 0xCF) || \
766 (rid == 0xEF) || \
767 (rid == 0xFF))))
768
769#define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
770 ((rid == 0xE2)))
771
772/* polaris12 kickers */
773#define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
774 ((rid == 0xC0) || \
775 (rid == 0xC1) || \
776 (rid == 0xC3) || \
777 (rid == 0xC7))) || \
778 ((did == 0x6981) && \
779 ((rid == 0x00) || \
780 (rid == 0x01) || \
781 (rid == 0x10))))
782
783struct amdgpu_mqd_prop {
784 uint64_t mqd_gpu_addr;
785 uint64_t hqd_base_gpu_addr;
786 uint64_t rptr_gpu_addr;
787 uint64_t wptr_gpu_addr;
788 uint32_t queue_size;
789 bool use_doorbell;
790 uint32_t doorbell_index;
791 uint64_t eop_gpu_addr;
792 uint32_t hqd_pipe_priority;
793 uint32_t hqd_queue_priority;
794 bool allow_tunneling;
795 bool hqd_active;
796};
797
798struct amdgpu_mqd {
799 unsigned mqd_size;
800 int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
801 struct amdgpu_mqd_prop *p);
802};
803
804#define AMDGPU_RESET_MAGIC_NUM 64
805#define AMDGPU_MAX_DF_PERFMONS 4
806struct amdgpu_reset_domain;
807struct amdgpu_fru_info;
808
809struct amdgpu_reset_info {
810 /* reset dump register */
811 u32 *reset_dump_reg_list;
812 u32 *reset_dump_reg_value;
813 int num_regs;
814
815#ifdef CONFIG_DEV_COREDUMP
816 struct amdgpu_coredump_info *coredump_info;
817#endif
818};
819
820/*
821 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
822 */
823#define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
824
825struct amdgpu_device {
826 struct device *dev;
827 struct pci_dev *pdev;
828 struct drm_device ddev;
829
830#ifdef CONFIG_DRM_AMD_ACP
831 struct amdgpu_acp acp;
832#endif
833 struct amdgpu_hive_info *hive;
834 struct amdgpu_xcp_mgr *xcp_mgr;
835 /* ASIC */
836 enum amd_asic_type asic_type;
837 uint32_t family;
838 uint32_t rev_id;
839 uint32_t external_rev_id;
840 unsigned long flags;
841 unsigned long apu_flags;
842 int usec_timeout;
843 const struct amdgpu_asic_funcs *asic_funcs;
844 bool shutdown;
845 bool need_swiotlb;
846 bool accel_working;
847 struct notifier_block acpi_nb;
848 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
849 struct debugfs_blob_wrapper debugfs_vbios_blob;
850 struct debugfs_blob_wrapper debugfs_discovery_blob;
851 struct mutex srbm_mutex;
852 /* GRBM index mutex. Protects concurrent access to GRBM index */
853 struct mutex grbm_idx_mutex;
854 struct dev_pm_domain vga_pm_domain;
855 bool have_disp_power_ref;
856 bool have_atomics_support;
857
858 /* BIOS */
859 bool is_atom_fw;
860 uint8_t *bios;
861 uint32_t bios_size;
862 uint32_t bios_scratch_reg_offset;
863 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
864
865 /* Register/doorbell mmio */
866 resource_size_t rmmio_base;
867 resource_size_t rmmio_size;
868 void __iomem *rmmio;
869 /* protects concurrent MM_INDEX/DATA based register access */
870 spinlock_t mmio_idx_lock;
871 struct amdgpu_mmio_remap rmmio_remap;
872 /* protects concurrent SMC based register access */
873 spinlock_t smc_idx_lock;
874 amdgpu_rreg_t smc_rreg;
875 amdgpu_wreg_t smc_wreg;
876 /* protects concurrent PCIE register access */
877 spinlock_t pcie_idx_lock;
878 amdgpu_rreg_t pcie_rreg;
879 amdgpu_wreg_t pcie_wreg;
880 amdgpu_rreg_t pciep_rreg;
881 amdgpu_wreg_t pciep_wreg;
882 amdgpu_rreg_ext_t pcie_rreg_ext;
883 amdgpu_wreg_ext_t pcie_wreg_ext;
884 amdgpu_rreg64_t pcie_rreg64;
885 amdgpu_wreg64_t pcie_wreg64;
886 amdgpu_rreg64_ext_t pcie_rreg64_ext;
887 amdgpu_wreg64_ext_t pcie_wreg64_ext;
888 /* protects concurrent UVD register access */
889 spinlock_t uvd_ctx_idx_lock;
890 amdgpu_rreg_t uvd_ctx_rreg;
891 amdgpu_wreg_t uvd_ctx_wreg;
892 /* protects concurrent DIDT register access */
893 spinlock_t didt_idx_lock;
894 amdgpu_rreg_t didt_rreg;
895 amdgpu_wreg_t didt_wreg;
896 /* protects concurrent gc_cac register access */
897 spinlock_t gc_cac_idx_lock;
898 amdgpu_rreg_t gc_cac_rreg;
899 amdgpu_wreg_t gc_cac_wreg;
900 /* protects concurrent se_cac register access */
901 spinlock_t se_cac_idx_lock;
902 amdgpu_rreg_t se_cac_rreg;
903 amdgpu_wreg_t se_cac_wreg;
904 /* protects concurrent ENDPOINT (audio) register access */
905 spinlock_t audio_endpt_idx_lock;
906 amdgpu_block_rreg_t audio_endpt_rreg;
907 amdgpu_block_wreg_t audio_endpt_wreg;
908 struct amdgpu_doorbell doorbell;
909
910 /* clock/pll info */
911 struct amdgpu_clock clock;
912
913 /* MC */
914 struct amdgpu_gmc gmc;
915 struct amdgpu_gart gart;
916 dma_addr_t dummy_page_addr;
917 struct amdgpu_vm_manager vm_manager;
918 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
919 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
920
921 /* memory management */
922 struct amdgpu_mman mman;
923 struct amdgpu_mem_scratch mem_scratch;
924 struct amdgpu_wb wb;
925 atomic64_t num_bytes_moved;
926 atomic64_t num_evictions;
927 atomic64_t num_vram_cpu_page_faults;
928 atomic_t gpu_reset_counter;
929 atomic_t vram_lost_counter;
930
931 /* data for buffer migration throttling */
932 struct {
933 spinlock_t lock;
934 s64 last_update_us;
935 s64 accum_us; /* accumulated microseconds */
936 s64 accum_us_vis; /* for visible VRAM */
937 u32 log2_max_MBps;
938 } mm_stats;
939
940 /* display */
941 bool enable_virtual_display;
942 struct amdgpu_vkms_output *amdgpu_vkms_output;
943 struct amdgpu_mode_info mode_info;
944 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
945 struct delayed_work hotplug_work;
946 struct amdgpu_irq_src crtc_irq;
947 struct amdgpu_irq_src vline0_irq;
948 struct amdgpu_irq_src vupdate_irq;
949 struct amdgpu_irq_src pageflip_irq;
950 struct amdgpu_irq_src hpd_irq;
951 struct amdgpu_irq_src dmub_trace_irq;
952 struct amdgpu_irq_src dmub_outbox_irq;
953
954 /* rings */
955 u64 fence_context;
956 unsigned num_rings;
957 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
958 struct dma_fence __rcu *gang_submit;
959 bool ib_pool_ready;
960 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
961 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
962
963 /* interrupts */
964 struct amdgpu_irq irq;
965
966 /* powerplay */
967 struct amd_powerplay powerplay;
968 struct amdgpu_pm pm;
969 u64 cg_flags;
970 u32 pg_flags;
971
972 /* nbio */
973 struct amdgpu_nbio nbio;
974
975 /* hdp */
976 struct amdgpu_hdp hdp;
977
978 /* smuio */
979 struct amdgpu_smuio smuio;
980
981 /* mmhub */
982 struct amdgpu_mmhub mmhub;
983
984 /* gfxhub */
985 struct amdgpu_gfxhub gfxhub;
986
987 /* gfx */
988 struct amdgpu_gfx gfx;
989
990 /* sdma */
991 struct amdgpu_sdma sdma;
992
993 /* lsdma */
994 struct amdgpu_lsdma lsdma;
995
996 /* uvd */
997 struct amdgpu_uvd uvd;
998
999 /* vce */
1000 struct amdgpu_vce vce;
1001
1002 /* vcn */
1003 struct amdgpu_vcn vcn;
1004
1005 /* jpeg */
1006 struct amdgpu_jpeg jpeg;
1007
1008 /* vpe */
1009 struct amdgpu_vpe vpe;
1010
1011 /* umsch */
1012 struct amdgpu_umsch_mm umsch_mm;
1013 bool enable_umsch_mm;
1014
1015 /* firmwares */
1016 struct amdgpu_firmware firmware;
1017
1018 /* PSP */
1019 struct psp_context psp;
1020
1021 /* GDS */
1022 struct amdgpu_gds gds;
1023
1024 /* for userq and VM fences */
1025 struct amdgpu_seq64 seq64;
1026
1027 /* KFD */
1028 struct amdgpu_kfd_dev kfd;
1029
1030 /* UMC */
1031 struct amdgpu_umc umc;
1032
1033 /* display related functionality */
1034 struct amdgpu_display_manager dm;
1035
1036 /* mes */
1037 bool enable_mes;
1038 bool enable_mes_kiq;
1039 struct amdgpu_mes mes;
1040 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
1041
1042 /* df */
1043 struct amdgpu_df df;
1044
1045 /* MCA */
1046 struct amdgpu_mca mca;
1047
1048 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1049 uint32_t harvest_ip_mask;
1050 int num_ip_blocks;
1051 struct mutex mn_lock;
1052 DECLARE_HASHTABLE(mn_hash, 7);
1053
1054 /* tracking pinned memory */
1055 atomic64_t vram_pin_size;
1056 atomic64_t visible_pin_size;
1057 atomic64_t gart_pin_size;
1058
1059 /* soc15 register offset based on ip, instance and segment */
1060 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1061 struct amdgpu_ip_map_info ip_map;
1062
1063 /* delayed work_func for deferring clockgating during resume */
1064 struct delayed_work delayed_init_work;
1065
1066 struct amdgpu_virt virt;
1067
1068 /* link all shadow bo */
1069 struct list_head shadow_list;
1070 struct mutex shadow_list_lock;
1071
1072 /* record hw reset is performed */
1073 bool has_hw_reset;
1074 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1075
1076 /* s3/s4 mask */
1077 bool in_suspend;
1078 bool in_s3;
1079 bool in_s4;
1080 bool in_s0ix;
1081
1082 enum pp_mp1_state mp1_state;
1083 struct amdgpu_doorbell_index doorbell_index;
1084
1085 struct mutex notifier_lock;
1086
1087 int asic_reset_res;
1088 struct work_struct xgmi_reset_work;
1089 struct list_head reset_list;
1090
1091 long gfx_timeout;
1092 long sdma_timeout;
1093 long video_timeout;
1094 long compute_timeout;
1095
1096 uint64_t unique_id;
1097 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1098
1099 /* enable runtime pm on the device */
1100 bool in_runpm;
1101 bool has_pr3;
1102
1103 bool ucode_sysfs_en;
1104
1105 struct amdgpu_fru_info *fru_info;
1106 atomic_t throttling_logging_enabled;
1107 struct ratelimit_state throttling_logging_rs;
1108 uint32_t ras_hw_enabled;
1109 uint32_t ras_enabled;
1110
1111 bool no_hw_access;
1112 struct pci_saved_state *pci_state;
1113 pci_channel_state_t pci_channel_state;
1114
1115 /* Track auto wait count on s_barrier settings */
1116 bool barrier_has_auto_waitcnt;
1117
1118 struct amdgpu_reset_control *reset_cntl;
1119 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1120
1121 bool ram_is_direct_mapped;
1122
1123 struct list_head ras_list;
1124
1125 struct ip_discovery_top *ip_top;
1126
1127 struct amdgpu_reset_domain *reset_domain;
1128
1129 struct mutex benchmark_mutex;
1130
1131 struct amdgpu_reset_info reset_info;
1132
1133 bool scpm_enabled;
1134 uint32_t scpm_status;
1135
1136 struct work_struct reset_work;
1137
1138 bool job_hang;
1139 bool dc_enabled;
1140 /* Mask of active clusters */
1141 uint32_t aid_mask;
1142
1143 /* Debug */
1144 bool debug_vm;
1145 bool debug_largebar;
1146 bool debug_disable_soft_recovery;
1147 bool debug_use_vram_fw_buf;
1148};
1149
1150static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
1151 uint8_t ip, uint8_t inst)
1152{
1153 /* This considers only major/minor/rev and ignores
1154 * subrevision/variant fields.
1155 */
1156 return adev->ip_versions[ip][inst] & ~0xFFU;
1157}
1158
1159static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev,
1160 uint8_t ip, uint8_t inst)
1161{
1162 /* This returns full version - major/minor/rev/variant/subrevision */
1163 return adev->ip_versions[ip][inst];
1164}
1165
1166static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1167{
1168 return container_of(ddev, struct amdgpu_device, ddev);
1169}
1170
1171static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1172{
1173 return &adev->ddev;
1174}
1175
1176static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1177{
1178 return container_of(bdev, struct amdgpu_device, mman.bdev);
1179}
1180
1181int amdgpu_device_init(struct amdgpu_device *adev,
1182 uint32_t flags);
1183void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1184void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1185
1186int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1187
1188void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1189 void *buf, size_t size, bool write);
1190size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1191 void *buf, size_t size, bool write);
1192
1193void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1194 void *buf, size_t size, bool write);
1195uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
1196 uint32_t inst, uint32_t reg_addr, char reg_name[],
1197 uint32_t expected_value, uint32_t mask);
1198uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1199 uint32_t reg, uint32_t acc_flags);
1200u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
1201 u64 reg_addr);
1202uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
1203 uint32_t reg, uint32_t acc_flags,
1204 uint32_t xcc_id);
1205void amdgpu_device_wreg(struct amdgpu_device *adev,
1206 uint32_t reg, uint32_t v,
1207 uint32_t acc_flags);
1208void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
1209 u64 reg_addr, u32 reg_data);
1210void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
1211 uint32_t reg, uint32_t v,
1212 uint32_t acc_flags,
1213 uint32_t xcc_id);
1214void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1215 uint32_t reg, uint32_t v, uint32_t xcc_id);
1216void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1217uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1218
1219u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1220 u32 reg_addr);
1221u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1222 u32 reg_addr);
1223u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
1224 u64 reg_addr);
1225void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1226 u32 reg_addr, u32 reg_data);
1227void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1228 u32 reg_addr, u64 reg_data);
1229void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
1230 u64 reg_addr, u64 reg_data);
1231u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);
1232bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1233bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1234
1235void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1236
1237int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1238 struct amdgpu_reset_context *reset_context);
1239
1240int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1241 struct amdgpu_reset_context *reset_context);
1242
1243int emu_soc_asic_init(struct amdgpu_device *adev);
1244
1245/*
1246 * Registers read & write functions.
1247 */
1248#define AMDGPU_REGS_NO_KIQ (1<<1)
1249#define AMDGPU_REGS_RLC (1<<2)
1250
1251#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1252#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1253
1254#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0)
1255#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0)
1256
1257#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1258#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1259
1260#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1261#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1262#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1263#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1264#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1265#define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst)
1266#define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)
1267#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1268#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1269#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1270#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1271#define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
1272#define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
1273#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1274#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1275#define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg))
1276#define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v))
1277#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1278#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1279#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1280#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1281#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1282#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1283#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1284#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1285#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1286#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1287#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1288#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1289#define WREG32_P(reg, val, mask) \
1290 do { \
1291 uint32_t tmp_ = RREG32(reg); \
1292 tmp_ &= (mask); \
1293 tmp_ |= ((val) & ~(mask)); \
1294 WREG32(reg, tmp_); \
1295 } while (0)
1296#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1297#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1298#define WREG32_PLL_P(reg, val, mask) \
1299 do { \
1300 uint32_t tmp_ = RREG32_PLL(reg); \
1301 tmp_ &= (mask); \
1302 tmp_ |= ((val) & ~(mask)); \
1303 WREG32_PLL(reg, tmp_); \
1304 } while (0)
1305
1306#define WREG32_SMC_P(_Reg, _Val, _Mask) \
1307 do { \
1308 u32 tmp = RREG32_SMC(_Reg); \
1309 tmp &= (_Mask); \
1310 tmp |= ((_Val) & ~(_Mask)); \
1311 WREG32_SMC(_Reg, tmp); \
1312 } while (0)
1313
1314#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1315
1316#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1317#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1318
1319#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1320 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1321 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1322
1323#define REG_GET_FIELD(value, reg, field) \
1324 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1325
1326#define WREG32_FIELD(reg, field, val) \
1327 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1328
1329#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1330 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1331
1332/*
1333 * BIOS helpers.
1334 */
1335#define RBIOS8(i) (adev->bios[i])
1336#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1337#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1338
1339/*
1340 * ASICs macro.
1341 */
1342#define amdgpu_asic_set_vga_state(adev, state) \
1343 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
1344#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1345#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1346#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1347#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1348#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1349#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1350#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1351#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1352#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1353#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1354#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1355#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1356#define amdgpu_asic_flush_hdp(adev, r) \
1357 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1358#define amdgpu_asic_invalidate_hdp(adev, r) \
1359 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1360 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0))
1361#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1362#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1363#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1364#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1365#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1366#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1367#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1368#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1369 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1370#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1371
1372#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter))
1373
1374#define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i))
1375#define for_each_inst(i, inst_mask) \
1376 for (i = ffs(inst_mask); i-- != 0; \
1377 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
1378
1379/* Common functions */
1380bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1381bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1382int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1383 struct amdgpu_job *job,
1384 struct amdgpu_reset_context *reset_context);
1385void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1386int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1387bool amdgpu_device_need_post(struct amdgpu_device *adev);
1388bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev);
1389bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1390
1391void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1392 u64 num_vis_bytes);
1393int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1394void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1395 const u32 *registers,
1396 const u32 array_size);
1397
1398int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1399bool amdgpu_device_supports_atpx(struct drm_device *dev);
1400bool amdgpu_device_supports_px(struct drm_device *dev);
1401bool amdgpu_device_supports_boco(struct drm_device *dev);
1402bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1403bool amdgpu_device_supports_baco(struct drm_device *dev);
1404bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1405 struct amdgpu_device *peer_adev);
1406int amdgpu_device_baco_enter(struct drm_device *dev);
1407int amdgpu_device_baco_exit(struct drm_device *dev);
1408
1409void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1410 struct amdgpu_ring *ring);
1411void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1412 struct amdgpu_ring *ring);
1413
1414void amdgpu_device_halt(struct amdgpu_device *adev);
1415u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1416 u32 reg);
1417void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1418 u32 reg, u32 v);
1419struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1420 struct dma_fence *gang);
1421bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1422
1423/* atpx handler */
1424#if defined(CONFIG_VGA_SWITCHEROO)
1425void amdgpu_register_atpx_handler(void);
1426void amdgpu_unregister_atpx_handler(void);
1427bool amdgpu_has_atpx_dgpu_power_cntl(void);
1428bool amdgpu_is_atpx_hybrid(void);
1429bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1430bool amdgpu_has_atpx(void);
1431#else
1432static inline void amdgpu_register_atpx_handler(void) {}
1433static inline void amdgpu_unregister_atpx_handler(void) {}
1434static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1435static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1436static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1437static inline bool amdgpu_has_atpx(void) { return false; }
1438#endif
1439
1440#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1441void *amdgpu_atpx_get_dhandle(void);
1442#else
1443static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1444#endif
1445
1446/*
1447 * KMS
1448 */
1449extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1450extern const int amdgpu_max_kms_ioctl;
1451
1452int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1453void amdgpu_driver_unload_kms(struct drm_device *dev);
1454void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1455int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1456void amdgpu_driver_postclose_kms(struct drm_device *dev,
1457 struct drm_file *file_priv);
1458void amdgpu_driver_release_kms(struct drm_device *dev);
1459
1460int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1461int amdgpu_device_prepare(struct drm_device *dev);
1462int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1463int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1464u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1465int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1466void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1467int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1468 struct drm_file *filp);
1469
1470/*
1471 * functions used by amdgpu_encoder.c
1472 */
1473struct amdgpu_afmt_acr {
1474 u32 clock;
1475
1476 int n_32khz;
1477 int cts_32khz;
1478
1479 int n_44_1khz;
1480 int cts_44_1khz;
1481
1482 int n_48khz;
1483 int cts_48khz;
1484
1485};
1486
1487struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1488
1489/* amdgpu_acpi.c */
1490
1491struct amdgpu_numa_info {
1492 uint64_t size;
1493 int pxm;
1494 int nid;
1495};
1496
1497/* ATCS Device/Driver State */
1498#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
1499#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
1500#define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
1501#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
1502
1503#if defined(CONFIG_ACPI)
1504int amdgpu_acpi_init(struct amdgpu_device *adev);
1505void amdgpu_acpi_fini(struct amdgpu_device *adev);
1506bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1507bool amdgpu_acpi_is_power_shift_control_supported(void);
1508int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1509 u8 perf_req, bool advertise);
1510int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1511 u8 dev_state, bool drv_state);
1512int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1513int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1514int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
1515 u64 *tmr_size);
1516int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1517 struct amdgpu_numa_info *numa_info);
1518
1519void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1520bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1521void amdgpu_acpi_detect(void);
1522void amdgpu_acpi_release(void);
1523#else
1524static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1525static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
1526 u64 *tmr_offset, u64 *tmr_size)
1527{
1528 return -EINVAL;
1529}
1530static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
1531 int xcc_id,
1532 struct amdgpu_numa_info *numa_info)
1533{
1534 return -EINVAL;
1535}
1536static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1537static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1538static inline void amdgpu_acpi_detect(void) { }
1539static inline void amdgpu_acpi_release(void) { }
1540static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1541static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1542 u8 dev_state, bool drv_state) { return 0; }
1543static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1544 enum amdgpu_ss ss_state) { return 0; }
1545#endif
1546
1547#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1548bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1549bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1550#else
1551static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1552static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1553#endif
1554
1555#if defined(CONFIG_DRM_AMD_DC)
1556int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1557#else
1558static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1559#endif
1560
1561
1562void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1563void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1564
1565pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1566 pci_channel_state_t state);
1567pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1568pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1569void amdgpu_pci_resume(struct pci_dev *pdev);
1570
1571bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1572bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1573
1574bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1575
1576int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1577 enum amd_clockgating_state state);
1578int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1579 enum amd_powergating_state state);
1580
1581static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1582{
1583 return amdgpu_gpu_recovery != 0 &&
1584 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1585 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1586 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1587 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1588}
1589
1590#include "amdgpu_object.h"
1591
1592static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1593{
1594 return adev->gmc.tmz_enabled;
1595}
1596
1597int amdgpu_in_reset(struct amdgpu_device *adev);
1598
1599extern const struct attribute_group amdgpu_vram_mgr_attr_group;
1600extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
1601extern const struct attribute_group amdgpu_flash_attr_group;
1602
1603#endif