Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
2/* Do not edit directly, auto-generated from: */
3/* Documentation/netlink/specs/dpll.yaml */
4/* YNL-GEN uapi header */
5
6#ifndef _UAPI_LINUX_DPLL_H
7#define _UAPI_LINUX_DPLL_H
8
9#define DPLL_FAMILY_NAME "dpll"
10#define DPLL_FAMILY_VERSION 1
11
12/**
13 * enum dpll_mode - working modes a dpll can support, differentiates if and how
14 * dpll selects one of its inputs to syntonize with it, valid values for
15 * DPLL_A_MODE attribute
16 * @DPLL_MODE_MANUAL: input can be only selected by sending a request to dpll
17 * @DPLL_MODE_AUTOMATIC: highest prio input pin auto selected by dpll
18 */
19enum dpll_mode {
20 DPLL_MODE_MANUAL = 1,
21 DPLL_MODE_AUTOMATIC,
22
23 /* private: */
24 __DPLL_MODE_MAX,
25 DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1)
26};
27
28/**
29 * enum dpll_lock_status - provides information of dpll device lock status,
30 * valid values for DPLL_A_LOCK_STATUS attribute
31 * @DPLL_LOCK_STATUS_UNLOCKED: dpll was not yet locked to any valid input (or
32 * forced by setting DPLL_A_MODE to DPLL_MODE_DETACHED)
33 * @DPLL_LOCK_STATUS_LOCKED: dpll is locked to a valid signal, but no holdover
34 * available
35 * @DPLL_LOCK_STATUS_LOCKED_HO_ACQ: dpll is locked and holdover acquired
36 * @DPLL_LOCK_STATUS_HOLDOVER: dpll is in holdover state - lost a valid lock or
37 * was forced by disconnecting all the pins (latter possible only when dpll
38 * lock-state was already DPLL_LOCK_STATUS_LOCKED_HO_ACQ, if dpll lock-state
39 * was not DPLL_LOCK_STATUS_LOCKED_HO_ACQ, the dpll's lock-state shall remain
40 * DPLL_LOCK_STATUS_UNLOCKED)
41 */
42enum dpll_lock_status {
43 DPLL_LOCK_STATUS_UNLOCKED = 1,
44 DPLL_LOCK_STATUS_LOCKED,
45 DPLL_LOCK_STATUS_LOCKED_HO_ACQ,
46 DPLL_LOCK_STATUS_HOLDOVER,
47
48 /* private: */
49 __DPLL_LOCK_STATUS_MAX,
50 DPLL_LOCK_STATUS_MAX = (__DPLL_LOCK_STATUS_MAX - 1)
51};
52
53#define DPLL_TEMP_DIVIDER 1000
54
55/**
56 * enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute
57 * @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal
58 * @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock
59 */
60enum dpll_type {
61 DPLL_TYPE_PPS = 1,
62 DPLL_TYPE_EEC,
63
64 /* private: */
65 __DPLL_TYPE_MAX,
66 DPLL_TYPE_MAX = (__DPLL_TYPE_MAX - 1)
67};
68
69/**
70 * enum dpll_pin_type - defines possible types of a pin, valid values for
71 * DPLL_A_PIN_TYPE attribute
72 * @DPLL_PIN_TYPE_MUX: aggregates another layer of selectable pins
73 * @DPLL_PIN_TYPE_EXT: external input
74 * @DPLL_PIN_TYPE_SYNCE_ETH_PORT: ethernet port PHY's recovered clock
75 * @DPLL_PIN_TYPE_INT_OSCILLATOR: device internal oscillator
76 * @DPLL_PIN_TYPE_GNSS: GNSS recovered clock
77 */
78enum dpll_pin_type {
79 DPLL_PIN_TYPE_MUX = 1,
80 DPLL_PIN_TYPE_EXT,
81 DPLL_PIN_TYPE_SYNCE_ETH_PORT,
82 DPLL_PIN_TYPE_INT_OSCILLATOR,
83 DPLL_PIN_TYPE_GNSS,
84
85 /* private: */
86 __DPLL_PIN_TYPE_MAX,
87 DPLL_PIN_TYPE_MAX = (__DPLL_PIN_TYPE_MAX - 1)
88};
89
90/**
91 * enum dpll_pin_direction - defines possible direction of a pin, valid values
92 * for DPLL_A_PIN_DIRECTION attribute
93 * @DPLL_PIN_DIRECTION_INPUT: pin used as a input of a signal
94 * @DPLL_PIN_DIRECTION_OUTPUT: pin used to output the signal
95 */
96enum dpll_pin_direction {
97 DPLL_PIN_DIRECTION_INPUT = 1,
98 DPLL_PIN_DIRECTION_OUTPUT,
99
100 /* private: */
101 __DPLL_PIN_DIRECTION_MAX,
102 DPLL_PIN_DIRECTION_MAX = (__DPLL_PIN_DIRECTION_MAX - 1)
103};
104
105#define DPLL_PIN_FREQUENCY_1_HZ 1
106#define DPLL_PIN_FREQUENCY_10_KHZ 10000
107#define DPLL_PIN_FREQUENCY_77_5_KHZ 77500
108#define DPLL_PIN_FREQUENCY_10_MHZ 10000000
109
110/**
111 * enum dpll_pin_state - defines possible states of a pin, valid values for
112 * DPLL_A_PIN_STATE attribute
113 * @DPLL_PIN_STATE_CONNECTED: pin connected, active input of phase locked loop
114 * @DPLL_PIN_STATE_DISCONNECTED: pin disconnected, not considered as a valid
115 * input
116 * @DPLL_PIN_STATE_SELECTABLE: pin enabled for automatic input selection
117 */
118enum dpll_pin_state {
119 DPLL_PIN_STATE_CONNECTED = 1,
120 DPLL_PIN_STATE_DISCONNECTED,
121 DPLL_PIN_STATE_SELECTABLE,
122
123 /* private: */
124 __DPLL_PIN_STATE_MAX,
125 DPLL_PIN_STATE_MAX = (__DPLL_PIN_STATE_MAX - 1)
126};
127
128/**
129 * enum dpll_pin_capabilities - defines possible capabilities of a pin, valid
130 * flags on DPLL_A_PIN_CAPABILITIES attribute
131 * @DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE: pin direction can be changed
132 * @DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE: pin priority can be changed
133 * @DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE: pin state can be changed
134 */
135enum dpll_pin_capabilities {
136 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE = 1,
137 DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE = 2,
138 DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4,
139};
140
141#define DPLL_PHASE_OFFSET_DIVIDER 1000
142
143enum dpll_a {
144 DPLL_A_ID = 1,
145 DPLL_A_MODULE_NAME,
146 DPLL_A_PAD,
147 DPLL_A_CLOCK_ID,
148 DPLL_A_MODE,
149 DPLL_A_MODE_SUPPORTED,
150 DPLL_A_LOCK_STATUS,
151 DPLL_A_TEMP,
152 DPLL_A_TYPE,
153
154 __DPLL_A_MAX,
155 DPLL_A_MAX = (__DPLL_A_MAX - 1)
156};
157
158enum dpll_a_pin {
159 DPLL_A_PIN_ID = 1,
160 DPLL_A_PIN_PARENT_ID,
161 DPLL_A_PIN_MODULE_NAME,
162 DPLL_A_PIN_PAD,
163 DPLL_A_PIN_CLOCK_ID,
164 DPLL_A_PIN_BOARD_LABEL,
165 DPLL_A_PIN_PANEL_LABEL,
166 DPLL_A_PIN_PACKAGE_LABEL,
167 DPLL_A_PIN_TYPE,
168 DPLL_A_PIN_DIRECTION,
169 DPLL_A_PIN_FREQUENCY,
170 DPLL_A_PIN_FREQUENCY_SUPPORTED,
171 DPLL_A_PIN_FREQUENCY_MIN,
172 DPLL_A_PIN_FREQUENCY_MAX,
173 DPLL_A_PIN_PRIO,
174 DPLL_A_PIN_STATE,
175 DPLL_A_PIN_CAPABILITIES,
176 DPLL_A_PIN_PARENT_DEVICE,
177 DPLL_A_PIN_PARENT_PIN,
178 DPLL_A_PIN_PHASE_ADJUST_MIN,
179 DPLL_A_PIN_PHASE_ADJUST_MAX,
180 DPLL_A_PIN_PHASE_ADJUST,
181 DPLL_A_PIN_PHASE_OFFSET,
182
183 __DPLL_A_PIN_MAX,
184 DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)
185};
186
187enum dpll_cmd {
188 DPLL_CMD_DEVICE_ID_GET = 1,
189 DPLL_CMD_DEVICE_GET,
190 DPLL_CMD_DEVICE_SET,
191 DPLL_CMD_DEVICE_CREATE_NTF,
192 DPLL_CMD_DEVICE_DELETE_NTF,
193 DPLL_CMD_DEVICE_CHANGE_NTF,
194 DPLL_CMD_PIN_ID_GET,
195 DPLL_CMD_PIN_GET,
196 DPLL_CMD_PIN_SET,
197 DPLL_CMD_PIN_CREATE_NTF,
198 DPLL_CMD_PIN_DELETE_NTF,
199 DPLL_CMD_PIN_CHANGE_NTF,
200
201 __DPLL_CMD_MAX,
202 DPLL_CMD_MAX = (__DPLL_CMD_MAX - 1)
203};
204
205#define DPLL_MCGRP_MONITOR "monitor"
206
207#endif /* _UAPI_LINUX_DPLL_H */