tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display overlay
8
9maintainers:
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14 Mediatek display overlay, namely OVL, can do alpha blending from
15 the memory.
16 OVL device node must be siblings to the central MMSYS_CONFIG node.
17 For a description of the MMSYS_CONFIG binding, see
18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19 for details.
20
21properties:
22 compatible:
23 oneOf:
24 - enum:
25 - mediatek,mt2701-disp-ovl
26 - mediatek,mt8173-disp-ovl
27 - mediatek,mt8183-disp-ovl
28 - mediatek,mt8192-disp-ovl
29 - items:
30 - enum:
31 - mediatek,mt7623-disp-ovl
32 - mediatek,mt2712-disp-ovl
33 - const: mediatek,mt2701-disp-ovl
34 - items:
35 - enum:
36 - mediatek,mt6795-disp-ovl
37 - const: mediatek,mt8173-disp-ovl
38 - items:
39 - enum:
40 - mediatek,mt8188-disp-ovl
41 - mediatek,mt8195-disp-ovl
42 - const: mediatek,mt8183-disp-ovl
43 - items:
44 - enum:
45 - mediatek,mt8186-disp-ovl
46 - const: mediatek,mt8192-disp-ovl
47
48 reg:
49 maxItems: 1
50
51 interrupts:
52 maxItems: 1
53
54 power-domains:
55 description: A phandle and PM domain specifier as defined by bindings of
56 the power controller specified by phandle. See
57 Documentation/devicetree/bindings/power/power-domain.yaml for details.
58
59 clocks:
60 items:
61 - description: OVL Clock
62
63 iommus:
64 description:
65 This property should point to the respective IOMMU block with master port as argument,
66 see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
67
68 mediatek,gce-client-reg:
69 description: The register of client driver can be configured by gce with
70 4 arguments defined in this property, such as phandle of gce, subsys id,
71 register offset and size. Each GCE subsys id is mapping to a client
72 defined in the header include/dt-bindings/gce/<chip>-gce.h.
73 $ref: /schemas/types.yaml#/definitions/phandle-array
74 maxItems: 1
75
76required:
77 - compatible
78 - reg
79 - interrupts
80 - power-domains
81 - clocks
82 - iommus
83
84additionalProperties: false
85
86examples:
87 - |
88 #include <dt-bindings/interrupt-controller/arm-gic.h>
89 #include <dt-bindings/clock/mt8173-clk.h>
90 #include <dt-bindings/power/mt8173-power.h>
91 #include <dt-bindings/gce/mt8173-gce.h>
92 #include <dt-bindings/memory/mt8173-larb-port.h>
93
94 soc {
95 #address-cells = <2>;
96 #size-cells = <2>;
97
98 ovl0: ovl@1400c000 {
99 compatible = "mediatek,mt8173-disp-ovl";
100 reg = <0 0x1400c000 0 0x1000>;
101 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
102 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
103 clocks = <&mmsys CLK_MM_DISP_OVL0>;
104 iommus = <&iommu M4U_PORT_DISP_OVL0>;
105 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
106 };
107 };