tjh.dev
Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: YT SHEN <yt.shen@mediatek.com>
5 */
6
7#include <linux/component.h>
8#include <linux/iommu.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/of_platform.h>
12#include <linux/platform_device.h>
13#include <linux/pm_runtime.h>
14#include <linux/dma-mapping.h>
15
16#include <drm/drm_atomic.h>
17#include <drm/drm_atomic_helper.h>
18#include <drm/drm_drv.h>
19#include <drm/drm_fbdev_generic.h>
20#include <drm/drm_fourcc.h>
21#include <drm/drm_gem.h>
22#include <drm/drm_gem_framebuffer_helper.h>
23#include <drm/drm_ioctl.h>
24#include <drm/drm_of.h>
25#include <drm/drm_probe_helper.h>
26#include <drm/drm_vblank.h>
27
28#include "mtk_drm_crtc.h"
29#include "mtk_drm_ddp_comp.h"
30#include "mtk_drm_drv.h"
31#include "mtk_drm_gem.h"
32
33#define DRIVER_NAME "mediatek"
34#define DRIVER_DESC "Mediatek SoC DRM"
35#define DRIVER_DATE "20150513"
36#define DRIVER_MAJOR 1
37#define DRIVER_MINOR 0
38
39static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
40 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
41};
42
43static struct drm_framebuffer *
44mtk_drm_mode_fb_create(struct drm_device *dev,
45 struct drm_file *file,
46 const struct drm_mode_fb_cmd2 *cmd)
47{
48 const struct drm_format_info *info = drm_get_format_info(dev, cmd);
49
50 if (info->num_planes != 1)
51 return ERR_PTR(-EINVAL);
52
53 return drm_gem_fb_create(dev, file, cmd);
54}
55
56static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
57 .fb_create = mtk_drm_mode_fb_create,
58 .atomic_check = drm_atomic_helper_check,
59 .atomic_commit = drm_atomic_helper_commit,
60};
61
62static const unsigned int mt2701_mtk_ddp_main[] = {
63 DDP_COMPONENT_OVL0,
64 DDP_COMPONENT_RDMA0,
65 DDP_COMPONENT_COLOR0,
66 DDP_COMPONENT_BLS,
67 DDP_COMPONENT_DSI0,
68};
69
70static const unsigned int mt2701_mtk_ddp_ext[] = {
71 DDP_COMPONENT_RDMA1,
72 DDP_COMPONENT_DPI0,
73};
74
75static const unsigned int mt7623_mtk_ddp_main[] = {
76 DDP_COMPONENT_OVL0,
77 DDP_COMPONENT_RDMA0,
78 DDP_COMPONENT_COLOR0,
79 DDP_COMPONENT_BLS,
80 DDP_COMPONENT_DPI0,
81};
82
83static const unsigned int mt7623_mtk_ddp_ext[] = {
84 DDP_COMPONENT_RDMA1,
85 DDP_COMPONENT_DSI0,
86};
87
88static const unsigned int mt2712_mtk_ddp_main[] = {
89 DDP_COMPONENT_OVL0,
90 DDP_COMPONENT_COLOR0,
91 DDP_COMPONENT_AAL0,
92 DDP_COMPONENT_OD0,
93 DDP_COMPONENT_RDMA0,
94 DDP_COMPONENT_DPI0,
95 DDP_COMPONENT_PWM0,
96};
97
98static const unsigned int mt2712_mtk_ddp_ext[] = {
99 DDP_COMPONENT_OVL1,
100 DDP_COMPONENT_COLOR1,
101 DDP_COMPONENT_AAL1,
102 DDP_COMPONENT_OD1,
103 DDP_COMPONENT_RDMA1,
104 DDP_COMPONENT_DPI1,
105 DDP_COMPONENT_PWM1,
106};
107
108static const unsigned int mt2712_mtk_ddp_third[] = {
109 DDP_COMPONENT_RDMA2,
110 DDP_COMPONENT_DSI3,
111 DDP_COMPONENT_PWM2,
112};
113
114static unsigned int mt8167_mtk_ddp_main[] = {
115 DDP_COMPONENT_OVL0,
116 DDP_COMPONENT_COLOR0,
117 DDP_COMPONENT_CCORR,
118 DDP_COMPONENT_AAL0,
119 DDP_COMPONENT_GAMMA,
120 DDP_COMPONENT_DITHER0,
121 DDP_COMPONENT_RDMA0,
122 DDP_COMPONENT_DSI0,
123};
124
125static const unsigned int mt8173_mtk_ddp_main[] = {
126 DDP_COMPONENT_OVL0,
127 DDP_COMPONENT_COLOR0,
128 DDP_COMPONENT_AAL0,
129 DDP_COMPONENT_OD0,
130 DDP_COMPONENT_RDMA0,
131 DDP_COMPONENT_UFOE,
132 DDP_COMPONENT_DSI0,
133 DDP_COMPONENT_PWM0,
134};
135
136static const unsigned int mt8173_mtk_ddp_ext[] = {
137 DDP_COMPONENT_OVL1,
138 DDP_COMPONENT_COLOR1,
139 DDP_COMPONENT_GAMMA,
140 DDP_COMPONENT_RDMA1,
141 DDP_COMPONENT_DPI0,
142};
143
144static const unsigned int mt8183_mtk_ddp_main[] = {
145 DDP_COMPONENT_OVL0,
146 DDP_COMPONENT_OVL_2L0,
147 DDP_COMPONENT_RDMA0,
148 DDP_COMPONENT_COLOR0,
149 DDP_COMPONENT_CCORR,
150 DDP_COMPONENT_AAL0,
151 DDP_COMPONENT_GAMMA,
152 DDP_COMPONENT_DITHER0,
153 DDP_COMPONENT_DSI0,
154};
155
156static const unsigned int mt8183_mtk_ddp_ext[] = {
157 DDP_COMPONENT_OVL_2L1,
158 DDP_COMPONENT_RDMA1,
159 DDP_COMPONENT_DPI0,
160};
161
162static const unsigned int mt8186_mtk_ddp_main[] = {
163 DDP_COMPONENT_OVL0,
164 DDP_COMPONENT_RDMA0,
165 DDP_COMPONENT_COLOR0,
166 DDP_COMPONENT_CCORR,
167 DDP_COMPONENT_AAL0,
168 DDP_COMPONENT_GAMMA,
169 DDP_COMPONENT_POSTMASK0,
170 DDP_COMPONENT_DITHER0,
171 DDP_COMPONENT_DSI0,
172};
173
174static const unsigned int mt8186_mtk_ddp_ext[] = {
175 DDP_COMPONENT_OVL_2L0,
176 DDP_COMPONENT_RDMA1,
177 DDP_COMPONENT_DPI0,
178};
179
180static const unsigned int mt8188_mtk_ddp_main[] = {
181 DDP_COMPONENT_OVL0,
182 DDP_COMPONENT_RDMA0,
183 DDP_COMPONENT_COLOR0,
184 DDP_COMPONENT_CCORR,
185 DDP_COMPONENT_AAL0,
186 DDP_COMPONENT_GAMMA,
187 DDP_COMPONENT_POSTMASK0,
188 DDP_COMPONENT_DITHER0,
189};
190
191static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = {
192 {0, DDP_COMPONENT_DP_INTF0},
193 {0, DDP_COMPONENT_DSI0},
194};
195
196static const unsigned int mt8192_mtk_ddp_main[] = {
197 DDP_COMPONENT_OVL0,
198 DDP_COMPONENT_OVL_2L0,
199 DDP_COMPONENT_RDMA0,
200 DDP_COMPONENT_COLOR0,
201 DDP_COMPONENT_CCORR,
202 DDP_COMPONENT_AAL0,
203 DDP_COMPONENT_GAMMA,
204 DDP_COMPONENT_POSTMASK0,
205 DDP_COMPONENT_DITHER0,
206 DDP_COMPONENT_DSI0,
207};
208
209static const unsigned int mt8192_mtk_ddp_ext[] = {
210 DDP_COMPONENT_OVL_2L2,
211 DDP_COMPONENT_RDMA4,
212 DDP_COMPONENT_DPI0,
213};
214
215static const unsigned int mt8195_mtk_ddp_main[] = {
216 DDP_COMPONENT_OVL0,
217 DDP_COMPONENT_RDMA0,
218 DDP_COMPONENT_COLOR0,
219 DDP_COMPONENT_CCORR,
220 DDP_COMPONENT_AAL0,
221 DDP_COMPONENT_GAMMA,
222 DDP_COMPONENT_DITHER0,
223 DDP_COMPONENT_DSC0,
224 DDP_COMPONENT_MERGE0,
225 DDP_COMPONENT_DP_INTF0,
226};
227
228static const unsigned int mt8195_mtk_ddp_ext[] = {
229 DDP_COMPONENT_DRM_OVL_ADAPTOR,
230 DDP_COMPONENT_MERGE5,
231 DDP_COMPONENT_DP_INTF1,
232};
233
234static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
235 .main_path = mt2701_mtk_ddp_main,
236 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
237 .ext_path = mt2701_mtk_ddp_ext,
238 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
239 .shadow_register = true,
240 .mmsys_dev_num = 1,
241};
242
243static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
244 .main_path = mt7623_mtk_ddp_main,
245 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
246 .ext_path = mt7623_mtk_ddp_ext,
247 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
248 .shadow_register = true,
249 .mmsys_dev_num = 1,
250};
251
252static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
253 .main_path = mt2712_mtk_ddp_main,
254 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
255 .ext_path = mt2712_mtk_ddp_ext,
256 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
257 .third_path = mt2712_mtk_ddp_third,
258 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
259 .mmsys_dev_num = 1,
260};
261
262static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
263 .main_path = mt8167_mtk_ddp_main,
264 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
265 .mmsys_dev_num = 1,
266};
267
268static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
269 .main_path = mt8173_mtk_ddp_main,
270 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
271 .ext_path = mt8173_mtk_ddp_ext,
272 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
273 .mmsys_dev_num = 1,
274};
275
276static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
277 .main_path = mt8183_mtk_ddp_main,
278 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
279 .ext_path = mt8183_mtk_ddp_ext,
280 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
281 .mmsys_dev_num = 1,
282};
283
284static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
285 .main_path = mt8186_mtk_ddp_main,
286 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
287 .ext_path = mt8186_mtk_ddp_ext,
288 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
289 .mmsys_dev_num = 1,
290};
291
292static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
293 .main_path = mt8188_mtk_ddp_main,
294 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
295 .conn_routes = mt8188_mtk_ddp_main_routes,
296 .num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes),
297 .mmsys_dev_num = 1,
298};
299
300static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
301 .main_path = mt8192_mtk_ddp_main,
302 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
303 .ext_path = mt8192_mtk_ddp_ext,
304 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
305 .mmsys_dev_num = 1,
306};
307
308static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
309 .main_path = mt8195_mtk_ddp_main,
310 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
311 .mmsys_dev_num = 2,
312};
313
314static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
315 .ext_path = mt8195_mtk_ddp_ext,
316 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
317 .mmsys_id = 1,
318 .mmsys_dev_num = 2,
319};
320
321static const struct of_device_id mtk_drm_of_ids[] = {
322 { .compatible = "mediatek,mt2701-mmsys",
323 .data = &mt2701_mmsys_driver_data},
324 { .compatible = "mediatek,mt7623-mmsys",
325 .data = &mt7623_mmsys_driver_data},
326 { .compatible = "mediatek,mt2712-mmsys",
327 .data = &mt2712_mmsys_driver_data},
328 { .compatible = "mediatek,mt8167-mmsys",
329 .data = &mt8167_mmsys_driver_data},
330 { .compatible = "mediatek,mt8173-mmsys",
331 .data = &mt8173_mmsys_driver_data},
332 { .compatible = "mediatek,mt8183-mmsys",
333 .data = &mt8183_mmsys_driver_data},
334 { .compatible = "mediatek,mt8186-mmsys",
335 .data = &mt8186_mmsys_driver_data},
336 { .compatible = "mediatek,mt8188-vdosys0",
337 .data = &mt8188_vdosys0_driver_data},
338 { .compatible = "mediatek,mt8192-mmsys",
339 .data = &mt8192_mmsys_driver_data},
340 { .compatible = "mediatek,mt8195-mmsys",
341 .data = &mt8195_vdosys0_driver_data},
342 { .compatible = "mediatek,mt8195-vdosys0",
343 .data = &mt8195_vdosys0_driver_data},
344 { .compatible = "mediatek,mt8195-vdosys1",
345 .data = &mt8195_vdosys1_driver_data},
346 { }
347};
348MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
349
350static int mtk_drm_match(struct device *dev, void *data)
351{
352 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1))
353 return true;
354 return false;
355}
356
357static bool mtk_drm_get_all_drm_priv(struct device *dev)
358{
359 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
360 struct mtk_drm_private *all_drm_priv[MAX_CRTC];
361 struct mtk_drm_private *temp_drm_priv;
362 struct device_node *phandle = dev->parent->of_node;
363 const struct of_device_id *of_id;
364 struct device_node *node;
365 struct device *drm_dev;
366 unsigned int cnt = 0;
367 int i, j;
368
369 for_each_child_of_node(phandle->parent, node) {
370 struct platform_device *pdev;
371
372 of_id = of_match_node(mtk_drm_of_ids, node);
373 if (!of_id)
374 continue;
375
376 pdev = of_find_device_by_node(node);
377 if (!pdev)
378 continue;
379
380 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match);
381 if (!drm_dev)
382 continue;
383
384 temp_drm_priv = dev_get_drvdata(drm_dev);
385 if (!temp_drm_priv)
386 continue;
387
388 if (temp_drm_priv->data->main_len)
389 all_drm_priv[CRTC_MAIN] = temp_drm_priv;
390 else if (temp_drm_priv->data->ext_len)
391 all_drm_priv[CRTC_EXT] = temp_drm_priv;
392 else if (temp_drm_priv->data->third_len)
393 all_drm_priv[CRTC_THIRD] = temp_drm_priv;
394
395 if (temp_drm_priv->mtk_drm_bound)
396 cnt++;
397
398 if (cnt == MAX_CRTC)
399 break;
400 }
401
402 if (drm_priv->data->mmsys_dev_num == cnt) {
403 for (i = 0; i < cnt; i++)
404 for (j = 0; j < cnt; j++)
405 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
406
407 return true;
408 }
409
410 return false;
411}
412
413static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
414{
415 const struct mtk_mmsys_driver_data *drv_data = private->data;
416 int i;
417
418 if (drv_data->main_path)
419 for (i = 0; i < drv_data->main_len; i++)
420 if (drv_data->main_path[i] == comp_id)
421 return true;
422
423 if (drv_data->ext_path)
424 for (i = 0; i < drv_data->ext_len; i++)
425 if (drv_data->ext_path[i] == comp_id)
426 return true;
427
428 if (drv_data->third_path)
429 for (i = 0; i < drv_data->third_len; i++)
430 if (drv_data->third_path[i] == comp_id)
431 return true;
432
433 if (drv_data->num_conn_routes)
434 for (i = 0; i < drv_data->num_conn_routes; i++)
435 if (drv_data->conn_routes[i].route_ddp == comp_id)
436 return true;
437
438 return false;
439}
440
441static int mtk_drm_kms_init(struct drm_device *drm)
442{
443 struct mtk_drm_private *private = drm->dev_private;
444 struct mtk_drm_private *priv_n;
445 struct device *dma_dev = NULL;
446 struct drm_crtc *crtc;
447 int ret, i, j;
448
449 if (drm_firmware_drivers_only())
450 return -ENODEV;
451
452 ret = drmm_mode_config_init(drm);
453 if (ret)
454 goto put_mutex_dev;
455
456 drm->mode_config.min_width = 64;
457 drm->mode_config.min_height = 64;
458
459 /*
460 * set max width and height as default value(4096x4096).
461 * this value would be used to check framebuffer size limitation
462 * at drm_mode_addfb().
463 */
464 drm->mode_config.max_width = 4096;
465 drm->mode_config.max_height = 4096;
466 drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
467 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
468
469 for (i = 0; i < private->data->mmsys_dev_num; i++) {
470 drm->dev_private = private->all_drm_private[i];
471 ret = component_bind_all(private->all_drm_private[i]->dev, drm);
472 if (ret)
473 goto put_mutex_dev;
474 }
475
476 /*
477 * Ensure internal panels are at the top of the connector list before
478 * crtc creation.
479 */
480 drm_helper_move_panel_connectors_to_head(drm);
481
482 /*
483 * 1. We currently support two fixed data streams, each optional,
484 * and each statically assigned to a crtc:
485 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
486 * 2. For multi mmsys architecture, crtc path data are located in
487 * different drm private data structures. Loop through crtc index to
488 * create crtc from the main path and then ext_path and finally the
489 * third path.
490 */
491 for (i = 0; i < MAX_CRTC; i++) {
492 for (j = 0; j < private->data->mmsys_dev_num; j++) {
493 priv_n = private->all_drm_private[j];
494
495 if (i == CRTC_MAIN && priv_n->data->main_len) {
496 ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
497 priv_n->data->main_len, j,
498 priv_n->data->conn_routes,
499 priv_n->data->num_conn_routes);
500 if (ret)
501 goto err_component_unbind;
502
503 continue;
504 } else if (i == CRTC_EXT && priv_n->data->ext_len) {
505 ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
506 priv_n->data->ext_len, j, NULL, 0);
507 if (ret)
508 goto err_component_unbind;
509
510 continue;
511 } else if (i == CRTC_THIRD && priv_n->data->third_len) {
512 ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
513 priv_n->data->third_len, j, NULL, 0);
514 if (ret)
515 goto err_component_unbind;
516
517 continue;
518 }
519 }
520 }
521
522 /* Use OVL device for all DMA memory allocations */
523 crtc = drm_crtc_from_index(drm, 0);
524 if (crtc)
525 dma_dev = mtk_drm_crtc_dma_dev_get(crtc);
526 if (!dma_dev) {
527 ret = -ENODEV;
528 dev_err(drm->dev, "Need at least one OVL device\n");
529 goto err_component_unbind;
530 }
531
532 for (i = 0; i < private->data->mmsys_dev_num; i++)
533 private->all_drm_private[i]->dma_dev = dma_dev;
534
535 /*
536 * Configure the DMA segment size to make sure we get contiguous IOVA
537 * when importing PRIME buffers.
538 */
539 ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
540 if (ret) {
541 dev_err(dma_dev, "Failed to set DMA segment size\n");
542 goto err_component_unbind;
543 }
544
545 ret = drm_vblank_init(drm, MAX_CRTC);
546 if (ret < 0)
547 goto err_component_unbind;
548
549 drm_kms_helper_poll_init(drm);
550 drm_mode_config_reset(drm);
551
552 return 0;
553
554err_component_unbind:
555 for (i = 0; i < private->data->mmsys_dev_num; i++)
556 component_unbind_all(private->all_drm_private[i]->dev, drm);
557put_mutex_dev:
558 for (i = 0; i < private->data->mmsys_dev_num; i++)
559 put_device(private->all_drm_private[i]->mutex_dev);
560
561 return ret;
562}
563
564static void mtk_drm_kms_deinit(struct drm_device *drm)
565{
566 drm_kms_helper_poll_fini(drm);
567 drm_atomic_helper_shutdown(drm);
568
569 component_unbind_all(drm->dev, drm);
570}
571
572DEFINE_DRM_GEM_FOPS(mtk_drm_fops);
573
574/*
575 * We need to override this because the device used to import the memory is
576 * not dev->dev, as drm_gem_prime_import() expects.
577 */
578static struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev,
579 struct dma_buf *dma_buf)
580{
581 struct mtk_drm_private *private = dev->dev_private;
582
583 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev);
584}
585
586static const struct drm_driver mtk_drm_driver = {
587 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
588
589 .dumb_create = mtk_drm_gem_dumb_create,
590
591 .gem_prime_import = mtk_drm_gem_prime_import,
592 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
593 .fops = &mtk_drm_fops,
594
595 .name = DRIVER_NAME,
596 .desc = DRIVER_DESC,
597 .date = DRIVER_DATE,
598 .major = DRIVER_MAJOR,
599 .minor = DRIVER_MINOR,
600};
601
602static int compare_dev(struct device *dev, void *data)
603{
604 return dev == (struct device *)data;
605}
606
607static int mtk_drm_bind(struct device *dev)
608{
609 struct mtk_drm_private *private = dev_get_drvdata(dev);
610 struct platform_device *pdev;
611 struct drm_device *drm;
612 int ret, i;
613
614 if (!iommu_present(&platform_bus_type))
615 return -EPROBE_DEFER;
616
617 pdev = of_find_device_by_node(private->mutex_node);
618 if (!pdev) {
619 dev_err(dev, "Waiting for disp-mutex device %pOF\n",
620 private->mutex_node);
621 of_node_put(private->mutex_node);
622 return -EPROBE_DEFER;
623 }
624
625 private->mutex_dev = &pdev->dev;
626 private->mtk_drm_bound = true;
627 private->dev = dev;
628
629 if (!mtk_drm_get_all_drm_priv(dev))
630 return 0;
631
632 drm = drm_dev_alloc(&mtk_drm_driver, dev);
633 if (IS_ERR(drm))
634 return PTR_ERR(drm);
635
636 private->drm_master = true;
637 drm->dev_private = private;
638 for (i = 0; i < private->data->mmsys_dev_num; i++)
639 private->all_drm_private[i]->drm = drm;
640
641 ret = mtk_drm_kms_init(drm);
642 if (ret < 0)
643 goto err_free;
644
645 ret = drm_dev_register(drm, 0);
646 if (ret < 0)
647 goto err_deinit;
648
649 drm_fbdev_generic_setup(drm, 32);
650
651 return 0;
652
653err_deinit:
654 mtk_drm_kms_deinit(drm);
655err_free:
656 private->drm = NULL;
657 drm_dev_put(drm);
658 return ret;
659}
660
661static void mtk_drm_unbind(struct device *dev)
662{
663 struct mtk_drm_private *private = dev_get_drvdata(dev);
664
665 /* for multi mmsys dev, unregister drm dev in mmsys master */
666 if (private->drm_master) {
667 drm_dev_unregister(private->drm);
668 mtk_drm_kms_deinit(private->drm);
669 drm_dev_put(private->drm);
670 }
671 private->mtk_drm_bound = false;
672 private->drm_master = false;
673 private->drm = NULL;
674}
675
676static const struct component_master_ops mtk_drm_ops = {
677 .bind = mtk_drm_bind,
678 .unbind = mtk_drm_unbind,
679};
680
681static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
682 { .compatible = "mediatek,mt8167-disp-aal",
683 .data = (void *)MTK_DISP_AAL},
684 { .compatible = "mediatek,mt8173-disp-aal",
685 .data = (void *)MTK_DISP_AAL},
686 { .compatible = "mediatek,mt8183-disp-aal",
687 .data = (void *)MTK_DISP_AAL},
688 { .compatible = "mediatek,mt8192-disp-aal",
689 .data = (void *)MTK_DISP_AAL},
690 { .compatible = "mediatek,mt8167-disp-ccorr",
691 .data = (void *)MTK_DISP_CCORR },
692 { .compatible = "mediatek,mt8183-disp-ccorr",
693 .data = (void *)MTK_DISP_CCORR },
694 { .compatible = "mediatek,mt8192-disp-ccorr",
695 .data = (void *)MTK_DISP_CCORR },
696 { .compatible = "mediatek,mt2701-disp-color",
697 .data = (void *)MTK_DISP_COLOR },
698 { .compatible = "mediatek,mt8167-disp-color",
699 .data = (void *)MTK_DISP_COLOR },
700 { .compatible = "mediatek,mt8173-disp-color",
701 .data = (void *)MTK_DISP_COLOR },
702 { .compatible = "mediatek,mt8167-disp-dither",
703 .data = (void *)MTK_DISP_DITHER },
704 { .compatible = "mediatek,mt8183-disp-dither",
705 .data = (void *)MTK_DISP_DITHER },
706 { .compatible = "mediatek,mt8195-disp-dsc",
707 .data = (void *)MTK_DISP_DSC },
708 { .compatible = "mediatek,mt8167-disp-gamma",
709 .data = (void *)MTK_DISP_GAMMA, },
710 { .compatible = "mediatek,mt8173-disp-gamma",
711 .data = (void *)MTK_DISP_GAMMA, },
712 { .compatible = "mediatek,mt8183-disp-gamma",
713 .data = (void *)MTK_DISP_GAMMA, },
714 { .compatible = "mediatek,mt8195-disp-merge",
715 .data = (void *)MTK_DISP_MERGE },
716 { .compatible = "mediatek,mt2701-disp-mutex",
717 .data = (void *)MTK_DISP_MUTEX },
718 { .compatible = "mediatek,mt2712-disp-mutex",
719 .data = (void *)MTK_DISP_MUTEX },
720 { .compatible = "mediatek,mt8167-disp-mutex",
721 .data = (void *)MTK_DISP_MUTEX },
722 { .compatible = "mediatek,mt8173-disp-mutex",
723 .data = (void *)MTK_DISP_MUTEX },
724 { .compatible = "mediatek,mt8183-disp-mutex",
725 .data = (void *)MTK_DISP_MUTEX },
726 { .compatible = "mediatek,mt8186-disp-mutex",
727 .data = (void *)MTK_DISP_MUTEX },
728 { .compatible = "mediatek,mt8188-disp-mutex",
729 .data = (void *)MTK_DISP_MUTEX },
730 { .compatible = "mediatek,mt8192-disp-mutex",
731 .data = (void *)MTK_DISP_MUTEX },
732 { .compatible = "mediatek,mt8195-disp-mutex",
733 .data = (void *)MTK_DISP_MUTEX },
734 { .compatible = "mediatek,mt8173-disp-od",
735 .data = (void *)MTK_DISP_OD },
736 { .compatible = "mediatek,mt2701-disp-ovl",
737 .data = (void *)MTK_DISP_OVL },
738 { .compatible = "mediatek,mt8167-disp-ovl",
739 .data = (void *)MTK_DISP_OVL },
740 { .compatible = "mediatek,mt8173-disp-ovl",
741 .data = (void *)MTK_DISP_OVL },
742 { .compatible = "mediatek,mt8183-disp-ovl",
743 .data = (void *)MTK_DISP_OVL },
744 { .compatible = "mediatek,mt8192-disp-ovl",
745 .data = (void *)MTK_DISP_OVL },
746 { .compatible = "mediatek,mt8183-disp-ovl-2l",
747 .data = (void *)MTK_DISP_OVL_2L },
748 { .compatible = "mediatek,mt8192-disp-ovl-2l",
749 .data = (void *)MTK_DISP_OVL_2L },
750 { .compatible = "mediatek,mt8192-disp-postmask",
751 .data = (void *)MTK_DISP_POSTMASK },
752 { .compatible = "mediatek,mt2701-disp-pwm",
753 .data = (void *)MTK_DISP_BLS },
754 { .compatible = "mediatek,mt8167-disp-pwm",
755 .data = (void *)MTK_DISP_PWM },
756 { .compatible = "mediatek,mt8173-disp-pwm",
757 .data = (void *)MTK_DISP_PWM },
758 { .compatible = "mediatek,mt2701-disp-rdma",
759 .data = (void *)MTK_DISP_RDMA },
760 { .compatible = "mediatek,mt8167-disp-rdma",
761 .data = (void *)MTK_DISP_RDMA },
762 { .compatible = "mediatek,mt8173-disp-rdma",
763 .data = (void *)MTK_DISP_RDMA },
764 { .compatible = "mediatek,mt8183-disp-rdma",
765 .data = (void *)MTK_DISP_RDMA },
766 { .compatible = "mediatek,mt8195-disp-rdma",
767 .data = (void *)MTK_DISP_RDMA },
768 { .compatible = "mediatek,mt8173-disp-ufoe",
769 .data = (void *)MTK_DISP_UFOE },
770 { .compatible = "mediatek,mt8173-disp-wdma",
771 .data = (void *)MTK_DISP_WDMA },
772 { .compatible = "mediatek,mt2701-dpi",
773 .data = (void *)MTK_DPI },
774 { .compatible = "mediatek,mt8167-dsi",
775 .data = (void *)MTK_DSI },
776 { .compatible = "mediatek,mt8173-dpi",
777 .data = (void *)MTK_DPI },
778 { .compatible = "mediatek,mt8183-dpi",
779 .data = (void *)MTK_DPI },
780 { .compatible = "mediatek,mt8186-dpi",
781 .data = (void *)MTK_DPI },
782 { .compatible = "mediatek,mt8188-dp-intf",
783 .data = (void *)MTK_DP_INTF },
784 { .compatible = "mediatek,mt8192-dpi",
785 .data = (void *)MTK_DPI },
786 { .compatible = "mediatek,mt8195-dp-intf",
787 .data = (void *)MTK_DP_INTF },
788 { .compatible = "mediatek,mt2701-dsi",
789 .data = (void *)MTK_DSI },
790 { .compatible = "mediatek,mt8173-dsi",
791 .data = (void *)MTK_DSI },
792 { .compatible = "mediatek,mt8183-dsi",
793 .data = (void *)MTK_DSI },
794 { .compatible = "mediatek,mt8186-dsi",
795 .data = (void *)MTK_DSI },
796 { .compatible = "mediatek,mt8188-dsi",
797 .data = (void *)MTK_DSI },
798 { }
799};
800
801static int mtk_drm_probe(struct platform_device *pdev)
802{
803 struct device *dev = &pdev->dev;
804 struct device_node *phandle = dev->parent->of_node;
805 const struct of_device_id *of_id;
806 struct mtk_drm_private *private;
807 struct device_node *node;
808 struct component_match *match = NULL;
809 struct platform_device *ovl_adaptor;
810 int ret;
811 int i;
812
813 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
814 if (!private)
815 return -ENOMEM;
816
817 private->mmsys_dev = dev->parent;
818 if (!private->mmsys_dev) {
819 dev_err(dev, "Failed to get MMSYS device\n");
820 return -ENODEV;
821 }
822
823 of_id = of_match_node(mtk_drm_of_ids, phandle);
824 if (!of_id)
825 return -ENODEV;
826
827 private->data = of_id->data;
828
829 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num,
830 sizeof(*private->all_drm_private),
831 GFP_KERNEL);
832 if (!private->all_drm_private)
833 return -ENOMEM;
834
835 /* Bringup ovl_adaptor */
836 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) {
837 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",
838 PLATFORM_DEVID_AUTO,
839 (void *)private->mmsys_dev,
840 sizeof(*private->mmsys_dev));
841 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev;
842 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR],
843 DDP_COMPONENT_DRM_OVL_ADAPTOR);
844 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev);
845 }
846
847 /* Iterate over sibling DISP function blocks */
848 for_each_child_of_node(phandle->parent, node) {
849 const struct of_device_id *of_id;
850 enum mtk_ddp_comp_type comp_type;
851 int comp_id;
852
853 of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
854 if (!of_id)
855 continue;
856
857 if (!of_device_is_available(node)) {
858 dev_dbg(dev, "Skipping disabled component %pOF\n",
859 node);
860 continue;
861 }
862
863 comp_type = (enum mtk_ddp_comp_type)(uintptr_t)of_id->data;
864
865 if (comp_type == MTK_DISP_MUTEX) {
866 int id;
867
868 id = of_alias_get_id(node, "mutex");
869 if (id < 0 || id == private->data->mmsys_id) {
870 private->mutex_node = of_node_get(node);
871 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id);
872 }
873 continue;
874 }
875
876 comp_id = mtk_ddp_comp_get_id(node, comp_type);
877 if (comp_id < 0) {
878 dev_warn(dev, "Skipping unknown component %pOF\n",
879 node);
880 continue;
881 }
882
883 if (!mtk_drm_find_mmsys_comp(private, comp_id))
884 continue;
885
886 private->comp_node[comp_id] = of_node_get(node);
887
888 /*
889 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
890 * blocks have separate component platform drivers and initialize their own
891 * DDP component structure. The others are initialized here.
892 */
893 if (comp_type == MTK_DISP_AAL ||
894 comp_type == MTK_DISP_CCORR ||
895 comp_type == MTK_DISP_COLOR ||
896 comp_type == MTK_DISP_GAMMA ||
897 comp_type == MTK_DISP_MERGE ||
898 comp_type == MTK_DISP_OVL ||
899 comp_type == MTK_DISP_OVL_2L ||
900 comp_type == MTK_DISP_OVL_ADAPTOR ||
901 comp_type == MTK_DISP_RDMA ||
902 comp_type == MTK_DP_INTF ||
903 comp_type == MTK_DPI ||
904 comp_type == MTK_DSI) {
905 dev_info(dev, "Adding component match for %pOF\n",
906 node);
907 drm_of_component_match_add(dev, &match, component_compare_of,
908 node);
909 }
910
911 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id);
912 if (ret) {
913 of_node_put(node);
914 goto err_node;
915 }
916 }
917
918 if (!private->mutex_node) {
919 dev_err(dev, "Failed to find disp-mutex node\n");
920 ret = -ENODEV;
921 goto err_node;
922 }
923
924 pm_runtime_enable(dev);
925
926 platform_set_drvdata(pdev, private);
927
928 ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
929 if (ret)
930 goto err_pm;
931
932 return 0;
933
934err_pm:
935 pm_runtime_disable(dev);
936err_node:
937 of_node_put(private->mutex_node);
938 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
939 of_node_put(private->comp_node[i]);
940 return ret;
941}
942
943static void mtk_drm_remove(struct platform_device *pdev)
944{
945 struct mtk_drm_private *private = platform_get_drvdata(pdev);
946 int i;
947
948 component_master_del(&pdev->dev, &mtk_drm_ops);
949 pm_runtime_disable(&pdev->dev);
950 of_node_put(private->mutex_node);
951 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
952 of_node_put(private->comp_node[i]);
953}
954
955static int mtk_drm_sys_prepare(struct device *dev)
956{
957 struct mtk_drm_private *private = dev_get_drvdata(dev);
958 struct drm_device *drm = private->drm;
959
960 if (private->drm_master)
961 return drm_mode_config_helper_suspend(drm);
962 else
963 return 0;
964}
965
966static void mtk_drm_sys_complete(struct device *dev)
967{
968 struct mtk_drm_private *private = dev_get_drvdata(dev);
969 struct drm_device *drm = private->drm;
970 int ret = 0;
971
972 if (private->drm_master)
973 ret = drm_mode_config_helper_resume(drm);
974 if (ret)
975 dev_err(dev, "Failed to resume\n");
976}
977
978static const struct dev_pm_ops mtk_drm_pm_ops = {
979 .prepare = mtk_drm_sys_prepare,
980 .complete = mtk_drm_sys_complete,
981};
982
983static struct platform_driver mtk_drm_platform_driver = {
984 .probe = mtk_drm_probe,
985 .remove_new = mtk_drm_remove,
986 .driver = {
987 .name = "mediatek-drm",
988 .pm = &mtk_drm_pm_ops,
989 },
990};
991
992static struct platform_driver * const mtk_drm_drivers[] = {
993 &mtk_disp_aal_driver,
994 &mtk_disp_ccorr_driver,
995 &mtk_disp_color_driver,
996 &mtk_disp_gamma_driver,
997 &mtk_disp_merge_driver,
998 &mtk_disp_ovl_adaptor_driver,
999 &mtk_disp_ovl_driver,
1000 &mtk_disp_rdma_driver,
1001 &mtk_dpi_driver,
1002 &mtk_drm_platform_driver,
1003 &mtk_dsi_driver,
1004 &mtk_ethdr_driver,
1005 &mtk_mdp_rdma_driver,
1006};
1007
1008static int __init mtk_drm_init(void)
1009{
1010 return platform_register_drivers(mtk_drm_drivers,
1011 ARRAY_SIZE(mtk_drm_drivers));
1012}
1013
1014static void __exit mtk_drm_exit(void)
1015{
1016 platform_unregister_drivers(mtk_drm_drivers,
1017 ARRAY_SIZE(mtk_drm_drivers));
1018}
1019
1020module_init(mtk_drm_init);
1021module_exit(mtk_drm_exit);
1022
1023MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
1024MODULE_DESCRIPTION("Mediatek SoC DRM driver");
1025MODULE_LICENSE("GPL v2");