tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef __AMDGPU_MCA_H__
22#define __AMDGPU_MCA_H__
23
24#include "amdgpu_ras.h"
25
26#define MCA_MAX_REGS_COUNT (16)
27
28#define MCA_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> l)
29#define MCA_REG__STATUS__VAL(x) MCA_REG_FIELD(x, 63, 63)
30#define MCA_REG__STATUS__OVERFLOW(x) MCA_REG_FIELD(x, 62, 62)
31#define MCA_REG__STATUS__UC(x) MCA_REG_FIELD(x, 61, 61)
32#define MCA_REG__STATUS__EN(x) MCA_REG_FIELD(x, 60, 60)
33#define MCA_REG__STATUS__MISCV(x) MCA_REG_FIELD(x, 59, 59)
34#define MCA_REG__STATUS__ADDRV(x) MCA_REG_FIELD(x, 58, 58)
35#define MCA_REG__STATUS__PCC(x) MCA_REG_FIELD(x, 57, 57)
36#define MCA_REG__STATUS__ERRCOREIDVAL(x) MCA_REG_FIELD(x, 56, 56)
37#define MCA_REG__STATUS__TCC(x) MCA_REG_FIELD(x, 55, 55)
38#define MCA_REG__STATUS__SYNDV(x) MCA_REG_FIELD(x, 53, 53)
39#define MCA_REG__STATUS__CECC(x) MCA_REG_FIELD(x, 46, 46)
40#define MCA_REG__STATUS__UECC(x) MCA_REG_FIELD(x, 45, 45)
41#define MCA_REG__STATUS__DEFERRED(x) MCA_REG_FIELD(x, 44, 44)
42#define MCA_REG__STATUS__POISON(x) MCA_REG_FIELD(x, 43, 43)
43#define MCA_REG__STATUS__SCRUB(x) MCA_REG_FIELD(x, 40, 40)
44#define MCA_REG__STATUS__ERRCOREID(x) MCA_REG_FIELD(x, 37, 32)
45#define MCA_REG__STATUS__ADDRLSB(x) MCA_REG_FIELD(x, 29, 24)
46#define MCA_REG__STATUS__ERRORCODEEXT(x) MCA_REG_FIELD(x, 21, 16)
47#define MCA_REG__STATUS__ERRORCODE(x) MCA_REG_FIELD(x, 15, 0)
48
49enum amdgpu_mca_ip {
50 AMDGPU_MCA_IP_UNKNOW = -1,
51 AMDGPU_MCA_IP_PSP = 0,
52 AMDGPU_MCA_IP_SDMA,
53 AMDGPU_MCA_IP_GC,
54 AMDGPU_MCA_IP_SMU,
55 AMDGPU_MCA_IP_MP5,
56 AMDGPU_MCA_IP_UMC,
57 AMDGPU_MCA_IP_PCS_XGMI,
58 AMDGPU_MCA_IP_COUNT,
59};
60
61enum amdgpu_mca_error_type {
62 AMDGPU_MCA_ERROR_TYPE_UE = 0,
63 AMDGPU_MCA_ERROR_TYPE_CE,
64};
65
66struct amdgpu_mca_ras_block {
67 struct amdgpu_ras_block_object ras_block;
68};
69
70struct amdgpu_mca_ras {
71 struct ras_common_if *ras_if;
72 struct amdgpu_mca_ras_block *ras;
73};
74
75struct amdgpu_mca {
76 struct amdgpu_mca_ras mp0;
77 struct amdgpu_mca_ras mp1;
78 struct amdgpu_mca_ras mpio;
79 const struct amdgpu_mca_smu_funcs *mca_funcs;
80};
81
82enum mca_reg_idx {
83 MCA_REG_IDX_STATUS = 1,
84 MCA_REG_IDX_ADDR = 2,
85 MCA_REG_IDX_MISC0 = 3,
86 MCA_REG_IDX_IPID = 5,
87 MCA_REG_IDX_SYND = 6,
88 MCA_REG_IDX_COUNT = 16,
89};
90
91struct mca_bank_info {
92 int socket_id;
93 int aid;
94 int hwid;
95 int mcatype;
96};
97
98struct mca_bank_entry {
99 int idx;
100 enum amdgpu_mca_error_type type;
101 enum amdgpu_mca_ip ip;
102 struct mca_bank_info info;
103 uint64_t regs[MCA_MAX_REGS_COUNT];
104};
105
106struct mca_bank_node {
107 struct mca_bank_entry entry;
108 struct list_head node;
109};
110
111struct mca_bank_set {
112 int nr_entries;
113 struct list_head list;
114};
115
116struct amdgpu_mca_smu_funcs {
117 int max_ue_count;
118 int max_ce_count;
119 int (*mca_set_debug_mode)(struct amdgpu_device *adev, bool enable);
120 int (*mca_get_ras_mca_set)(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
121 struct mca_bank_set *mca_set);
122 int (*mca_parse_mca_error_count)(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
123 struct mca_bank_entry *entry, uint32_t *count);
124 int (*mca_get_valid_mca_count)(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
125 uint32_t *count);
126 int (*mca_get_mca_entry)(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
127 int idx, struct mca_bank_entry *entry);
128};
129
130void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev,
131 uint64_t mc_status_addr,
132 unsigned long *error_count);
133
134void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev,
135 uint64_t mc_status_addr,
136 unsigned long *error_count);
137
138void amdgpu_mca_reset_error_count(struct amdgpu_device *adev,
139 uint64_t mc_status_addr);
140
141void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,
142 uint64_t mc_status_addr,
143 void *ras_error_status);
144int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev);
145int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev);
146int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev);
147
148void amdgpu_mca_smu_init_funcs(struct amdgpu_device *adev, const struct amdgpu_mca_smu_funcs *mca_funcs);
149int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable);
150int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count);
151int amdgpu_mca_smu_get_mca_set_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
152 enum amdgpu_mca_error_type type, uint32_t *total);
153int amdgpu_mca_smu_get_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
154 enum amdgpu_mca_error_type type, uint32_t *count);
155int amdgpu_mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
156 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);
157int amdgpu_mca_smu_get_mca_set(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
158 enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set);
159int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
160 int idx, struct mca_bank_entry *entry);
161
162void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root);
163
164void amdgpu_mca_bank_set_init(struct mca_bank_set *mca_set);
165int amdgpu_mca_bank_set_add_entry(struct mca_bank_set *mca_set, struct mca_bank_entry *entry);
166void amdgpu_mca_bank_set_release(struct mca_bank_set *mca_set);
167int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, struct ras_err_data *err_data);
168
169#endif