tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx Versal clock controller
8
9maintainers:
10 - Michal Simek <michal.simek@amd.com>
11
12description: |
13 The clock controller is a hardware block of Xilinx versal clock tree. It
14 reads required input clock frequencies from the devicetree and acts as clock
15 provider for all clock consumers of PS clocks.
16
17properties:
18 compatible:
19 oneOf:
20 - enum:
21 - xlnx,versal-clk
22 - xlnx,zynqmp-clk
23 - items:
24 - enum:
25 - xlnx,versal-net-clk
26 - const: xlnx,versal-clk
27
28 "#clock-cells":
29 const: 1
30
31 clocks:
32 description: List of clock specifiers which are external input
33 clocks to the given clock controller.
34 minItems: 3
35 maxItems: 8
36
37 clock-names:
38 minItems: 3
39 maxItems: 8
40
41required:
42 - compatible
43 - "#clock-cells"
44 - clocks
45 - clock-names
46
47additionalProperties: false
48
49allOf:
50 - if:
51 properties:
52 compatible:
53 contains:
54 enum:
55 - xlnx,versal-clk
56
57 then:
58 properties:
59 clocks:
60 items:
61 - description: reference clock
62 - description: alternate reference clock
63 - description: alternate reference clock for programmable logic
64
65 clock-names:
66 items:
67 - const: ref
68 - const: alt_ref
69 - const: pl_alt_ref
70
71 - if:
72 properties:
73 compatible:
74 contains:
75 enum:
76 - xlnx,zynqmp-clk
77
78 then:
79 properties:
80 clocks:
81 minItems: 5
82 items:
83 - description: PS reference clock
84 - description: reference clock for video system
85 - description: alternative PS reference clock
86 - description: auxiliary reference clock
87 - description: transceiver reference clock
88 - description: (E)MIO clock source (Optional clock)
89 - description: GEM emio clock (Optional clock)
90 - description: Watchdog external clock (Optional clock)
91
92 clock-names:
93 minItems: 5
94 items:
95 - const: pss_ref_clk
96 - const: video_clk
97 - const: pss_alt_ref_clk
98 - const: aux_ref_clk
99 - const: gt_crx_ref_clk
100 - pattern: "^mio_clk[00-77]+.*$"
101 - pattern: "gem[0-3]+_emio_clk.*$"
102 - pattern: "swdt[0-1]+_ext_clk.*$"
103
104examples:
105 - |
106 firmware {
107 zynqmp_firmware: zynqmp-firmware {
108 compatible = "xlnx,zynqmp-firmware";
109 method = "smc";
110 versal_clk: clock-controller {
111 #clock-cells = <1>;
112 compatible = "xlnx,versal-clk";
113 clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
114 clock-names = "ref", "alt_ref", "pl_alt_ref";
115 };
116 };
117 };
118
119 clock-controller {
120 #clock-cells = <1>;
121 compatible = "xlnx,zynqmp-clk";
122 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
123 <&aux_ref_clk>, <>_crx_ref_clk>;
124 clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
125 "aux_ref_clk", "gt_crx_ref_clk";
126 };
127...