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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef DRIVERS_PCI_H
3#define DRIVERS_PCI_H
4
5#include <linux/pci.h>
6
7/* Number of possible devfns: 0.0 to 1f.7 inclusive */
8#define MAX_NR_DEVFNS 256
9
10#define PCI_FIND_CAP_TTL 48
11
12#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
13
14#define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
15
16/*
17 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
18 * Recommends 1ms to 10ms timeout to check L2 ready.
19 */
20#define PCIE_PME_TO_L2_TIMEOUT_US 10000
21
22extern const unsigned char pcie_link_speed[];
23extern bool pci_early_dump;
24
25bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
26bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
27bool pcie_cap_has_rtctl(const struct pci_dev *dev);
28
29/* Functions internal to the PCI core code */
30
31int pci_create_sysfs_dev_files(struct pci_dev *pdev);
32void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
33void pci_cleanup_rom(struct pci_dev *dev);
34#ifdef CONFIG_DMI
35extern const struct attribute_group pci_dev_smbios_attr_group;
36#endif
37
38enum pci_mmap_api {
39 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
40 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
41};
42int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
43 enum pci_mmap_api mmap_api);
44
45bool pci_reset_supported(struct pci_dev *dev);
46void pci_init_reset_methods(struct pci_dev *dev);
47int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
48int pci_bus_error_reset(struct pci_dev *dev);
49
50struct pci_cap_saved_data {
51 u16 cap_nr;
52 bool cap_extended;
53 unsigned int size;
54 u32 data[];
55};
56
57struct pci_cap_saved_state {
58 struct hlist_node next;
59 struct pci_cap_saved_data cap;
60};
61
62void pci_allocate_cap_save_buffers(struct pci_dev *dev);
63void pci_free_cap_save_buffers(struct pci_dev *dev);
64int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
65int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
66 u16 cap, unsigned int size);
67struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
68struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
69 u16 cap);
70
71#define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
72#define PCI_PM_D3HOT_WAIT 10 /* msec */
73#define PCI_PM_D3COLD_WAIT 100 /* msec */
74
75void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
76void pci_refresh_power_state(struct pci_dev *dev);
77int pci_power_up(struct pci_dev *dev);
78void pci_disable_enabled_device(struct pci_dev *dev);
79int pci_finish_runtime_suspend(struct pci_dev *dev);
80void pcie_clear_device_status(struct pci_dev *dev);
81void pcie_clear_root_pme_status(struct pci_dev *dev);
82bool pci_check_pme_status(struct pci_dev *dev);
83void pci_pme_wakeup_bus(struct pci_bus *bus);
84int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
85void pci_pme_restore(struct pci_dev *dev);
86bool pci_dev_need_resume(struct pci_dev *dev);
87void pci_dev_adjust_pme(struct pci_dev *dev);
88void pci_dev_complete_resume(struct pci_dev *pci_dev);
89void pci_config_pm_runtime_get(struct pci_dev *dev);
90void pci_config_pm_runtime_put(struct pci_dev *dev);
91void pci_pm_init(struct pci_dev *dev);
92void pci_ea_init(struct pci_dev *dev);
93void pci_msi_init(struct pci_dev *dev);
94void pci_msix_init(struct pci_dev *dev);
95bool pci_bridge_d3_possible(struct pci_dev *dev);
96void pci_bridge_d3_update(struct pci_dev *dev);
97void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
98int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
99
100static inline void pci_wakeup_event(struct pci_dev *dev)
101{
102 /* Wait 100 ms before the system can be put into a sleep state. */
103 pm_wakeup_event(&dev->dev, 100);
104}
105
106static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
107{
108 return !!(pci_dev->subordinate);
109}
110
111static inline bool pci_power_manageable(struct pci_dev *pci_dev)
112{
113 /*
114 * Currently we allow normal PCI devices and PCI bridges transition
115 * into D3 if their bridge_d3 is set.
116 */
117 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
118}
119
120static inline bool pcie_downstream_port(const struct pci_dev *dev)
121{
122 int type = pci_pcie_type(dev);
123
124 return type == PCI_EXP_TYPE_ROOT_PORT ||
125 type == PCI_EXP_TYPE_DOWNSTREAM ||
126 type == PCI_EXP_TYPE_PCIE_BRIDGE;
127}
128
129void pci_vpd_init(struct pci_dev *dev);
130void pci_vpd_release(struct pci_dev *dev);
131extern const struct attribute_group pci_dev_vpd_attr_group;
132
133/* PCI Virtual Channel */
134int pci_save_vc_state(struct pci_dev *dev);
135void pci_restore_vc_state(struct pci_dev *dev);
136void pci_allocate_vc_save_buffers(struct pci_dev *dev);
137
138/* PCI /proc functions */
139#ifdef CONFIG_PROC_FS
140int pci_proc_attach_device(struct pci_dev *dev);
141int pci_proc_detach_device(struct pci_dev *dev);
142int pci_proc_detach_bus(struct pci_bus *bus);
143#else
144static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
145static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
146static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
147#endif
148
149/* Functions for PCI Hotplug drivers to use */
150int pci_hp_add_bridge(struct pci_dev *dev);
151
152#ifdef HAVE_PCI_LEGACY
153void pci_create_legacy_files(struct pci_bus *bus);
154void pci_remove_legacy_files(struct pci_bus *bus);
155#else
156static inline void pci_create_legacy_files(struct pci_bus *bus) { }
157static inline void pci_remove_legacy_files(struct pci_bus *bus) { }
158#endif
159
160/* Lock for read/write access to pci device and bus lists */
161extern struct rw_semaphore pci_bus_sem;
162extern struct mutex pci_slot_mutex;
163
164extern raw_spinlock_t pci_lock;
165
166extern unsigned int pci_pm_d3hot_delay;
167
168#ifdef CONFIG_PCI_MSI
169void pci_no_msi(void);
170#else
171static inline void pci_no_msi(void) { }
172#endif
173
174void pci_realloc_get_opt(char *);
175
176static inline int pci_no_d1d2(struct pci_dev *dev)
177{
178 unsigned int parent_dstates = 0;
179
180 if (dev->bus->self)
181 parent_dstates = dev->bus->self->no_d1d2;
182 return (dev->no_d1d2 || parent_dstates);
183
184}
185extern const struct attribute_group *pci_dev_groups[];
186extern const struct attribute_group *pcibus_groups[];
187extern const struct device_type pci_dev_type;
188extern const struct attribute_group *pci_bus_groups[];
189
190extern unsigned long pci_hotplug_io_size;
191extern unsigned long pci_hotplug_mmio_size;
192extern unsigned long pci_hotplug_mmio_pref_size;
193extern unsigned long pci_hotplug_bus_size;
194
195/**
196 * pci_match_one_device - Tell if a PCI device structure has a matching
197 * PCI device id structure
198 * @id: single PCI device id structure to match
199 * @dev: the PCI device structure to match against
200 *
201 * Returns the matching pci_device_id structure or %NULL if there is no match.
202 */
203static inline const struct pci_device_id *
204pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
205{
206 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
207 (id->device == PCI_ANY_ID || id->device == dev->device) &&
208 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
209 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
210 !((id->class ^ dev->class) & id->class_mask))
211 return id;
212 return NULL;
213}
214
215/* PCI slot sysfs helper code */
216#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
217
218extern struct kset *pci_slots_kset;
219
220struct pci_slot_attribute {
221 struct attribute attr;
222 ssize_t (*show)(struct pci_slot *, char *);
223 ssize_t (*store)(struct pci_slot *, const char *, size_t);
224};
225#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
226
227enum pci_bar_type {
228 pci_bar_unknown, /* Standard PCI BAR probe */
229 pci_bar_io, /* An I/O port BAR */
230 pci_bar_mem32, /* A 32-bit memory BAR */
231 pci_bar_mem64, /* A 64-bit memory BAR */
232};
233
234struct device *pci_get_host_bridge_device(struct pci_dev *dev);
235void pci_put_host_bridge_device(struct device *dev);
236
237int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
238bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
239 int crs_timeout);
240bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
241 int crs_timeout);
242int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
243
244int pci_setup_device(struct pci_dev *dev);
245int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
246 struct resource *res, unsigned int reg);
247void pci_configure_ari(struct pci_dev *dev);
248void __pci_bus_size_bridges(struct pci_bus *bus,
249 struct list_head *realloc_head);
250void __pci_bus_assign_resources(const struct pci_bus *bus,
251 struct list_head *realloc_head,
252 struct list_head *fail_head);
253bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
254
255void pci_reassigndev_resource_alignment(struct pci_dev *dev);
256void pci_disable_bridge_window(struct pci_dev *dev);
257struct pci_bus *pci_bus_get(struct pci_bus *bus);
258void pci_bus_put(struct pci_bus *bus);
259
260/* PCIe link information from Link Capabilities 2 */
261#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
262 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
263 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
264 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
265 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
266 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
267 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
268 PCI_SPEED_UNKNOWN)
269
270/* PCIe speed to Mb/s reduced by encoding overhead */
271#define PCIE_SPEED2MBS_ENC(speed) \
272 ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \
273 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
274 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
275 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
276 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
277 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
278 0)
279
280const char *pci_speed_string(enum pci_bus_speed speed);
281enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
282enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
283u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
284 enum pcie_link_width *width);
285void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
286void pcie_report_downtraining(struct pci_dev *dev);
287void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
288
289/* Single Root I/O Virtualization */
290struct pci_sriov {
291 int pos; /* Capability position */
292 int nres; /* Number of resources */
293 u32 cap; /* SR-IOV Capabilities */
294 u16 ctrl; /* SR-IOV Control */
295 u16 total_VFs; /* Total VFs associated with the PF */
296 u16 initial_VFs; /* Initial VFs associated with the PF */
297 u16 num_VFs; /* Number of VFs available */
298 u16 offset; /* First VF Routing ID offset */
299 u16 stride; /* Following VF stride */
300 u16 vf_device; /* VF device ID */
301 u32 pgsz; /* Page size for BAR alignment */
302 u8 link; /* Function Dependency Link */
303 u8 max_VF_buses; /* Max buses consumed by VFs */
304 u16 driver_max_VFs; /* Max num VFs driver supports */
305 struct pci_dev *dev; /* Lowest numbered PF */
306 struct pci_dev *self; /* This PF */
307 u32 class; /* VF device */
308 u8 hdr_type; /* VF header type */
309 u16 subsystem_vendor; /* VF subsystem vendor */
310 u16 subsystem_device; /* VF subsystem device */
311 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
312 bool drivers_autoprobe; /* Auto probing of VFs by driver */
313};
314
315#ifdef CONFIG_PCI_DOE
316void pci_doe_init(struct pci_dev *pdev);
317void pci_doe_destroy(struct pci_dev *pdev);
318void pci_doe_disconnected(struct pci_dev *pdev);
319#else
320static inline void pci_doe_init(struct pci_dev *pdev) { }
321static inline void pci_doe_destroy(struct pci_dev *pdev) { }
322static inline void pci_doe_disconnected(struct pci_dev *pdev) { }
323#endif
324
325/**
326 * pci_dev_set_io_state - Set the new error state if possible.
327 *
328 * @dev: PCI device to set new error_state
329 * @new: the state we want dev to be in
330 *
331 * If the device is experiencing perm_failure, it has to remain in that state.
332 * Any other transition is allowed.
333 *
334 * Returns true if state has been changed to the requested state.
335 */
336static inline bool pci_dev_set_io_state(struct pci_dev *dev,
337 pci_channel_state_t new)
338{
339 pci_channel_state_t old;
340
341 switch (new) {
342 case pci_channel_io_perm_failure:
343 xchg(&dev->error_state, pci_channel_io_perm_failure);
344 return true;
345 case pci_channel_io_frozen:
346 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
347 pci_channel_io_frozen);
348 return old != pci_channel_io_perm_failure;
349 case pci_channel_io_normal:
350 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
351 pci_channel_io_normal);
352 return old != pci_channel_io_perm_failure;
353 default:
354 return false;
355 }
356}
357
358static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
359{
360 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
361 pci_doe_disconnected(dev);
362
363 return 0;
364}
365
366static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
367{
368 return dev->error_state == pci_channel_io_perm_failure;
369}
370
371/* pci_dev priv_flags */
372#define PCI_DEV_ADDED 0
373#define PCI_DPC_RECOVERED 1
374#define PCI_DPC_RECOVERING 2
375
376static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
377{
378 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
379}
380
381static inline bool pci_dev_is_added(const struct pci_dev *dev)
382{
383 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
384}
385
386#ifdef CONFIG_PCIEAER
387#include <linux/aer.h>
388
389#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
390
391struct aer_err_info {
392 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
393 int error_dev_num;
394
395 unsigned int id:16;
396
397 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
398 unsigned int __pad1:5;
399 unsigned int multi_error_valid:1;
400
401 unsigned int first_error:5;
402 unsigned int __pad2:2;
403 unsigned int tlp_header_valid:1;
404
405 unsigned int status; /* COR/UNCOR Error Status */
406 unsigned int mask; /* COR/UNCOR Error Mask */
407 struct aer_header_log_regs tlp; /* TLP Header */
408};
409
410int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
411void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
412#endif /* CONFIG_PCIEAER */
413
414#ifdef CONFIG_PCIEPORTBUS
415/* Cached RCEC Endpoint Association */
416struct rcec_ea {
417 u8 nextbusn;
418 u8 lastbusn;
419 u32 bitmap;
420};
421#endif
422
423#ifdef CONFIG_PCIE_DPC
424void pci_save_dpc_state(struct pci_dev *dev);
425void pci_restore_dpc_state(struct pci_dev *dev);
426void pci_dpc_init(struct pci_dev *pdev);
427void dpc_process_error(struct pci_dev *pdev);
428pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
429bool pci_dpc_recovered(struct pci_dev *pdev);
430#else
431static inline void pci_save_dpc_state(struct pci_dev *dev) { }
432static inline void pci_restore_dpc_state(struct pci_dev *dev) { }
433static inline void pci_dpc_init(struct pci_dev *pdev) { }
434static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
435#endif
436
437#ifdef CONFIG_PCIEPORTBUS
438void pci_rcec_init(struct pci_dev *dev);
439void pci_rcec_exit(struct pci_dev *dev);
440void pcie_link_rcec(struct pci_dev *rcec);
441void pcie_walk_rcec(struct pci_dev *rcec,
442 int (*cb)(struct pci_dev *, void *),
443 void *userdata);
444#else
445static inline void pci_rcec_init(struct pci_dev *dev) { }
446static inline void pci_rcec_exit(struct pci_dev *dev) { }
447static inline void pcie_link_rcec(struct pci_dev *rcec) { }
448static inline void pcie_walk_rcec(struct pci_dev *rcec,
449 int (*cb)(struct pci_dev *, void *),
450 void *userdata) { }
451#endif
452
453#ifdef CONFIG_PCI_ATS
454/* Address Translation Service */
455void pci_ats_init(struct pci_dev *dev);
456void pci_restore_ats_state(struct pci_dev *dev);
457#else
458static inline void pci_ats_init(struct pci_dev *d) { }
459static inline void pci_restore_ats_state(struct pci_dev *dev) { }
460#endif /* CONFIG_PCI_ATS */
461
462#ifdef CONFIG_PCI_PRI
463void pci_pri_init(struct pci_dev *dev);
464void pci_restore_pri_state(struct pci_dev *pdev);
465#else
466static inline void pci_pri_init(struct pci_dev *dev) { }
467static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
468#endif
469
470#ifdef CONFIG_PCI_PASID
471void pci_pasid_init(struct pci_dev *dev);
472void pci_restore_pasid_state(struct pci_dev *pdev);
473#else
474static inline void pci_pasid_init(struct pci_dev *dev) { }
475static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
476#endif
477
478#ifdef CONFIG_PCI_IOV
479int pci_iov_init(struct pci_dev *dev);
480void pci_iov_release(struct pci_dev *dev);
481void pci_iov_remove(struct pci_dev *dev);
482void pci_iov_update_resource(struct pci_dev *dev, int resno);
483resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
484void pci_restore_iov_state(struct pci_dev *dev);
485int pci_iov_bus_range(struct pci_bus *bus);
486extern const struct attribute_group sriov_pf_dev_attr_group;
487extern const struct attribute_group sriov_vf_dev_attr_group;
488#else
489static inline int pci_iov_init(struct pci_dev *dev)
490{
491 return -ENODEV;
492}
493static inline void pci_iov_release(struct pci_dev *dev) { }
494static inline void pci_iov_remove(struct pci_dev *dev) { }
495static inline void pci_restore_iov_state(struct pci_dev *dev) { }
496static inline int pci_iov_bus_range(struct pci_bus *bus)
497{
498 return 0;
499}
500
501#endif /* CONFIG_PCI_IOV */
502
503#ifdef CONFIG_PCIE_PTM
504void pci_ptm_init(struct pci_dev *dev);
505void pci_save_ptm_state(struct pci_dev *dev);
506void pci_restore_ptm_state(struct pci_dev *dev);
507void pci_suspend_ptm(struct pci_dev *dev);
508void pci_resume_ptm(struct pci_dev *dev);
509#else
510static inline void pci_ptm_init(struct pci_dev *dev) { }
511static inline void pci_save_ptm_state(struct pci_dev *dev) { }
512static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
513static inline void pci_suspend_ptm(struct pci_dev *dev) { }
514static inline void pci_resume_ptm(struct pci_dev *dev) { }
515#endif
516
517unsigned long pci_cardbus_resource_alignment(struct resource *);
518
519static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
520 struct resource *res)
521{
522#ifdef CONFIG_PCI_IOV
523 int resno = res - dev->resource;
524
525 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
526 return pci_sriov_resource_alignment(dev, resno);
527#endif
528 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
529 return pci_cardbus_resource_alignment(res);
530 return resource_alignment(res);
531}
532
533void pci_acs_init(struct pci_dev *dev);
534#ifdef CONFIG_PCI_QUIRKS
535int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
536int pci_dev_specific_enable_acs(struct pci_dev *dev);
537int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
538bool pcie_failed_link_retrain(struct pci_dev *dev);
539#else
540static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
541 u16 acs_flags)
542{
543 return -ENOTTY;
544}
545static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
546{
547 return -ENOTTY;
548}
549static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
550{
551 return -ENOTTY;
552}
553static inline bool pcie_failed_link_retrain(struct pci_dev *dev)
554{
555 return false;
556}
557#endif
558
559/* PCI error reporting and recovery */
560pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
561 pci_channel_state_t state,
562 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
563
564bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
565int pcie_retrain_link(struct pci_dev *pdev, bool use_lt);
566#ifdef CONFIG_PCIEASPM
567void pcie_aspm_init_link_state(struct pci_dev *pdev);
568void pcie_aspm_exit_link_state(struct pci_dev *pdev);
569void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
570#else
571static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
572static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
573static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
574#endif
575
576#ifdef CONFIG_PCIE_ECRC
577void pcie_set_ecrc_checking(struct pci_dev *dev);
578void pcie_ecrc_get_policy(char *str);
579#else
580static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
581static inline void pcie_ecrc_get_policy(char *str) { }
582#endif
583
584struct pci_dev_reset_methods {
585 u16 vendor;
586 u16 device;
587 int (*reset)(struct pci_dev *dev, bool probe);
588};
589
590struct pci_reset_fn_method {
591 int (*reset_fn)(struct pci_dev *pdev, bool probe);
592 char *name;
593};
594
595#ifdef CONFIG_PCI_QUIRKS
596int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
597#else
598static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
599{
600 return -ENOTTY;
601}
602#endif
603
604#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
605int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
606 struct resource *res);
607#else
608static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
609 u16 segment, struct resource *res)
610{
611 return -ENODEV;
612}
613#endif
614
615int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
616int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
617static inline u64 pci_rebar_size_to_bytes(int size)
618{
619 return 1ULL << (size + 20);
620}
621
622struct device_node;
623
624#ifdef CONFIG_OF
625int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
626int of_get_pci_domain_nr(struct device_node *node);
627int of_pci_get_max_link_speed(struct device_node *node);
628u32 of_pci_get_slot_power_limit(struct device_node *node,
629 u8 *slot_power_limit_value,
630 u8 *slot_power_limit_scale);
631int pci_set_of_node(struct pci_dev *dev);
632void pci_release_of_node(struct pci_dev *dev);
633void pci_set_bus_of_node(struct pci_bus *bus);
634void pci_release_bus_of_node(struct pci_bus *bus);
635
636int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
637
638#else
639static inline int
640of_pci_parse_bus_range(struct device_node *node, struct resource *res)
641{
642 return -EINVAL;
643}
644
645static inline int
646of_get_pci_domain_nr(struct device_node *node)
647{
648 return -1;
649}
650
651static inline int
652of_pci_get_max_link_speed(struct device_node *node)
653{
654 return -EINVAL;
655}
656
657static inline u32
658of_pci_get_slot_power_limit(struct device_node *node,
659 u8 *slot_power_limit_value,
660 u8 *slot_power_limit_scale)
661{
662 if (slot_power_limit_value)
663 *slot_power_limit_value = 0;
664 if (slot_power_limit_scale)
665 *slot_power_limit_scale = 0;
666 return 0;
667}
668
669static inline int pci_set_of_node(struct pci_dev *dev) { return 0; }
670static inline void pci_release_of_node(struct pci_dev *dev) { }
671static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
672static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
673
674static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
675{
676 return 0;
677}
678
679#endif /* CONFIG_OF */
680
681struct of_changeset;
682
683#ifdef CONFIG_PCI_DYNAMIC_OF_NODES
684void of_pci_make_dev_node(struct pci_dev *pdev);
685void of_pci_remove_node(struct pci_dev *pdev);
686int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
687 struct device_node *np);
688#else
689static inline void of_pci_make_dev_node(struct pci_dev *pdev) { }
690static inline void of_pci_remove_node(struct pci_dev *pdev) { }
691#endif
692
693#ifdef CONFIG_PCIEAER
694void pci_no_aer(void);
695void pci_aer_init(struct pci_dev *dev);
696void pci_aer_exit(struct pci_dev *dev);
697extern const struct attribute_group aer_stats_attr_group;
698void pci_aer_clear_fatal_status(struct pci_dev *dev);
699int pci_aer_clear_status(struct pci_dev *dev);
700int pci_aer_raw_clear_status(struct pci_dev *dev);
701void pci_save_aer_state(struct pci_dev *dev);
702void pci_restore_aer_state(struct pci_dev *dev);
703#else
704static inline void pci_no_aer(void) { }
705static inline void pci_aer_init(struct pci_dev *d) { }
706static inline void pci_aer_exit(struct pci_dev *d) { }
707static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
708static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
709static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
710static inline void pci_save_aer_state(struct pci_dev *dev) { }
711static inline void pci_restore_aer_state(struct pci_dev *dev) { }
712#endif
713
714#ifdef CONFIG_ACPI
715int pci_acpi_program_hp_params(struct pci_dev *dev);
716extern const struct attribute_group pci_dev_acpi_attr_group;
717void pci_set_acpi_fwnode(struct pci_dev *dev);
718int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
719bool acpi_pci_power_manageable(struct pci_dev *dev);
720bool acpi_pci_bridge_d3(struct pci_dev *dev);
721int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
722pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
723void acpi_pci_refresh_power_state(struct pci_dev *dev);
724int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
725bool acpi_pci_need_resume(struct pci_dev *dev);
726pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
727#else
728static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
729{
730 return -ENOTTY;
731}
732static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { }
733static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
734{
735 return -ENODEV;
736}
737static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
738{
739 return false;
740}
741static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
742{
743 return false;
744}
745static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
746{
747 return -ENODEV;
748}
749static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
750{
751 return PCI_UNKNOWN;
752}
753static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { }
754static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
755{
756 return -ENODEV;
757}
758static inline bool acpi_pci_need_resume(struct pci_dev *dev)
759{
760 return false;
761}
762static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
763{
764 return PCI_POWER_ERROR;
765}
766#endif
767
768#ifdef CONFIG_PCIEASPM
769extern const struct attribute_group aspm_ctrl_attr_group;
770#endif
771
772extern const struct attribute_group pci_dev_reset_method_attr_group;
773
774#ifdef CONFIG_X86_INTEL_MID
775bool pci_use_mid_pm(void);
776int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
777pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
778#else
779static inline bool pci_use_mid_pm(void)
780{
781 return false;
782}
783static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
784{
785 return -ENODEV;
786}
787static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
788{
789 return PCI_UNKNOWN;
790}
791#endif
792
793/*
794 * Config Address for PCI Configuration Mechanism #1
795 *
796 * See PCI Local Bus Specification, Revision 3.0,
797 * Section 3.2.2.3.2, Figure 3-2, p. 50.
798 */
799
800#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
801#define PCI_CONF1_DEV_SHIFT 11 /* Device number */
802#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
803
804#define PCI_CONF1_BUS_MASK 0xff
805#define PCI_CONF1_DEV_MASK 0x1f
806#define PCI_CONF1_FUNC_MASK 0x7
807#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
808
809#define PCI_CONF1_ENABLE BIT(31)
810#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
811#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
812#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
813#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
814
815#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
816 (PCI_CONF1_ENABLE | \
817 PCI_CONF1_BUS(bus) | \
818 PCI_CONF1_DEV(dev) | \
819 PCI_CONF1_FUNC(func) | \
820 PCI_CONF1_REG(reg))
821
822/*
823 * Extension of PCI Config Address for accessing extended PCIe registers
824 *
825 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
826 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
827 * are used for specifying additional 4 high bits of PCI Express register.
828 */
829
830#define PCI_CONF1_EXT_REG_SHIFT 16
831#define PCI_CONF1_EXT_REG_MASK 0xf00
832#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
833
834#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
835 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
836 PCI_CONF1_EXT_REG(reg))
837
838#endif /* DRIVERS_PCI_H */