tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare XPCS helpers
5 *
6 * Author: Jose Abreu <Jose.Abreu@synopsys.com>
7 */
8
9#define SYNOPSYS_XPCS_ID 0x7996ced0
10#define SYNOPSYS_XPCS_MASK 0xffffffff
11
12/* Vendor regs access */
13#define DW_VENDOR BIT(15)
14
15/* VR_XS_PCS */
16#define DW_USXGMII_RST BIT(10)
17#define DW_USXGMII_EN BIT(9)
18#define DW_VR_XS_PCS_DIG_CTRL1 0x0000
19#define DW_VR_RST BIT(15)
20#define DW_EN_VSMMD1 BIT(13)
21#define DW_CL37_BP BIT(12)
22#define DW_VR_XS_PCS_DIG_STS 0x0010
23#define DW_RXFIFO_ERR GENMASK(6, 5)
24#define DW_PSEQ_ST GENMASK(4, 2)
25#define DW_PSEQ_ST_GOOD FIELD_PREP(GENMASK(4, 2), 0x4)
26
27/* SR_MII */
28#define DW_USXGMII_FULL BIT(8)
29#define DW_USXGMII_SS_MASK (BIT(13) | BIT(6) | BIT(5))
30#define DW_USXGMII_10000 (BIT(13) | BIT(6))
31#define DW_USXGMII_5000 (BIT(13) | BIT(5))
32#define DW_USXGMII_2500 (BIT(5))
33#define DW_USXGMII_1000 (BIT(6))
34#define DW_USXGMII_100 (BIT(13))
35#define DW_USXGMII_10 (0)
36
37/* SR_AN */
38#define DW_SR_AN_ADV1 0x10
39#define DW_SR_AN_ADV2 0x11
40#define DW_SR_AN_ADV3 0x12
41
42/* Clause 73 Defines */
43/* AN_LP_ABL1 */
44#define DW_C73_PAUSE BIT(10)
45#define DW_C73_ASYM_PAUSE BIT(11)
46#define DW_C73_AN_ADV_SF 0x1
47/* AN_LP_ABL2 */
48#define DW_C73_1000KX BIT(5)
49#define DW_C73_10000KX4 BIT(6)
50#define DW_C73_10000KR BIT(7)
51/* AN_LP_ABL3 */
52#define DW_C73_2500KX BIT(0)
53#define DW_C73_5000KR BIT(1)
54
55/* Clause 37 Defines */
56/* VR MII MMD registers offsets */
57#define DW_VR_MII_MMD_CTRL 0x0000
58#define DW_VR_MII_DIG_CTRL1 0x8000
59#define DW_VR_MII_AN_CTRL 0x8001
60#define DW_VR_MII_AN_INTR_STS 0x8002
61/* Enable 2.5G Mode */
62#define DW_VR_MII_DIG_CTRL1_2G5_EN BIT(2)
63/* EEE Mode Control Register */
64#define DW_VR_MII_EEE_MCTRL0 0x8006
65#define DW_VR_MII_EEE_MCTRL1 0x800b
66#define DW_VR_MII_DIG_CTRL2 0x80e1
67
68/* VR_MII_DIG_CTRL1 */
69#define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW BIT(9)
70#define DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL BIT(0)
71
72/* VR_MII_DIG_CTRL2 */
73#define DW_VR_MII_DIG_CTRL2_TX_POL_INV BIT(4)
74#define DW_VR_MII_DIG_CTRL2_RX_POL_INV BIT(0)
75
76/* VR_MII_AN_CTRL */
77#define DW_VR_MII_AN_CTRL_8BIT BIT(8)
78#define DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT 3
79#define DW_VR_MII_TX_CONFIG_MASK BIT(3)
80#define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII 0x1
81#define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII 0x0
82#define DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT 1
83#define DW_VR_MII_PCS_MODE_MASK GENMASK(2, 1)
84#define DW_VR_MII_PCS_MODE_C37_1000BASEX 0x0
85#define DW_VR_MII_PCS_MODE_C37_SGMII 0x2
86#define DW_VR_MII_AN_INTR_EN BIT(0)
87
88/* VR_MII_AN_INTR_STS */
89#define DW_VR_MII_AN_STS_C37_ANCMPLT_INTR BIT(0)
90#define DW_VR_MII_AN_STS_C37_ANSGM_FD BIT(1)
91#define DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT 2
92#define DW_VR_MII_AN_STS_C37_ANSGM_SP GENMASK(3, 2)
93#define DW_VR_MII_C37_ANSGM_SP_10 0x0
94#define DW_VR_MII_C37_ANSGM_SP_100 0x1
95#define DW_VR_MII_C37_ANSGM_SP_1000 0x2
96#define DW_VR_MII_C37_ANSGM_SP_LNKSTS BIT(4)
97
98/* SR MII MMD Control defines */
99#define AN_CL37_EN BIT(12) /* Enable Clause 37 auto-nego */
100#define SGMII_SPEED_SS13 BIT(13) /* SGMII speed along with SS6 */
101#define SGMII_SPEED_SS6 BIT(6) /* SGMII speed along with SS13 */
102
103/* SR MII MMD AN Advertisement defines */
104#define DW_HALF_DUPLEX BIT(6)
105#define DW_FULL_DUPLEX BIT(5)
106
107/* VR MII EEE Control 0 defines */
108#define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */
109#define DW_VR_MII_EEE_LRX_EN BIT(1) /* LPI Rx Enable */
110#define DW_VR_MII_EEE_TX_QUIET_EN BIT(2) /* Tx Quiet Enable */
111#define DW_VR_MII_EEE_RX_QUIET_EN BIT(3) /* Rx Quiet Enable */
112#define DW_VR_MII_EEE_TX_EN_CTRL BIT(4) /* Tx Control Enable */
113#define DW_VR_MII_EEE_RX_EN_CTRL BIT(7) /* Rx Control Enable */
114
115#define DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT 8
116#define DW_VR_MII_EEE_MULT_FACT_100NS GENMASK(11, 8)
117
118/* VR MII EEE Control 1 defines */
119#define DW_VR_MII_EEE_TRN_LPI BIT(0) /* Transparent Mode Enable */
120
121int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg);
122int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val);
123int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg);
124int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val);
125int nxp_sja1105_sgmii_pma_config(struct dw_xpcs *xpcs);
126int nxp_sja1110_sgmii_pma_config(struct dw_xpcs *xpcs);
127int nxp_sja1110_2500basex_pma_config(struct dw_xpcs *xpcs);
128int txgbe_xpcs_switch_mode(struct dw_xpcs *xpcs, phy_interface_t interface);