tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Pinctrl / GPIO driver for StarFive JH7110 SoC sys controller
4 *
5 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
6 * Copyright (C) 2022 StarFive Technology Co., Ltd.
7 */
8
9#include <linux/bits.h>
10#include <linux/clk.h>
11#include <linux/gpio/driver.h>
12#include <linux/io.h>
13#include <linux/mod_devicetable.h>
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <linux/platform_device.h>
17#include <linux/reset.h>
18#include <linux/spinlock.h>
19
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
22
23#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
24
25#include "../core.h"
26#include "../pinctrl-utils.h"
27#include "../pinmux.h"
28#include "../pinconf.h"
29#include "pinctrl-starfive-jh7110.h"
30
31#define JH7110_SYS_NGPIO 64
32#define JH7110_SYS_GC_BASE 0
33
34/* registers */
35#define JH7110_SYS_DOEN 0x000
36#define JH7110_SYS_DOUT 0x040
37#define JH7110_SYS_GPI 0x080
38#define JH7110_SYS_GPIOIN 0x118
39
40#define JH7110_SYS_GPIOEN 0x0dc
41#define JH7110_SYS_GPIOIS0 0x0e0
42#define JH7110_SYS_GPIOIS1 0x0e4
43#define JH7110_SYS_GPIOIC0 0x0e8
44#define JH7110_SYS_GPIOIC1 0x0ec
45#define JH7110_SYS_GPIOIBE0 0x0f0
46#define JH7110_SYS_GPIOIBE1 0x0f4
47#define JH7110_SYS_GPIOIEV0 0x0f8
48#define JH7110_SYS_GPIOIEV1 0x0fc
49#define JH7110_SYS_GPIOIE0 0x100
50#define JH7110_SYS_GPIOIE1 0x104
51#define JH7110_SYS_GPIORIS0 0x108
52#define JH7110_SYS_GPIORIS1 0x10c
53#define JH7110_SYS_GPIOMIS0 0x110
54#define JH7110_SYS_GPIOMIS1 0x114
55
56#define JH7110_SYS_GPO_PDA_0_74_CFG 0x120
57#define JH7110_SYS_GPO_PDA_89_94_CFG 0x284
58
59static const struct pinctrl_pin_desc jh7110_sys_pins[] = {
60 PINCTRL_PIN(PAD_GPIO0, "GPIO0"),
61 PINCTRL_PIN(PAD_GPIO1, "GPIO1"),
62 PINCTRL_PIN(PAD_GPIO2, "GPIO2"),
63 PINCTRL_PIN(PAD_GPIO3, "GPIO3"),
64 PINCTRL_PIN(PAD_GPIO4, "GPIO4"),
65 PINCTRL_PIN(PAD_GPIO5, "GPIO5"),
66 PINCTRL_PIN(PAD_GPIO6, "GPIO6"),
67 PINCTRL_PIN(PAD_GPIO7, "GPIO7"),
68 PINCTRL_PIN(PAD_GPIO8, "GPIO8"),
69 PINCTRL_PIN(PAD_GPIO9, "GPIO9"),
70 PINCTRL_PIN(PAD_GPIO10, "GPIO10"),
71 PINCTRL_PIN(PAD_GPIO11, "GPIO11"),
72 PINCTRL_PIN(PAD_GPIO12, "GPIO12"),
73 PINCTRL_PIN(PAD_GPIO13, "GPIO13"),
74 PINCTRL_PIN(PAD_GPIO14, "GPIO14"),
75 PINCTRL_PIN(PAD_GPIO15, "GPIO15"),
76 PINCTRL_PIN(PAD_GPIO16, "GPIO16"),
77 PINCTRL_PIN(PAD_GPIO17, "GPIO17"),
78 PINCTRL_PIN(PAD_GPIO18, "GPIO18"),
79 PINCTRL_PIN(PAD_GPIO19, "GPIO19"),
80 PINCTRL_PIN(PAD_GPIO20, "GPIO20"),
81 PINCTRL_PIN(PAD_GPIO21, "GPIO21"),
82 PINCTRL_PIN(PAD_GPIO22, "GPIO22"),
83 PINCTRL_PIN(PAD_GPIO23, "GPIO23"),
84 PINCTRL_PIN(PAD_GPIO24, "GPIO24"),
85 PINCTRL_PIN(PAD_GPIO25, "GPIO25"),
86 PINCTRL_PIN(PAD_GPIO26, "GPIO26"),
87 PINCTRL_PIN(PAD_GPIO27, "GPIO27"),
88 PINCTRL_PIN(PAD_GPIO28, "GPIO28"),
89 PINCTRL_PIN(PAD_GPIO29, "GPIO29"),
90 PINCTRL_PIN(PAD_GPIO30, "GPIO30"),
91 PINCTRL_PIN(PAD_GPIO31, "GPIO31"),
92 PINCTRL_PIN(PAD_GPIO32, "GPIO32"),
93 PINCTRL_PIN(PAD_GPIO33, "GPIO33"),
94 PINCTRL_PIN(PAD_GPIO34, "GPIO34"),
95 PINCTRL_PIN(PAD_GPIO35, "GPIO35"),
96 PINCTRL_PIN(PAD_GPIO36, "GPIO36"),
97 PINCTRL_PIN(PAD_GPIO37, "GPIO37"),
98 PINCTRL_PIN(PAD_GPIO38, "GPIO38"),
99 PINCTRL_PIN(PAD_GPIO39, "GPIO39"),
100 PINCTRL_PIN(PAD_GPIO40, "GPIO40"),
101 PINCTRL_PIN(PAD_GPIO41, "GPIO41"),
102 PINCTRL_PIN(PAD_GPIO42, "GPIO42"),
103 PINCTRL_PIN(PAD_GPIO43, "GPIO43"),
104 PINCTRL_PIN(PAD_GPIO44, "GPIO44"),
105 PINCTRL_PIN(PAD_GPIO45, "GPIO45"),
106 PINCTRL_PIN(PAD_GPIO46, "GPIO46"),
107 PINCTRL_PIN(PAD_GPIO47, "GPIO47"),
108 PINCTRL_PIN(PAD_GPIO48, "GPIO48"),
109 PINCTRL_PIN(PAD_GPIO49, "GPIO49"),
110 PINCTRL_PIN(PAD_GPIO50, "GPIO50"),
111 PINCTRL_PIN(PAD_GPIO51, "GPIO51"),
112 PINCTRL_PIN(PAD_GPIO52, "GPIO52"),
113 PINCTRL_PIN(PAD_GPIO53, "GPIO53"),
114 PINCTRL_PIN(PAD_GPIO54, "GPIO54"),
115 PINCTRL_PIN(PAD_GPIO55, "GPIO55"),
116 PINCTRL_PIN(PAD_GPIO56, "GPIO56"),
117 PINCTRL_PIN(PAD_GPIO57, "GPIO57"),
118 PINCTRL_PIN(PAD_GPIO58, "GPIO58"),
119 PINCTRL_PIN(PAD_GPIO59, "GPIO59"),
120 PINCTRL_PIN(PAD_GPIO60, "GPIO60"),
121 PINCTRL_PIN(PAD_GPIO61, "GPIO61"),
122 PINCTRL_PIN(PAD_GPIO62, "GPIO62"),
123 PINCTRL_PIN(PAD_GPIO63, "GPIO63"),
124 PINCTRL_PIN(PAD_SD0_CLK, "SD0_CLK"),
125 PINCTRL_PIN(PAD_SD0_CMD, "SD0_CMD"),
126 PINCTRL_PIN(PAD_SD0_DATA0, "SD0_DATA0"),
127 PINCTRL_PIN(PAD_SD0_DATA1, "SD0_DATA1"),
128 PINCTRL_PIN(PAD_SD0_DATA2, "SD0_DATA2"),
129 PINCTRL_PIN(PAD_SD0_DATA3, "SD0_DATA3"),
130 PINCTRL_PIN(PAD_SD0_DATA4, "SD0_DATA4"),
131 PINCTRL_PIN(PAD_SD0_DATA5, "SD0_DATA5"),
132 PINCTRL_PIN(PAD_SD0_DATA6, "SD0_DATA6"),
133 PINCTRL_PIN(PAD_SD0_DATA7, "SD0_DATA7"),
134 PINCTRL_PIN(PAD_SD0_STRB, "SD0_STRB"),
135 PINCTRL_PIN(PAD_GMAC1_MDC, "GMAC1_MDC"),
136 PINCTRL_PIN(PAD_GMAC1_MDIO, "GMAC1_MDIO"),
137 PINCTRL_PIN(PAD_GMAC1_RXD0, "GMAC1_RXD0"),
138 PINCTRL_PIN(PAD_GMAC1_RXD1, "GMAC1_RXD1"),
139 PINCTRL_PIN(PAD_GMAC1_RXD2, "GMAC1_RXD2"),
140 PINCTRL_PIN(PAD_GMAC1_RXD3, "GMAC1_RXD3"),
141 PINCTRL_PIN(PAD_GMAC1_RXDV, "GMAC1_RXDV"),
142 PINCTRL_PIN(PAD_GMAC1_RXC, "GMAC1_RXC"),
143 PINCTRL_PIN(PAD_GMAC1_TXD0, "GMAC1_TXD0"),
144 PINCTRL_PIN(PAD_GMAC1_TXD1, "GMAC1_TXD1"),
145 PINCTRL_PIN(PAD_GMAC1_TXD2, "GMAC1_TXD2"),
146 PINCTRL_PIN(PAD_GMAC1_TXD3, "GMAC1_TXD3"),
147 PINCTRL_PIN(PAD_GMAC1_TXEN, "GMAC1_TXEN"),
148 PINCTRL_PIN(PAD_GMAC1_TXC, "GMAC1_TXC"),
149 PINCTRL_PIN(PAD_QSPI_SCLK, "QSPI_SCLK"),
150 PINCTRL_PIN(PAD_QSPI_CS0, "QSPI_CS0"),
151 PINCTRL_PIN(PAD_QSPI_DATA0, "QSPI_DATA0"),
152 PINCTRL_PIN(PAD_QSPI_DATA1, "QSPI_DATA1"),
153 PINCTRL_PIN(PAD_QSPI_DATA2, "QSPI_DATA2"),
154 PINCTRL_PIN(PAD_QSPI_DATA3, "QSPI_DATA3"),
155};
156
157struct jh7110_func_sel {
158 u16 offset;
159 u8 shift;
160 u8 max;
161};
162
163static const struct jh7110_func_sel
164 jh7110_sys_func_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
165 [PAD_GMAC1_RXC] = { 0x29c, 0, 1 },
166 [PAD_GPIO10] = { 0x29c, 2, 3 },
167 [PAD_GPIO11] = { 0x29c, 5, 3 },
168 [PAD_GPIO12] = { 0x29c, 8, 3 },
169 [PAD_GPIO13] = { 0x29c, 11, 3 },
170 [PAD_GPIO14] = { 0x29c, 14, 3 },
171 [PAD_GPIO15] = { 0x29c, 17, 3 },
172 [PAD_GPIO16] = { 0x29c, 20, 3 },
173 [PAD_GPIO17] = { 0x29c, 23, 3 },
174 [PAD_GPIO18] = { 0x29c, 26, 3 },
175 [PAD_GPIO19] = { 0x29c, 29, 3 },
176
177 [PAD_GPIO20] = { 0x2a0, 0, 3 },
178 [PAD_GPIO21] = { 0x2a0, 3, 3 },
179 [PAD_GPIO22] = { 0x2a0, 6, 3 },
180 [PAD_GPIO23] = { 0x2a0, 9, 3 },
181 [PAD_GPIO24] = { 0x2a0, 12, 3 },
182 [PAD_GPIO25] = { 0x2a0, 15, 3 },
183 [PAD_GPIO26] = { 0x2a0, 18, 3 },
184 [PAD_GPIO27] = { 0x2a0, 21, 3 },
185 [PAD_GPIO28] = { 0x2a0, 24, 3 },
186 [PAD_GPIO29] = { 0x2a0, 27, 3 },
187
188 [PAD_GPIO30] = { 0x2a4, 0, 3 },
189 [PAD_GPIO31] = { 0x2a4, 3, 3 },
190 [PAD_GPIO32] = { 0x2a4, 6, 3 },
191 [PAD_GPIO33] = { 0x2a4, 9, 3 },
192 [PAD_GPIO34] = { 0x2a4, 12, 3 },
193 [PAD_GPIO35] = { 0x2a4, 15, 3 },
194 [PAD_GPIO36] = { 0x2a4, 17, 3 },
195 [PAD_GPIO37] = { 0x2a4, 20, 3 },
196 [PAD_GPIO38] = { 0x2a4, 23, 3 },
197 [PAD_GPIO39] = { 0x2a4, 26, 3 },
198 [PAD_GPIO40] = { 0x2a4, 29, 3 },
199
200 [PAD_GPIO41] = { 0x2a8, 0, 3 },
201 [PAD_GPIO42] = { 0x2a8, 3, 3 },
202 [PAD_GPIO43] = { 0x2a8, 6, 3 },
203 [PAD_GPIO44] = { 0x2a8, 9, 3 },
204 [PAD_GPIO45] = { 0x2a8, 12, 3 },
205 [PAD_GPIO46] = { 0x2a8, 15, 3 },
206 [PAD_GPIO47] = { 0x2a8, 18, 3 },
207 [PAD_GPIO48] = { 0x2a8, 21, 3 },
208 [PAD_GPIO49] = { 0x2a8, 24, 3 },
209 [PAD_GPIO50] = { 0x2a8, 27, 3 },
210 [PAD_GPIO51] = { 0x2a8, 30, 3 },
211
212 [PAD_GPIO52] = { 0x2ac, 0, 3 },
213 [PAD_GPIO53] = { 0x2ac, 2, 3 },
214 [PAD_GPIO54] = { 0x2ac, 4, 3 },
215 [PAD_GPIO55] = { 0x2ac, 6, 3 },
216 [PAD_GPIO56] = { 0x2ac, 9, 3 },
217 [PAD_GPIO57] = { 0x2ac, 12, 3 },
218 [PAD_GPIO58] = { 0x2ac, 15, 3 },
219 [PAD_GPIO59] = { 0x2ac, 18, 3 },
220 [PAD_GPIO60] = { 0x2ac, 21, 3 },
221 [PAD_GPIO61] = { 0x2ac, 24, 3 },
222 [PAD_GPIO62] = { 0x2ac, 27, 3 },
223 [PAD_GPIO63] = { 0x2ac, 30, 3 },
224
225 [PAD_GPIO6] = { 0x2b0, 0, 3 },
226 [PAD_GPIO7] = { 0x2b0, 2, 3 },
227 [PAD_GPIO8] = { 0x2b0, 5, 3 },
228 [PAD_GPIO9] = { 0x2b0, 8, 3 },
229};
230
231struct jh7110_vin_group_sel {
232 u16 offset;
233 u8 shift;
234 u8 group;
235};
236
237static const struct jh7110_vin_group_sel
238 jh7110_sys_vin_group_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
239 [PAD_GPIO6] = { 0x2b4, 21, 0 },
240 [PAD_GPIO7] = { 0x2b4, 18, 0 },
241 [PAD_GPIO8] = { 0x2b4, 15, 0 },
242 [PAD_GPIO9] = { 0x2b0, 11, 0 },
243 [PAD_GPIO10] = { 0x2b0, 20, 0 },
244 [PAD_GPIO11] = { 0x2b0, 23, 0 },
245 [PAD_GPIO12] = { 0x2b0, 26, 0 },
246 [PAD_GPIO13] = { 0x2b0, 29, 0 },
247 [PAD_GPIO14] = { 0x2b4, 0, 0 },
248 [PAD_GPIO15] = { 0x2b4, 3, 0 },
249 [PAD_GPIO16] = { 0x2b4, 6, 0 },
250 [PAD_GPIO17] = { 0x2b4, 9, 0 },
251 [PAD_GPIO18] = { 0x2b4, 12, 0 },
252 [PAD_GPIO19] = { 0x2b0, 14, 0 },
253 [PAD_GPIO20] = { 0x2b0, 17, 0 },
254
255 [PAD_GPIO21] = { 0x2b4, 21, 1 },
256 [PAD_GPIO22] = { 0x2b4, 18, 1 },
257 [PAD_GPIO23] = { 0x2b4, 15, 1 },
258 [PAD_GPIO24] = { 0x2b0, 11, 1 },
259 [PAD_GPIO25] = { 0x2b0, 20, 1 },
260 [PAD_GPIO26] = { 0x2b0, 23, 1 },
261 [PAD_GPIO27] = { 0x2b0, 26, 1 },
262 [PAD_GPIO28] = { 0x2b0, 29, 1 },
263 [PAD_GPIO29] = { 0x2b4, 0, 1 },
264 [PAD_GPIO30] = { 0x2b4, 3, 1 },
265 [PAD_GPIO31] = { 0x2b4, 6, 1 },
266 [PAD_GPIO32] = { 0x2b4, 9, 1 },
267 [PAD_GPIO33] = { 0x2b4, 12, 1 },
268 [PAD_GPIO34] = { 0x2b0, 14, 1 },
269 [PAD_GPIO35] = { 0x2b0, 17, 1 },
270
271 [PAD_GPIO36] = { 0x2b4, 21, 2 },
272 [PAD_GPIO37] = { 0x2b4, 18, 2 },
273 [PAD_GPIO38] = { 0x2b4, 15, 2 },
274 [PAD_GPIO39] = { 0x2b0, 11, 2 },
275 [PAD_GPIO40] = { 0x2b0, 20, 2 },
276 [PAD_GPIO41] = { 0x2b0, 23, 2 },
277 [PAD_GPIO42] = { 0x2b0, 26, 2 },
278 [PAD_GPIO43] = { 0x2b0, 29, 2 },
279 [PAD_GPIO44] = { 0x2b4, 0, 2 },
280 [PAD_GPIO45] = { 0x2b4, 3, 2 },
281 [PAD_GPIO46] = { 0x2b4, 6, 2 },
282 [PAD_GPIO47] = { 0x2b4, 9, 2 },
283 [PAD_GPIO48] = { 0x2b4, 12, 2 },
284 [PAD_GPIO49] = { 0x2b0, 14, 2 },
285 [PAD_GPIO50] = { 0x2b0, 17, 2 },
286};
287
288static void jh7110_set_function(struct jh7110_pinctrl *sfp,
289 unsigned int pin, u32 func)
290{
291 const struct jh7110_func_sel *fs = &jh7110_sys_func_sel[pin];
292 unsigned long flags;
293 void __iomem *reg;
294 u32 mask;
295
296 if (!fs->offset)
297 return;
298
299 if (func > fs->max)
300 return;
301
302 reg = sfp->base + fs->offset;
303 func = func << fs->shift;
304 mask = 0x3U << fs->shift;
305
306 raw_spin_lock_irqsave(&sfp->lock, flags);
307 func |= readl_relaxed(reg) & ~mask;
308 writel_relaxed(func, reg);
309 raw_spin_unlock_irqrestore(&sfp->lock, flags);
310}
311
312static void jh7110_set_vin_group(struct jh7110_pinctrl *sfp,
313 unsigned int pin)
314{
315 const struct jh7110_vin_group_sel *gs = &jh7110_sys_vin_group_sel[pin];
316 unsigned long flags;
317 void __iomem *reg;
318 u32 mask;
319 u32 grp;
320
321 if (!gs->offset)
322 return;
323
324 reg = sfp->base + gs->offset;
325 grp = gs->group << gs->shift;
326 mask = 0x3U << gs->shift;
327
328 raw_spin_lock_irqsave(&sfp->lock, flags);
329 grp |= readl_relaxed(reg) & ~mask;
330 writel_relaxed(grp, reg);
331 raw_spin_unlock_irqrestore(&sfp->lock, flags);
332}
333
334static int jh7110_sys_set_one_pin_mux(struct jh7110_pinctrl *sfp,
335 unsigned int pin,
336 unsigned int din, u32 dout,
337 u32 doen, u32 func)
338{
339 if (pin < sfp->gc.ngpio && func == 0)
340 jh7110_set_gpiomux(sfp, pin, din, dout, doen);
341
342 jh7110_set_function(sfp, pin, func);
343
344 if (pin < sfp->gc.ngpio && func == 2)
345 jh7110_set_vin_group(sfp, pin);
346
347 return 0;
348}
349
350static int jh7110_sys_get_padcfg_base(struct jh7110_pinctrl *sfp,
351 unsigned int pin)
352{
353 if (pin < PAD_GMAC1_MDC)
354 return JH7110_SYS_GPO_PDA_0_74_CFG;
355 else if (pin > PAD_GMAC1_TXC && pin <= PAD_QSPI_DATA3)
356 return JH7110_SYS_GPO_PDA_89_94_CFG;
357 else
358 return -1;
359}
360
361static void jh7110_sys_irq_handler(struct irq_desc *desc)
362{
363 struct jh7110_pinctrl *sfp = jh7110_from_irq_desc(desc);
364 struct irq_chip *chip = irq_desc_get_chip(desc);
365 unsigned long mis;
366 unsigned int pin;
367
368 chained_irq_enter(chip, desc);
369
370 mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS0);
371 for_each_set_bit(pin, &mis, 32)
372 generic_handle_domain_irq(sfp->gc.irq.domain, pin);
373
374 mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS1);
375 for_each_set_bit(pin, &mis, 32)
376 generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);
377
378 chained_irq_exit(chip, desc);
379}
380
381static int jh7110_sys_init_hw(struct gpio_chip *gc)
382{
383 struct jh7110_pinctrl *sfp = container_of(gc,
384 struct jh7110_pinctrl, gc);
385
386 /* mask all GPIO interrupts */
387 writel(0U, sfp->base + JH7110_SYS_GPIOIE0);
388 writel(0U, sfp->base + JH7110_SYS_GPIOIE1);
389 /* clear edge interrupt flags */
390 writel(~0U, sfp->base + JH7110_SYS_GPIOIC0);
391 writel(~0U, sfp->base + JH7110_SYS_GPIOIC1);
392 /* enable GPIO interrupts */
393 writel(1U, sfp->base + JH7110_SYS_GPIOEN);
394 return 0;
395}
396
397static const struct jh7110_gpio_irq_reg jh7110_sys_irq_reg = {
398 .is_reg_base = JH7110_SYS_GPIOIS0,
399 .ic_reg_base = JH7110_SYS_GPIOIC0,
400 .ibe_reg_base = JH7110_SYS_GPIOIBE0,
401 .iev_reg_base = JH7110_SYS_GPIOIEV0,
402 .ie_reg_base = JH7110_SYS_GPIOIE0,
403 .ris_reg_base = JH7110_SYS_GPIORIS0,
404 .mis_reg_base = JH7110_SYS_GPIOMIS0,
405};
406
407static const struct jh7110_pinctrl_soc_info jh7110_sys_pinctrl_info = {
408 .pins = jh7110_sys_pins,
409 .npins = ARRAY_SIZE(jh7110_sys_pins),
410 .ngpios = JH7110_SYS_NGPIO,
411 .gc_base = JH7110_SYS_GC_BASE,
412 .dout_reg_base = JH7110_SYS_DOUT,
413 .dout_mask = GENMASK(6, 0),
414 .doen_reg_base = JH7110_SYS_DOEN,
415 .doen_mask = GENMASK(5, 0),
416 .gpi_reg_base = JH7110_SYS_GPI,
417 .gpi_mask = GENMASK(6, 0),
418 .gpioin_reg_base = JH7110_SYS_GPIOIN,
419 .irq_reg = &jh7110_sys_irq_reg,
420 .jh7110_set_one_pin_mux = jh7110_sys_set_one_pin_mux,
421 .jh7110_get_padcfg_base = jh7110_sys_get_padcfg_base,
422 .jh7110_gpio_irq_handler = jh7110_sys_irq_handler,
423 .jh7110_gpio_init_hw = jh7110_sys_init_hw,
424};
425
426static const struct of_device_id jh7110_sys_pinctrl_of_match[] = {
427 {
428 .compatible = "starfive,jh7110-sys-pinctrl",
429 .data = &jh7110_sys_pinctrl_info,
430 },
431 { /* sentinel */ }
432};
433MODULE_DEVICE_TABLE(of, jh7110_sys_pinctrl_of_match);
434
435static struct platform_driver jh7110_sys_pinctrl_driver = {
436 .probe = jh7110_pinctrl_probe,
437 .driver = {
438 .name = "starfive-jh7110-sys-pinctrl",
439 .of_match_table = jh7110_sys_pinctrl_of_match,
440 },
441};
442module_platform_driver(jh7110_sys_pinctrl_driver);
443
444MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC sys controller");
445MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
446MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>");
447MODULE_LICENSE("GPL");