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Linux kernel mirror (for testing)
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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25#ifndef __AMDGPU_PSP_H__
26#define __AMDGPU_PSP_H__
27
28#include "amdgpu.h"
29#include "psp_gfx_if.h"
30#include "ta_xgmi_if.h"
31#include "ta_ras_if.h"
32#include "ta_rap_if.h"
33#include "ta_secureDisplay_if.h"
34
35#define PSP_FENCE_BUFFER_SIZE 0x1000
36#define PSP_CMD_BUFFER_SIZE 0x1000
37#define PSP_1_MEG 0x100000
38#define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
39#define PSP_TMR_ALIGNMENT 0x100000
40#define PSP_FW_NAME_LEN 0x24
41
42extern const struct attribute_group amdgpu_flash_attr_group;
43
44enum psp_shared_mem_size {
45 PSP_ASD_SHARED_MEM_SIZE = 0x0,
46 PSP_XGMI_SHARED_MEM_SIZE = 0x4000,
47 PSP_RAS_SHARED_MEM_SIZE = 0x4000,
48 PSP_HDCP_SHARED_MEM_SIZE = 0x4000,
49 PSP_DTM_SHARED_MEM_SIZE = 0x4000,
50 PSP_RAP_SHARED_MEM_SIZE = 0x4000,
51 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000,
52};
53
54enum ta_type_id {
55 TA_TYPE_XGMI = 1,
56 TA_TYPE_RAS,
57 TA_TYPE_HDCP,
58 TA_TYPE_DTM,
59 TA_TYPE_RAP,
60 TA_TYPE_SECUREDISPLAY,
61
62 TA_TYPE_MAX_INDEX,
63};
64
65struct psp_context;
66struct psp_xgmi_node_info;
67struct psp_xgmi_topology_info;
68struct psp_bin_desc;
69
70enum psp_bootloader_cmd {
71 PSP_BL__LOAD_SYSDRV = 0x10000,
72 PSP_BL__LOAD_SOSDRV = 0x20000,
73 PSP_BL__LOAD_KEY_DATABASE = 0x80000,
74 PSP_BL__LOAD_SOCDRV = 0xB0000,
75 PSP_BL__LOAD_DBGDRV = 0xC0000,
76 PSP_BL__LOAD_INTFDRV = 0xD0000,
77 PSP_BL__LOAD_RASDRV = 0xE0000,
78 PSP_BL__DRAM_LONG_TRAIN = 0x100000,
79 PSP_BL__DRAM_SHORT_TRAIN = 0x200000,
80 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000,
81};
82
83enum psp_ring_type {
84 PSP_RING_TYPE__INVALID = 0,
85 /*
86 * These values map to the way the PSP kernel identifies the
87 * rings.
88 */
89 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
90 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */
91};
92
93struct psp_ring {
94 enum psp_ring_type ring_type;
95 struct psp_gfx_rb_frame *ring_mem;
96 uint64_t ring_mem_mc_addr;
97 void *ring_mem_handle;
98 uint32_t ring_size;
99 uint32_t ring_wptr;
100};
101
102/* More registers may will be supported */
103enum psp_reg_prog_id {
104 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */
105 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */
106 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */
107 PSP_REG_LAST
108};
109
110struct psp_funcs {
111 int (*init_microcode)(struct psp_context *psp);
112 int (*wait_for_bootloader)(struct psp_context *psp);
113 int (*bootloader_load_kdb)(struct psp_context *psp);
114 int (*bootloader_load_spl)(struct psp_context *psp);
115 int (*bootloader_load_sysdrv)(struct psp_context *psp);
116 int (*bootloader_load_soc_drv)(struct psp_context *psp);
117 int (*bootloader_load_intf_drv)(struct psp_context *psp);
118 int (*bootloader_load_dbg_drv)(struct psp_context *psp);
119 int (*bootloader_load_ras_drv)(struct psp_context *psp);
120 int (*bootloader_load_sos)(struct psp_context *psp);
121 int (*ring_create)(struct psp_context *psp,
122 enum psp_ring_type ring_type);
123 int (*ring_stop)(struct psp_context *psp,
124 enum psp_ring_type ring_type);
125 int (*ring_destroy)(struct psp_context *psp,
126 enum psp_ring_type ring_type);
127 bool (*smu_reload_quirk)(struct psp_context *psp);
128 int (*mode1_reset)(struct psp_context *psp);
129 int (*mem_training)(struct psp_context *psp, uint32_t ops);
130 uint32_t (*ring_get_wptr)(struct psp_context *psp);
131 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
132 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
133 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
134 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
135 int (*vbflash_stat)(struct psp_context *psp);
136 int (*fatal_error_recovery_quirk)(struct psp_context *psp);
137};
138
139struct ta_funcs {
140 int (*fn_ta_initialize)(struct psp_context *psp);
141 int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id);
142 int (*fn_ta_terminate)(struct psp_context *psp);
143};
144
145#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
146struct psp_xgmi_node_info {
147 uint64_t node_id;
148 uint8_t num_hops;
149 uint8_t is_sharing_enabled;
150 enum ta_xgmi_assigned_sdma_engine sdma_engine;
151 uint8_t num_links;
152};
153
154struct psp_xgmi_topology_info {
155 uint32_t num_nodes;
156 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
157};
158
159struct psp_bin_desc {
160 uint32_t fw_version;
161 uint32_t feature_version;
162 uint32_t size_bytes;
163 uint8_t *start_addr;
164};
165
166struct ta_mem_context {
167 struct amdgpu_bo *shared_bo;
168 uint64_t shared_mc_addr;
169 void *shared_buf;
170 enum psp_shared_mem_size shared_mem_size;
171};
172
173struct ta_context {
174 bool initialized;
175 uint32_t session_id;
176 uint32_t resp_status;
177 struct ta_mem_context mem_context;
178 struct psp_bin_desc bin_desc;
179 enum psp_gfx_cmd_id ta_load_type;
180 enum ta_type_id ta_type;
181};
182
183struct ta_cp_context {
184 struct ta_context context;
185 struct mutex mutex;
186};
187
188struct psp_xgmi_context {
189 struct ta_context context;
190 struct psp_xgmi_topology_info top_info;
191 bool supports_extended_data;
192};
193
194struct psp_ras_context {
195 struct ta_context context;
196 struct amdgpu_ras *ras;
197};
198
199#define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942
200#define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000
201#define GDDR6_MEM_TRAINING_OFFSET 0x8000
202/*Define the VRAM size that will be encroached by BIST training.*/
203#define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x2000000
204
205enum psp_memory_training_init_flag {
206 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0,
207 PSP_MEM_TRAIN_SUPPORT = 0x1,
208 PSP_MEM_TRAIN_INIT_FAILED = 0x2,
209 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4,
210 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8,
211};
212
213enum psp_memory_training_ops {
214 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1,
215 PSP_MEM_TRAIN_SAVE = 0x2,
216 PSP_MEM_TRAIN_RESTORE = 0x4,
217 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8,
218 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG,
219 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG,
220};
221
222struct psp_memory_training_context {
223 /*training data size*/
224 u64 train_data_size;
225 /*
226 * sys_cache
227 * cpu virtual address
228 * system memory buffer that used to store the training data.
229 */
230 void *sys_cache;
231
232 /*vram offset of the p2c training data*/
233 u64 p2c_train_data_offset;
234
235 /*vram offset of the c2p training data*/
236 u64 c2p_train_data_offset;
237 struct amdgpu_bo *c2p_bo;
238
239 enum psp_memory_training_init_flag init;
240 u32 training_cnt;
241 bool enable_mem_training;
242};
243
244/** PSP runtime DB **/
245#define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000
246#define PSP_RUNTIME_DB_OFFSET 0x100000
247#define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5
248#define PSP_RUNTIME_DB_VER_1 0x0100
249#define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40
250
251enum psp_runtime_entry_type {
252 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0,
253 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1,
254 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */
255 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */
256 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */
257 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */
258 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */
259};
260
261/* PSP runtime DB header */
262struct psp_runtime_data_header {
263 /* determine the existence of runtime db */
264 uint16_t cookie;
265 /* version of runtime db */
266 uint16_t version;
267};
268
269/* PSP runtime DB entry */
270struct psp_runtime_entry {
271 /* type of runtime db entry */
272 uint32_t entry_type;
273 /* offset of entry in bytes */
274 uint16_t offset;
275 /* size of entry in bytes */
276 uint16_t size;
277};
278
279/* PSP runtime DB directory */
280struct psp_runtime_data_directory {
281 /* number of valid entries */
282 uint16_t entry_count;
283 /* db entries*/
284 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
285};
286
287/* PSP runtime DB boot config feature bitmask */
288enum psp_runtime_boot_cfg_feature {
289 BOOT_CFG_FEATURE_GECC = 0x1,
290 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2,
291};
292
293/* PSP run time DB SCPM authentication defines */
294enum psp_runtime_scpm_authentication {
295 SCPM_DISABLE = 0x0,
296 SCPM_ENABLE = 0x1,
297 SCPM_ENABLE_WITH_SCPM_ERR = 0x2,
298};
299
300/* PSP runtime DB boot config entry */
301struct psp_runtime_boot_cfg_entry {
302 uint32_t boot_cfg_bitmask;
303 uint32_t reserved;
304};
305
306/* PSP runtime DB SCPM entry */
307struct psp_runtime_scpm_entry {
308 enum psp_runtime_scpm_authentication scpm_status;
309};
310
311struct psp_context {
312 struct amdgpu_device *adev;
313 struct psp_ring km_ring;
314 struct psp_gfx_cmd_resp *cmd;
315
316 const struct psp_funcs *funcs;
317 const struct ta_funcs *ta_funcs;
318
319 /* firmware buffer */
320 struct amdgpu_bo *fw_pri_bo;
321 uint64_t fw_pri_mc_addr;
322 void *fw_pri_buf;
323
324 /* sos firmware */
325 const struct firmware *sos_fw;
326 struct psp_bin_desc sys;
327 struct psp_bin_desc sos;
328 struct psp_bin_desc toc;
329 struct psp_bin_desc kdb;
330 struct psp_bin_desc spl;
331 struct psp_bin_desc rl;
332 struct psp_bin_desc soc_drv;
333 struct psp_bin_desc intf_drv;
334 struct psp_bin_desc dbg_drv;
335 struct psp_bin_desc ras_drv;
336
337 /* tmr buffer */
338 struct amdgpu_bo *tmr_bo;
339 uint64_t tmr_mc_addr;
340
341 /* asd firmware */
342 const struct firmware *asd_fw;
343
344 /* toc firmware */
345 const struct firmware *toc_fw;
346
347 /* cap firmware */
348 const struct firmware *cap_fw;
349
350 /* fence buffer */
351 struct amdgpu_bo *fence_buf_bo;
352 uint64_t fence_buf_mc_addr;
353 void *fence_buf;
354
355 /* cmd buffer */
356 struct amdgpu_bo *cmd_buf_bo;
357 uint64_t cmd_buf_mc_addr;
358 struct psp_gfx_cmd_resp *cmd_buf_mem;
359
360 /* fence value associated with cmd buffer */
361 atomic_t fence_value;
362 /* flag to mark whether gfx fw autoload is supported or not */
363 bool autoload_supported;
364 /* flag to mark whether df cstate management centralized to PMFW */
365 bool pmfw_centralized_cstate_management;
366
367 /* xgmi ta firmware and buffer */
368 const struct firmware *ta_fw;
369 uint32_t ta_fw_version;
370
371 uint32_t cap_fw_version;
372 uint32_t cap_feature_version;
373 uint32_t cap_ucode_size;
374
375 struct ta_context asd_context;
376 struct psp_xgmi_context xgmi_context;
377 struct psp_ras_context ras_context;
378 struct ta_cp_context hdcp_context;
379 struct ta_cp_context dtm_context;
380 struct ta_cp_context rap_context;
381 struct ta_cp_context securedisplay_context;
382 struct mutex mutex;
383 struct psp_memory_training_context mem_train_ctx;
384
385 uint32_t boot_cfg_bitmask;
386
387 /* firmware upgrades supported */
388 bool sup_pd_fw_up;
389 bool sup_ifwi_up;
390
391 char *vbflash_tmp_buf;
392 size_t vbflash_image_size;
393 bool vbflash_done;
394};
395
396struct amdgpu_psp_funcs {
397 bool (*check_fw_loading_status)(struct amdgpu_device *adev,
398 enum AMDGPU_UCODE_ID);
399};
400
401
402#define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
403#define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
404#define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
405#define psp_init_microcode(psp) \
406 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
407#define psp_bootloader_load_kdb(psp) \
408 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
409#define psp_bootloader_load_spl(psp) \
410 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
411#define psp_bootloader_load_sysdrv(psp) \
412 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
413#define psp_bootloader_load_soc_drv(psp) \
414 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)
415#define psp_bootloader_load_intf_drv(psp) \
416 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)
417#define psp_bootloader_load_dbg_drv(psp) \
418 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0)
419#define psp_bootloader_load_ras_drv(psp) \
420 ((psp)->funcs->bootloader_load_ras_drv ? \
421 (psp)->funcs->bootloader_load_ras_drv((psp)) : 0)
422#define psp_bootloader_load_sos(psp) \
423 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
424#define psp_smu_reload_quirk(psp) \
425 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
426#define psp_mode1_reset(psp) \
427 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
428#define psp_mem_training(psp, ops) \
429 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
430
431#define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
432#define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
433
434#define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \
435 ((psp)->funcs->load_usbc_pd_fw ? \
436 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL)
437
438#define psp_read_usbc_pd_fw(psp, fw_ver) \
439 ((psp)->funcs->read_usbc_pd_fw ? \
440 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
441
442#define psp_update_spirom(psp, fw_pri_mc_addr) \
443 ((psp)->funcs->update_spirom ? \
444 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)
445
446#define psp_vbflash_status(psp) \
447 ((psp)->funcs->vbflash_stat ? \
448 (psp)->funcs->vbflash_stat((psp)) : -EINVAL)
449
450#define psp_fatal_error_recovery_quirk(psp) \
451 ((psp)->funcs->fatal_error_recovery_quirk ? \
452 (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0)
453
454extern const struct amd_ip_funcs psp_ip_funcs;
455
456extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
457extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
458extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
459extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
460extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
461extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
462extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
463
464extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
465 uint32_t field_val, uint32_t mask, bool check_changed);
466extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
467 uint32_t field_val, uint32_t mask, uint32_t msec_timeout);
468
469int psp_execute_ip_fw_load(struct psp_context *psp,
470 struct amdgpu_firmware_info *ucode);
471
472int psp_gpu_reset(struct amdgpu_device *adev);
473
474int psp_ta_init_shared_buf(struct psp_context *psp,
475 struct ta_mem_context *mem_ctx);
476void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx);
477int psp_ta_unload(struct psp_context *psp, struct ta_context *context);
478int psp_ta_load(struct psp_context *psp, struct ta_context *context);
479int psp_ta_invoke(struct psp_context *psp,
480 uint32_t ta_cmd_id,
481 struct ta_context *context);
482
483int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta);
484int psp_xgmi_terminate(struct psp_context *psp);
485int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
486int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
487int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
488int psp_xgmi_get_topology_info(struct psp_context *psp,
489 int number_devices,
490 struct psp_xgmi_topology_info *topology,
491 bool get_extended_data);
492int psp_xgmi_set_topology_info(struct psp_context *psp,
493 int number_devices,
494 struct psp_xgmi_topology_info *topology);
495int psp_ras_initialize(struct psp_context *psp);
496int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
497int psp_ras_enable_features(struct psp_context *psp,
498 union ta_ras_cmd_input *info, bool enable);
499int psp_ras_trigger_error(struct psp_context *psp,
500 struct ta_ras_trigger_error_input *info, uint32_t instance_mask);
501int psp_ras_terminate(struct psp_context *psp);
502
503int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
504int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
505int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);
506int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
507
508int psp_rlc_autoload_start(struct psp_context *psp);
509
510int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
511 uint32_t value);
512int psp_ring_cmd_submit(struct psp_context *psp,
513 uint64_t cmd_buf_mc_addr,
514 uint64_t fence_mc_addr,
515 int index);
516int psp_init_asd_microcode(struct psp_context *psp,
517 const char *chip_name);
518int psp_init_toc_microcode(struct psp_context *psp,
519 const char *chip_name);
520int psp_init_sos_microcode(struct psp_context *psp,
521 const char *chip_name);
522int psp_init_ta_microcode(struct psp_context *psp,
523 const char *chip_name);
524int psp_init_cap_microcode(struct psp_context *psp,
525 const char *chip_name);
526int psp_get_fw_attestation_records_addr(struct psp_context *psp,
527 uint64_t *output_ptr);
528
529int psp_load_fw_list(struct psp_context *psp,
530 struct amdgpu_firmware_info **ucode_list, int ucode_count);
531void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
532
533int psp_spatial_partition(struct psp_context *psp, int mode);
534
535int is_psp_fw_valid(struct psp_bin_desc bin);
536
537int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev);
538
539#endif