tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Authors:
5 * YT Shen <yt.shen@mediatek.com>
6 * CK Hu <ck.hu@mediatek.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/of.h>
11#include <linux/of_address.h>
12#include <linux/of_platform.h>
13#include <linux/platform_device.h>
14#include <linux/soc/mediatek/mtk-cmdq.h>
15#include <drm/drm_print.h>
16
17#include "mtk_disp_drv.h"
18#include "mtk_drm_drv.h"
19#include "mtk_drm_plane.h"
20#include "mtk_drm_ddp_comp.h"
21#include "mtk_drm_crtc.h"
22
23
24#define DISP_REG_DITHER_EN 0x0000
25#define DITHER_EN BIT(0)
26#define DISP_REG_DITHER_CFG 0x0020
27#define DITHER_RELAY_MODE BIT(0)
28#define DITHER_ENGINE_EN BIT(1)
29#define DISP_DITHERING BIT(2)
30#define DISP_REG_DITHER_SIZE 0x0030
31#define DISP_REG_DITHER_5 0x0114
32#define DISP_REG_DITHER_7 0x011c
33#define DISP_REG_DITHER_15 0x013c
34#define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
35#define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
36#define DITHER_NEW_BIT_MODE BIT(0)
37#define DISP_REG_DITHER_16 0x0140
38#define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
39#define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
40#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
41#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
42
43#define DISP_REG_DSC_CON 0x0000
44#define DSC_EN BIT(0)
45#define DSC_DUAL_INOUT BIT(2)
46#define DSC_BYPASS BIT(4)
47#define DSC_UFOE_SEL BIT(16)
48
49#define DISP_REG_OD_EN 0x0000
50#define DISP_REG_OD_CFG 0x0020
51#define OD_RELAYMODE BIT(0)
52#define DISP_REG_OD_SIZE 0x0030
53
54#define DISP_REG_POSTMASK_EN 0x0000
55#define POSTMASK_EN BIT(0)
56#define DISP_REG_POSTMASK_CFG 0x0020
57#define POSTMASK_RELAY_MODE BIT(0)
58#define DISP_REG_POSTMASK_SIZE 0x0030
59
60#define DISP_REG_UFO_START 0x0000
61#define UFO_BYPASS BIT(2)
62
63struct mtk_ddp_comp_dev {
64 struct clk *clk;
65 void __iomem *regs;
66 struct cmdq_client_reg cmdq_reg;
67};
68
69void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
70 struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
71 unsigned int offset)
72{
73#if IS_REACHABLE(CONFIG_MTK_CMDQ)
74 if (cmdq_pkt)
75 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
76 cmdq_reg->offset + offset, value);
77 else
78#endif
79 writel(value, regs + offset);
80}
81
82void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
83 struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
84 unsigned int offset)
85{
86#if IS_REACHABLE(CONFIG_MTK_CMDQ)
87 if (cmdq_pkt)
88 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
89 cmdq_reg->offset + offset, value);
90 else
91#endif
92 writel_relaxed(value, regs + offset);
93}
94
95void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
96 struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
97 unsigned int offset, unsigned int mask)
98{
99#if IS_REACHABLE(CONFIG_MTK_CMDQ)
100 if (cmdq_pkt) {
101 cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
102 cmdq_reg->offset + offset, value, mask);
103 } else {
104#endif
105 u32 tmp = readl(regs + offset);
106
107 tmp = (tmp & ~mask) | (value & mask);
108 writel(tmp, regs + offset);
109#if IS_REACHABLE(CONFIG_MTK_CMDQ)
110 }
111#endif
112}
113
114static int mtk_ddp_clk_enable(struct device *dev)
115{
116 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
117
118 return clk_prepare_enable(priv->clk);
119}
120
121static void mtk_ddp_clk_disable(struct device *dev)
122{
123 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
124
125 clk_disable_unprepare(priv->clk);
126}
127
128void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
129 unsigned int bpc, unsigned int cfg,
130 unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
131{
132 /* If bpc equal to 0, the dithering function didn't be enabled */
133 if (bpc == 0)
134 return;
135
136 if (bpc >= MTK_MIN_BPC) {
137 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
138 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
139 mtk_ddp_write(cmdq_pkt,
140 DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
141 DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
142 DITHER_NEW_BIT_MODE,
143 cmdq_reg, regs, DISP_REG_DITHER_15);
144 mtk_ddp_write(cmdq_pkt,
145 DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
146 DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
147 DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
148 DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
149 cmdq_reg, regs, DISP_REG_DITHER_16);
150 mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
151 }
152}
153
154static void mtk_dither_config(struct device *dev, unsigned int w,
155 unsigned int h, unsigned int vrefresh,
156 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
157{
158 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
159
160 mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);
161 mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
162 DISP_REG_DITHER_CFG);
163 mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
164 DITHER_ENGINE_EN, cmdq_pkt);
165}
166
167static void mtk_dither_start(struct device *dev)
168{
169 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
170
171 writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
172}
173
174static void mtk_dither_stop(struct device *dev)
175{
176 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
177
178 writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
179}
180
181static void mtk_dither_set(struct device *dev, unsigned int bpc,
182 unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
183{
184 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
185
186 mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
187 DISP_DITHERING, cmdq_pkt);
188}
189
190static void mtk_dsc_config(struct device *dev, unsigned int w,
191 unsigned int h, unsigned int vrefresh,
192 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
193{
194 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
195
196 /* dsc bypass mode */
197 mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
198 DISP_REG_DSC_CON, DSC_BYPASS);
199 mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
200 DISP_REG_DSC_CON, DSC_UFOE_SEL);
201 mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
202 DISP_REG_DSC_CON, DSC_DUAL_INOUT);
203}
204
205static void mtk_dsc_start(struct device *dev)
206{
207 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
208
209 /* write with mask to reserve the value set in mtk_dsc_config */
210 mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
211}
212
213static void mtk_dsc_stop(struct device *dev)
214{
215 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
216
217 writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
218}
219
220static void mtk_od_config(struct device *dev, unsigned int w,
221 unsigned int h, unsigned int vrefresh,
222 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
223{
224 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
225
226 mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
227 mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
228 mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
229}
230
231static void mtk_od_start(struct device *dev)
232{
233 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
234
235 writel(1, priv->regs + DISP_REG_OD_EN);
236}
237
238static void mtk_postmask_config(struct device *dev, unsigned int w,
239 unsigned int h, unsigned int vrefresh,
240 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
241{
242 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
243
244 mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
245 DISP_REG_POSTMASK_SIZE);
246 mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,
247 priv->regs, DISP_REG_POSTMASK_CFG);
248}
249
250static void mtk_postmask_start(struct device *dev)
251{
252 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
253
254 writel(POSTMASK_EN, priv->regs + DISP_REG_POSTMASK_EN);
255}
256
257static void mtk_postmask_stop(struct device *dev)
258{
259 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
260
261 writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
262}
263
264static void mtk_ufoe_start(struct device *dev)
265{
266 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
267
268 writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
269}
270
271static const struct mtk_ddp_comp_funcs ddp_aal = {
272 .clk_enable = mtk_aal_clk_enable,
273 .clk_disable = mtk_aal_clk_disable,
274 .gamma_set = mtk_aal_gamma_set,
275 .config = mtk_aal_config,
276 .start = mtk_aal_start,
277 .stop = mtk_aal_stop,
278};
279
280static const struct mtk_ddp_comp_funcs ddp_ccorr = {
281 .clk_enable = mtk_ccorr_clk_enable,
282 .clk_disable = mtk_ccorr_clk_disable,
283 .config = mtk_ccorr_config,
284 .start = mtk_ccorr_start,
285 .stop = mtk_ccorr_stop,
286 .ctm_set = mtk_ccorr_ctm_set,
287};
288
289static const struct mtk_ddp_comp_funcs ddp_color = {
290 .clk_enable = mtk_color_clk_enable,
291 .clk_disable = mtk_color_clk_disable,
292 .config = mtk_color_config,
293 .start = mtk_color_start,
294};
295
296static const struct mtk_ddp_comp_funcs ddp_dither = {
297 .clk_enable = mtk_ddp_clk_enable,
298 .clk_disable = mtk_ddp_clk_disable,
299 .config = mtk_dither_config,
300 .start = mtk_dither_start,
301 .stop = mtk_dither_stop,
302};
303
304static const struct mtk_ddp_comp_funcs ddp_dpi = {
305 .start = mtk_dpi_start,
306 .stop = mtk_dpi_stop,
307};
308
309static const struct mtk_ddp_comp_funcs ddp_dsc = {
310 .clk_enable = mtk_ddp_clk_enable,
311 .clk_disable = mtk_ddp_clk_disable,
312 .config = mtk_dsc_config,
313 .start = mtk_dsc_start,
314 .stop = mtk_dsc_stop,
315};
316
317static const struct mtk_ddp_comp_funcs ddp_dsi = {
318 .start = mtk_dsi_ddp_start,
319 .stop = mtk_dsi_ddp_stop,
320};
321
322static const struct mtk_ddp_comp_funcs ddp_gamma = {
323 .clk_enable = mtk_gamma_clk_enable,
324 .clk_disable = mtk_gamma_clk_disable,
325 .gamma_set = mtk_gamma_set,
326 .config = mtk_gamma_config,
327 .start = mtk_gamma_start,
328 .stop = mtk_gamma_stop,
329};
330
331static const struct mtk_ddp_comp_funcs ddp_merge = {
332 .clk_enable = mtk_merge_clk_enable,
333 .clk_disable = mtk_merge_clk_disable,
334 .start = mtk_merge_start,
335 .stop = mtk_merge_stop,
336 .config = mtk_merge_config,
337};
338
339static const struct mtk_ddp_comp_funcs ddp_od = {
340 .clk_enable = mtk_ddp_clk_enable,
341 .clk_disable = mtk_ddp_clk_disable,
342 .config = mtk_od_config,
343 .start = mtk_od_start,
344};
345
346static const struct mtk_ddp_comp_funcs ddp_ovl = {
347 .clk_enable = mtk_ovl_clk_enable,
348 .clk_disable = mtk_ovl_clk_disable,
349 .config = mtk_ovl_config,
350 .start = mtk_ovl_start,
351 .stop = mtk_ovl_stop,
352 .register_vblank_cb = mtk_ovl_register_vblank_cb,
353 .unregister_vblank_cb = mtk_ovl_unregister_vblank_cb,
354 .enable_vblank = mtk_ovl_enable_vblank,
355 .disable_vblank = mtk_ovl_disable_vblank,
356 .supported_rotations = mtk_ovl_supported_rotations,
357 .layer_nr = mtk_ovl_layer_nr,
358 .layer_check = mtk_ovl_layer_check,
359 .layer_config = mtk_ovl_layer_config,
360 .bgclr_in_on = mtk_ovl_bgclr_in_on,
361 .bgclr_in_off = mtk_ovl_bgclr_in_off,
362 .get_formats = mtk_ovl_get_formats,
363 .get_num_formats = mtk_ovl_get_num_formats,
364};
365
366static const struct mtk_ddp_comp_funcs ddp_postmask = {
367 .clk_enable = mtk_ddp_clk_enable,
368 .clk_disable = mtk_ddp_clk_disable,
369 .config = mtk_postmask_config,
370 .start = mtk_postmask_start,
371 .stop = mtk_postmask_stop,
372};
373
374static const struct mtk_ddp_comp_funcs ddp_rdma = {
375 .clk_enable = mtk_rdma_clk_enable,
376 .clk_disable = mtk_rdma_clk_disable,
377 .config = mtk_rdma_config,
378 .start = mtk_rdma_start,
379 .stop = mtk_rdma_stop,
380 .register_vblank_cb = mtk_rdma_register_vblank_cb,
381 .unregister_vblank_cb = mtk_rdma_unregister_vblank_cb,
382 .enable_vblank = mtk_rdma_enable_vblank,
383 .disable_vblank = mtk_rdma_disable_vblank,
384 .layer_nr = mtk_rdma_layer_nr,
385 .layer_config = mtk_rdma_layer_config,
386 .get_formats = mtk_rdma_get_formats,
387 .get_num_formats = mtk_rdma_get_num_formats,
388};
389
390static const struct mtk_ddp_comp_funcs ddp_ufoe = {
391 .clk_enable = mtk_ddp_clk_enable,
392 .clk_disable = mtk_ddp_clk_disable,
393 .start = mtk_ufoe_start,
394};
395
396static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
397 .clk_enable = mtk_ovl_adaptor_clk_enable,
398 .clk_disable = mtk_ovl_adaptor_clk_disable,
399 .config = mtk_ovl_adaptor_config,
400 .start = mtk_ovl_adaptor_start,
401 .stop = mtk_ovl_adaptor_stop,
402 .layer_nr = mtk_ovl_adaptor_layer_nr,
403 .layer_config = mtk_ovl_adaptor_layer_config,
404 .register_vblank_cb = mtk_ovl_adaptor_register_vblank_cb,
405 .unregister_vblank_cb = mtk_ovl_adaptor_unregister_vblank_cb,
406 .enable_vblank = mtk_ovl_adaptor_enable_vblank,
407 .disable_vblank = mtk_ovl_adaptor_disable_vblank,
408 .dma_dev_get = mtk_ovl_adaptor_dma_dev_get,
409 .connect = mtk_ovl_adaptor_connect,
410 .disconnect = mtk_ovl_adaptor_disconnect,
411 .add = mtk_ovl_adaptor_add_comp,
412 .remove = mtk_ovl_adaptor_remove_comp,
413 .get_formats = mtk_ovl_adaptor_get_formats,
414 .get_num_formats = mtk_ovl_adaptor_get_num_formats,
415};
416
417static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
418 [MTK_DISP_AAL] = "aal",
419 [MTK_DISP_BLS] = "bls",
420 [MTK_DISP_CCORR] = "ccorr",
421 [MTK_DISP_COLOR] = "color",
422 [MTK_DISP_DITHER] = "dither",
423 [MTK_DISP_DSC] = "dsc",
424 [MTK_DISP_GAMMA] = "gamma",
425 [MTK_DISP_MERGE] = "merge",
426 [MTK_DISP_MUTEX] = "mutex",
427 [MTK_DISP_OD] = "od",
428 [MTK_DISP_OVL] = "ovl",
429 [MTK_DISP_OVL_2L] = "ovl-2l",
430 [MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor",
431 [MTK_DISP_POSTMASK] = "postmask",
432 [MTK_DISP_PWM] = "pwm",
433 [MTK_DISP_RDMA] = "rdma",
434 [MTK_DISP_UFOE] = "ufoe",
435 [MTK_DISP_WDMA] = "wdma",
436 [MTK_DP_INTF] = "dp-intf",
437 [MTK_DPI] = "dpi",
438 [MTK_DSI] = "dsi",
439};
440
441struct mtk_ddp_comp_match {
442 enum mtk_ddp_comp_type type;
443 int alias_id;
444 const struct mtk_ddp_comp_funcs *funcs;
445};
446
447static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX] = {
448 [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
449 [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
450 [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
451 [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
452 [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
453 [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
454 [DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
455 [DDP_COMPONENT_DP_INTF0] = { MTK_DP_INTF, 0, &ddp_dpi },
456 [DDP_COMPONENT_DP_INTF1] = { MTK_DP_INTF, 1, &ddp_dpi },
457 [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
458 [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
459 [DDP_COMPONENT_DRM_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor },
460 [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
461 [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
462 [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
463 [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
464 [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
465 [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
466 [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
467 [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
468 [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
469 [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
470 [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
471 [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
472 [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
473 [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
474 [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
475 [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
476 [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
477 [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
478 [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
479 [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
480 [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
481 [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
482 [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
483 [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
484 [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
485 [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
486 [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
487 [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma },
488 [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
489 [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
490 [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
491};
492
493static bool mtk_drm_find_comp_in_ddp(struct device *dev,
494 const unsigned int *path,
495 unsigned int path_len,
496 struct mtk_ddp_comp *ddp_comp)
497{
498 unsigned int i;
499
500 if (path == NULL)
501 return false;
502
503 for (i = 0U; i < path_len; i++)
504 if (dev == ddp_comp[path[i]].dev)
505 return true;
506
507 return false;
508}
509
510int mtk_ddp_comp_get_id(struct device_node *node,
511 enum mtk_ddp_comp_type comp_type)
512{
513 int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
514 int i;
515
516 for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
517 if (comp_type == mtk_ddp_matches[i].type &&
518 (id < 0 || id == mtk_ddp_matches[i].alias_id))
519 return i;
520 }
521
522 return -EINVAL;
523}
524
525unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
526 struct device *dev)
527{
528 struct mtk_drm_private *private = drm->dev_private;
529 unsigned int ret = 0;
530
531 if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path, private->data->main_len,
532 private->ddp_comp))
533 ret = BIT(0);
534 else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path,
535 private->data->ext_len, private->ddp_comp))
536 ret = BIT(1);
537 else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path,
538 private->data->third_len, private->ddp_comp))
539 ret = BIT(2);
540 else
541 DRM_INFO("Failed to find comp in ddp table\n");
542
543 return ret;
544}
545
546int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
547 unsigned int comp_id)
548{
549 struct platform_device *comp_pdev;
550 enum mtk_ddp_comp_type type;
551 struct mtk_ddp_comp_dev *priv;
552#if IS_REACHABLE(CONFIG_MTK_CMDQ)
553 int ret;
554#endif
555
556 if (comp_id < 0 || comp_id >= DDP_COMPONENT_DRM_ID_MAX)
557 return -EINVAL;
558
559 type = mtk_ddp_matches[comp_id].type;
560
561 comp->id = comp_id;
562 comp->funcs = mtk_ddp_matches[comp_id].funcs;
563 /* Not all drm components have a DTS device node, such as ovl_adaptor,
564 * which is the drm bring up sub driver
565 */
566 if (node) {
567 comp_pdev = of_find_device_by_node(node);
568 if (!comp_pdev) {
569 DRM_INFO("Waiting for device %s\n", node->full_name);
570 return -EPROBE_DEFER;
571 }
572 comp->dev = &comp_pdev->dev;
573 }
574
575 if (type == MTK_DISP_AAL ||
576 type == MTK_DISP_BLS ||
577 type == MTK_DISP_CCORR ||
578 type == MTK_DISP_COLOR ||
579 type == MTK_DISP_GAMMA ||
580 type == MTK_DISP_MERGE ||
581 type == MTK_DISP_OVL ||
582 type == MTK_DISP_OVL_2L ||
583 type == MTK_DISP_OVL_ADAPTOR ||
584 type == MTK_DISP_PWM ||
585 type == MTK_DISP_RDMA ||
586 type == MTK_DPI ||
587 type == MTK_DP_INTF ||
588 type == MTK_DSI)
589 return 0;
590
591 priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
592 if (!priv)
593 return -ENOMEM;
594
595 priv->regs = of_iomap(node, 0);
596 priv->clk = of_clk_get(node, 0);
597 if (IS_ERR(priv->clk))
598 return PTR_ERR(priv->clk);
599
600#if IS_REACHABLE(CONFIG_MTK_CMDQ)
601 ret = cmdq_dev_get_client_reg(comp->dev, &priv->cmdq_reg, 0);
602 if (ret)
603 dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n");
604#endif
605
606 platform_set_drvdata(comp_pdev, priv);
607
608 return 0;
609}