tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2023 Intel Corporation
4 */
5
6#ifndef __INTEL_DISPLAY_DEVICE_H__
7#define __INTEL_DISPLAY_DEVICE_H__
8
9#include <linux/types.h>
10
11#include "intel_display_limits.h"
12
13struct drm_i915_private;
14
15#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
16 /* Keep in alphabetical order */ \
17 func(cursor_needs_physical); \
18 func(has_cdclk_crawl); \
19 func(has_cdclk_squash); \
20 func(has_ddi); \
21 func(has_dp_mst); \
22 func(has_dsb); \
23 func(has_fpga_dbg); \
24 func(has_gmch); \
25 func(has_hotplug); \
26 func(has_hti); \
27 func(has_ipc); \
28 func(has_overlay); \
29 func(has_psr); \
30 func(has_psr_hw_tracking); \
31 func(overlay_needs_physical); \
32 func(supports_tv);
33
34#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
35#define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
36#define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
37#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
38#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915))
39#define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi)
40#define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
41#define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc)
42#define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
43#define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst)
44#define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
45#define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13)
46#define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb)
47#define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
48#define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
49#define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg)
50#define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
51#define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4)
52#define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915))
53#define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch)
54#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
55#define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
56#define HAS_IPS(i915) (IS_HSW_ULT(i915) || IS_BROADWELL(i915))
57#define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
58#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
59#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
60#define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay)
61#define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr)
62#define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking)
63#define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12)
64#define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
65#define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
66 BIT(trans)) != 0)
67#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
68#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
69#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
70#define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical)
71#define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
72
73struct intel_display_runtime_info {
74 struct {
75 u16 ver;
76 u16 rel;
77 u16 step;
78 } ip;
79
80 u8 pipe_mask;
81 u8 cpu_transcoder_mask;
82
83 u8 num_sprites[I915_MAX_PIPES];
84 u8 num_scalers[I915_MAX_PIPES];
85
86 u8 fbc_mask;
87
88 bool has_hdcp;
89 bool has_dmc;
90 bool has_dsc;
91};
92
93struct intel_display_device_info {
94 /* Initial runtime info. */
95 const struct intel_display_runtime_info __runtime_defaults;
96
97 u8 abox_mask;
98
99 struct {
100 u16 size; /* in blocks */
101 u8 slice_mask;
102 } dbuf;
103
104#define DEFINE_FLAG(name) u8 name:1
105 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
106#undef DEFINE_FLAG
107
108 /* Global register offset for the display engine */
109 u32 mmio_offset;
110
111 /* Register offsets for the various display pipes and transcoders */
112 u32 pipe_offsets[I915_MAX_TRANSCODERS];
113 u32 trans_offsets[I915_MAX_TRANSCODERS];
114 u32 cursor_offsets[I915_MAX_PIPES];
115
116 struct {
117 u32 degamma_lut_size;
118 u32 gamma_lut_size;
119 u32 degamma_lut_tests;
120 u32 gamma_lut_tests;
121 } color;
122};
123
124const struct intel_display_device_info *
125intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid,
126 u16 *ver, u16 *rel, u16 *step);
127void intel_display_device_info_runtime_init(struct drm_i915_private *i915);
128
129#endif