tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29#include <linux/pci.h>
30
31#include <drm/drm_atomic_helper.h>
32#include <drm/drm_drv.h>
33#include <drm/drm_gem.h>
34#include <drm/drm_managed.h>
35
36#include "ast_drv.h"
37
38void ast_set_index_reg_mask(struct ast_device *ast,
39 uint32_t base, uint8_t index,
40 uint8_t mask, uint8_t val)
41{
42 u8 tmp;
43 ast_io_write8(ast, base, index);
44 tmp = (ast_io_read8(ast, base + 1) & mask) | val;
45 ast_set_index_reg(ast, base, index, tmp);
46}
47
48uint8_t ast_get_index_reg(struct ast_device *ast,
49 uint32_t base, uint8_t index)
50{
51 uint8_t ret;
52 ast_io_write8(ast, base, index);
53 ret = ast_io_read8(ast, base + 1);
54 return ret;
55}
56
57uint8_t ast_get_index_reg_mask(struct ast_device *ast,
58 uint32_t base, uint8_t index, uint8_t mask)
59{
60 uint8_t ret;
61 ast_io_write8(ast, base, index);
62 ret = ast_io_read8(ast, base + 1) & mask;
63 return ret;
64}
65
66static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
67{
68 struct device_node *np = dev->dev->of_node;
69 struct ast_device *ast = to_ast_device(dev);
70 struct pci_dev *pdev = to_pci_dev(dev->dev);
71 uint32_t data, jregd0, jregd1;
72
73 /* Defaults */
74 ast->config_mode = ast_use_defaults;
75 *scu_rev = 0xffffffff;
76
77 /* Check if we have device-tree properties */
78 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
79 scu_rev)) {
80 /* We do, disable P2A access */
81 ast->config_mode = ast_use_dt;
82 drm_info(dev, "Using device-tree for configuration\n");
83 return;
84 }
85
86 /* Not all families have a P2A bridge */
87 if (pdev->device != PCI_CHIP_AST2000)
88 return;
89
90 /*
91 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
92 * is disabled. We force using P2A if VGA only mode bit
93 * is set D[7]
94 */
95 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
96 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
97 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
98 /* Patch AST2500 */
99 if (((pdev->revision & 0xF0) == 0x40)
100 && ((jregd0 & AST_VRAM_INIT_STATUS_MASK) == 0))
101 ast_patch_ahb_2500(ast);
102
103 /* Double check it's actually working */
104 data = ast_read32(ast, 0xf004);
105 if ((data != 0xFFFFFFFF) && (data != 0x00)) {
106 /* P2A works, grab silicon revision */
107 ast->config_mode = ast_use_p2a;
108
109 drm_info(dev, "Using P2A bridge for configuration\n");
110
111 /* Read SCU7c (silicon revision register) */
112 ast_write32(ast, 0xf004, 0x1e6e0000);
113 ast_write32(ast, 0xf000, 0x1);
114 *scu_rev = ast_read32(ast, 0x1207c);
115 return;
116 }
117 }
118
119 /* We have a P2A bridge but it's disabled */
120 drm_info(dev, "P2A bridge disabled, using default configuration\n");
121}
122
123static int ast_detect_chip(struct drm_device *dev, bool *need_post)
124{
125 struct ast_device *ast = to_ast_device(dev);
126 struct pci_dev *pdev = to_pci_dev(dev->dev);
127 uint32_t jreg, scu_rev;
128
129 /*
130 * If VGA isn't enabled, we need to enable now or subsequent
131 * access to the scratch registers will fail. We also inform
132 * our caller that it needs to POST the chip
133 * (Assumption: VGA not enabled -> need to POST)
134 */
135 if (!ast_is_vga_enabled(dev)) {
136 ast_enable_vga(dev);
137 drm_info(dev, "VGA not enabled on entry, requesting chip POST\n");
138 *need_post = true;
139 } else
140 *need_post = false;
141
142
143 /* Enable extended register access */
144 ast_open_key(ast);
145 ast_enable_mmio(dev);
146
147 /* Find out whether P2A works or whether to use device-tree */
148 ast_detect_config_mode(dev, &scu_rev);
149
150 /* Identify chipset */
151 if (pdev->revision >= 0x50) {
152 ast->chip = AST2600;
153 drm_info(dev, "AST 2600 detected\n");
154 } else if (pdev->revision >= 0x40) {
155 ast->chip = AST2500;
156 drm_info(dev, "AST 2500 detected\n");
157 } else if (pdev->revision >= 0x30) {
158 ast->chip = AST2400;
159 drm_info(dev, "AST 2400 detected\n");
160 } else if (pdev->revision >= 0x20) {
161 ast->chip = AST2300;
162 drm_info(dev, "AST 2300 detected\n");
163 } else if (pdev->revision >= 0x10) {
164 switch (scu_rev & 0x0300) {
165 case 0x0200:
166 ast->chip = AST1100;
167 drm_info(dev, "AST 1100 detected\n");
168 break;
169 case 0x0100:
170 ast->chip = AST2200;
171 drm_info(dev, "AST 2200 detected\n");
172 break;
173 case 0x0000:
174 ast->chip = AST2150;
175 drm_info(dev, "AST 2150 detected\n");
176 break;
177 default:
178 ast->chip = AST2100;
179 drm_info(dev, "AST 2100 detected\n");
180 break;
181 }
182 ast->vga2_clone = false;
183 } else {
184 ast->chip = AST2000;
185 drm_info(dev, "AST 2000 detected\n");
186 }
187
188 /* Check if we support wide screen */
189 switch (ast->chip) {
190 case AST2000:
191 ast->support_wide_screen = false;
192 break;
193 default:
194 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
195 if (!(jreg & 0x80))
196 ast->support_wide_screen = true;
197 else if (jreg & 0x01)
198 ast->support_wide_screen = true;
199 else {
200 ast->support_wide_screen = false;
201 if (ast->chip == AST2300 &&
202 (scu_rev & 0x300) == 0x0) /* ast1300 */
203 ast->support_wide_screen = true;
204 if (ast->chip == AST2400 &&
205 (scu_rev & 0x300) == 0x100) /* ast1400 */
206 ast->support_wide_screen = true;
207 if (ast->chip == AST2500 &&
208 scu_rev == 0x100) /* ast2510 */
209 ast->support_wide_screen = true;
210 if (ast->chip == AST2600) /* ast2600 */
211 ast->support_wide_screen = true;
212 }
213 break;
214 }
215
216 /* Check 3rd Tx option (digital output afaik) */
217 ast->tx_chip_types |= AST_TX_NONE_BIT;
218
219 /*
220 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
221 * enabled, in that case, assume we have a SIL164 TMDS transmitter
222 *
223 * Don't make that assumption if we the chip wasn't enabled and
224 * is at power-on reset, otherwise we'll incorrectly "detect" a
225 * SIL164 when there is none.
226 */
227 if (!*need_post) {
228 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
229 if (jreg & 0x80)
230 ast->tx_chip_types = AST_TX_SIL164_BIT;
231 }
232
233 if ((ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST2500)) {
234 /*
235 * On AST2300 and 2400, look the configuration set by the SoC in
236 * the SOC scratch register #1 bits 11:8 (interestingly marked
237 * as "reserved" in the spec)
238 */
239 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
240 switch (jreg) {
241 case 0x04:
242 ast->tx_chip_types = AST_TX_SIL164_BIT;
243 break;
244 case 0x08:
245 ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL);
246 if (ast->dp501_fw_addr) {
247 /* backup firmware */
248 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
249 drmm_kfree(dev, ast->dp501_fw_addr);
250 ast->dp501_fw_addr = NULL;
251 }
252 }
253 fallthrough;
254 case 0x0c:
255 ast->tx_chip_types = AST_TX_DP501_BIT;
256 }
257 } else if (ast->chip == AST2600) {
258 if (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, TX_TYPE_MASK) ==
259 ASTDP_DPMCU_TX) {
260 ast->tx_chip_types = AST_TX_ASTDP_BIT;
261 ast_dp_launch(&ast->base);
262 }
263 }
264
265 /* Print stuff for diagnostic purposes */
266 if (ast->tx_chip_types & AST_TX_NONE_BIT)
267 drm_info(dev, "Using analog VGA\n");
268 if (ast->tx_chip_types & AST_TX_SIL164_BIT)
269 drm_info(dev, "Using Sil164 TMDS transmitter\n");
270 if (ast->tx_chip_types & AST_TX_DP501_BIT)
271 drm_info(dev, "Using DP501 DisplayPort transmitter\n");
272 if (ast->tx_chip_types & AST_TX_ASTDP_BIT)
273 drm_info(dev, "Using ASPEED DisplayPort transmitter\n");
274
275 return 0;
276}
277
278static int ast_get_dram_info(struct drm_device *dev)
279{
280 struct device_node *np = dev->dev->of_node;
281 struct ast_device *ast = to_ast_device(dev);
282 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
283 uint32_t denum, num, div, ref_pll, dsel;
284
285 switch (ast->config_mode) {
286 case ast_use_dt:
287 /*
288 * If some properties are missing, use reasonable
289 * defaults for AST2400
290 */
291 if (of_property_read_u32(np, "aspeed,mcr-configuration",
292 &mcr_cfg))
293 mcr_cfg = 0x00000577;
294 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
295 &mcr_scu_mpll))
296 mcr_scu_mpll = 0x000050C0;
297 if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
298 &mcr_scu_strap))
299 mcr_scu_strap = 0;
300 break;
301 case ast_use_p2a:
302 ast_write32(ast, 0xf004, 0x1e6e0000);
303 ast_write32(ast, 0xf000, 0x1);
304 mcr_cfg = ast_read32(ast, 0x10004);
305 mcr_scu_mpll = ast_read32(ast, 0x10120);
306 mcr_scu_strap = ast_read32(ast, 0x10170);
307 break;
308 case ast_use_defaults:
309 default:
310 ast->dram_bus_width = 16;
311 ast->dram_type = AST_DRAM_1Gx16;
312 if (ast->chip == AST2500)
313 ast->mclk = 800;
314 else
315 ast->mclk = 396;
316 return 0;
317 }
318
319 if (mcr_cfg & 0x40)
320 ast->dram_bus_width = 16;
321 else
322 ast->dram_bus_width = 32;
323
324 if (ast->chip == AST2500) {
325 switch (mcr_cfg & 0x03) {
326 case 0:
327 ast->dram_type = AST_DRAM_1Gx16;
328 break;
329 default:
330 case 1:
331 ast->dram_type = AST_DRAM_2Gx16;
332 break;
333 case 2:
334 ast->dram_type = AST_DRAM_4Gx16;
335 break;
336 case 3:
337 ast->dram_type = AST_DRAM_8Gx16;
338 break;
339 }
340 } else if (ast->chip == AST2300 || ast->chip == AST2400) {
341 switch (mcr_cfg & 0x03) {
342 case 0:
343 ast->dram_type = AST_DRAM_512Mx16;
344 break;
345 default:
346 case 1:
347 ast->dram_type = AST_DRAM_1Gx16;
348 break;
349 case 2:
350 ast->dram_type = AST_DRAM_2Gx16;
351 break;
352 case 3:
353 ast->dram_type = AST_DRAM_4Gx16;
354 break;
355 }
356 } else {
357 switch (mcr_cfg & 0x0c) {
358 case 0:
359 case 4:
360 ast->dram_type = AST_DRAM_512Mx16;
361 break;
362 case 8:
363 if (mcr_cfg & 0x40)
364 ast->dram_type = AST_DRAM_1Gx16;
365 else
366 ast->dram_type = AST_DRAM_512Mx32;
367 break;
368 case 0xc:
369 ast->dram_type = AST_DRAM_1Gx32;
370 break;
371 }
372 }
373
374 if (mcr_scu_strap & 0x2000)
375 ref_pll = 14318;
376 else
377 ref_pll = 12000;
378
379 denum = mcr_scu_mpll & 0x1f;
380 num = (mcr_scu_mpll & 0x3fe0) >> 5;
381 dsel = (mcr_scu_mpll & 0xc000) >> 14;
382 switch (dsel) {
383 case 3:
384 div = 0x4;
385 break;
386 case 2:
387 case 1:
388 div = 0x2;
389 break;
390 default:
391 div = 0x1;
392 break;
393 }
394 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
395 return 0;
396}
397
398/*
399 * Run this function as part of the HW device cleanup; not
400 * when the DRM device gets released.
401 */
402static void ast_device_release(void *data)
403{
404 struct ast_device *ast = data;
405
406 /* enable standard VGA decode */
407 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04);
408}
409
410struct ast_device *ast_device_create(const struct drm_driver *drv,
411 struct pci_dev *pdev,
412 unsigned long flags)
413{
414 struct drm_device *dev;
415 struct ast_device *ast;
416 bool need_post;
417 int ret = 0;
418
419 ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_device, base);
420 if (IS_ERR(ast))
421 return ast;
422 dev = &ast->base;
423
424 pci_set_drvdata(pdev, dev);
425
426 ret = drmm_mutex_init(dev, &ast->ioregs_lock);
427 if (ret)
428 return ERR_PTR(ret);
429
430 ast->regs = pcim_iomap(pdev, 1, 0);
431 if (!ast->regs)
432 return ERR_PTR(-EIO);
433
434 /*
435 * After AST2500, MMIO is enabled by default, and it should be adopted
436 * to be compatible with Arm.
437 */
438 if (pdev->revision >= 0x40) {
439 ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
440 } else if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) {
441 drm_info(dev, "platform has no IO space, trying MMIO\n");
442 ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
443 }
444
445 /* "map" IO regs if the above hasn't done so already */
446 if (!ast->ioregs) {
447 ast->ioregs = pcim_iomap(pdev, 2, 0);
448 if (!ast->ioregs)
449 return ERR_PTR(-EIO);
450 }
451
452 ast_detect_chip(dev, &need_post);
453
454 ret = ast_get_dram_info(dev);
455 if (ret)
456 return ERR_PTR(ret);
457
458 drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
459 ast->mclk, ast->dram_type, ast->dram_bus_width);
460
461 if (need_post)
462 ast_post_gpu(dev);
463
464 ret = ast_mm_init(ast);
465 if (ret)
466 return ERR_PTR(ret);
467
468 /* map reserved buffer */
469 ast->dp501_fw_buf = NULL;
470 if (ast->vram_size < pci_resource_len(pdev, 0)) {
471 ast->dp501_fw_buf = pci_iomap_range(pdev, 0, ast->vram_size, 0);
472 if (!ast->dp501_fw_buf)
473 drm_info(dev, "failed to map reserved buffer!\n");
474 }
475
476 ret = ast_mode_config_init(ast);
477 if (ret)
478 return ERR_PTR(ret);
479
480 ret = devm_add_action_or_reset(dev->dev, ast_device_release, ast);
481 if (ret)
482 return ERR_PTR(ret);
483
484 return ast;
485}