tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/pmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM Performance Monitor Units
8
9maintainers:
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
12
13description: |+
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
16 representation in the device tree should be done as under:-
17
18properties:
19 compatible:
20 items:
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
25 - apple,firestorm-pmu
26 - apple,icestorm-pmu
27 - arm,armv8-pmuv3 # Only for s/w models
28 - arm,arm1136-pmu
29 - arm,arm1176-pmu
30 - arm,arm11mpcore-pmu
31 - arm,cortex-a5-pmu
32 - arm,cortex-a7-pmu
33 - arm,cortex-a8-pmu
34 - arm,cortex-a9-pmu
35 - arm,cortex-a12-pmu
36 - arm,cortex-a15-pmu
37 - arm,cortex-a17-pmu
38 - arm,cortex-a32-pmu
39 - arm,cortex-a34-pmu
40 - arm,cortex-a35-pmu
41 - arm,cortex-a53-pmu
42 - arm,cortex-a55-pmu
43 - arm,cortex-a57-pmu
44 - arm,cortex-a65-pmu
45 - arm,cortex-a72-pmu
46 - arm,cortex-a73-pmu
47 - arm,cortex-a75-pmu
48 - arm,cortex-a76-pmu
49 - arm,cortex-a77-pmu
50 - arm,cortex-a78-pmu
51 - arm,cortex-a510-pmu
52 - arm,cortex-a710-pmu
53 - arm,cortex-x1-pmu
54 - arm,cortex-x2-pmu
55 - arm,neoverse-e1-pmu
56 - arm,neoverse-n1-pmu
57 - arm,neoverse-n2-pmu
58 - arm,neoverse-v1-pmu
59 - brcm,vulcan-pmu
60 - cavium,thunder-pmu
61 - nvidia,denver-pmu
62 - nvidia,carmel-pmu
63 - qcom,krait-pmu
64 - qcom,scorpion-pmu
65 - qcom,scorpion-mp-pmu
66
67 interrupts:
68 # Don't know how many CPUs, so no constraints to specify
69 description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
70
71 interrupt-affinity:
72 $ref: /schemas/types.yaml#/definitions/phandle-array
73 items:
74 maxItems: 1
75 description:
76 When using SPIs, specifies a list of phandles to CPU
77 nodes corresponding directly to the affinity of
78 the SPIs listed in the interrupts property.
79
80 When using a PPI, specifies a list of phandles to CPU
81 nodes corresponding to the set of CPUs which have
82 a PMU of this type signalling the PPI listed in the
83 interrupts property, unless this is already specified
84 by the PPI interrupt specifier itself (in which case
85 the interrupt-affinity property shouldn't be present).
86
87 This property should be present when there is more than
88 a single SPI.
89
90 qcom,no-pc-write:
91 type: boolean
92 description:
93 Indicates that this PMU doesn't support the 0xc and 0xd events.
94
95 secure-reg-access:
96 type: boolean
97 description:
98 Indicates that the ARMv7 Secure Debug Enable Register
99 (SDER) is accessible. This will cause the driver to do
100 any setup required that is only possible in ARMv7 secure
101 state. If not present the ARMv7 SDER will not be touched,
102 which means the PMU may fail to operate unless external
103 code (bootloader or security monitor) has performed the
104 appropriate initialisation. Note that this property is
105 not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
106 in Non-secure state.
107
108required:
109 - compatible
110
111additionalProperties: false
112
113...