tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

kernel / drivers / pinctrl / qcom / pinctrl-sa8775p.c
at v6.5-rc5 1548 lines 45 kB view raw
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2023, Linaro Limited 5 */ 6 7#include <linux/module.h> 8#include <linux/of.h> 9#include <linux/platform_device.h> 10 11#include "pinctrl-msm.h" 12 13#define REG_BASE 0x100000 14#define REG_SIZE 0x1000 15#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)\ 16 { \ 17 .grp = PINCTRL_PINGROUP("gpio" #id, \ 18 gpio##id##_pins, \ 19 ARRAY_SIZE(gpio##id##_pins)), \ 20 .funcs = (int[]){ \ 21 msm_mux_gpio, /* gpio mode */ \ 22 msm_mux_##f1, \ 23 msm_mux_##f2, \ 24 msm_mux_##f3, \ 25 msm_mux_##f4, \ 26 msm_mux_##f5, \ 27 msm_mux_##f6, \ 28 msm_mux_##f7, \ 29 msm_mux_##f8, \ 30 msm_mux_##f9 \ 31 }, \ 32 .nfuncs = 10, \ 33 .ctl_reg = REG_BASE + REG_SIZE * id, \ 34 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 35 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 36 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 37 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 38 .mux_bit = 2, \ 39 .pull_bit = 0, \ 40 .drv_bit = 6, \ 41 .egpio_enable = 12, \ 42 .egpio_present = 11, \ 43 .oe_bit = 9, \ 44 .in_bit = 0, \ 45 .out_bit = 1, \ 46 .intr_enable_bit = 0, \ 47 .intr_status_bit = 0, \ 48 .intr_target_bit = 5, \ 49 .intr_target_kpss_val = 3, \ 50 .intr_raw_status_bit = 4, \ 51 .intr_polarity_bit = 1, \ 52 .intr_detection_bit = 2, \ 53 .intr_detection_width = 2, \ 54 } 55 56#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 57 { \ 58 .grp = PINCTRL_PINGROUP(#pg_name, \ 59 pg_name##_pins, \ 60 ARRAY_SIZE(pg_name##_pins)), \ 61 .ctl_reg = ctl, \ 62 .io_reg = 0, \ 63 .intr_cfg_reg = 0, \ 64 .intr_status_reg = 0, \ 65 .intr_target_reg = 0, \ 66 .mux_bit = -1, \ 67 .pull_bit = pull, \ 68 .drv_bit = drv, \ 69 .oe_bit = -1, \ 70 .in_bit = -1, \ 71 .out_bit = -1, \ 72 .intr_enable_bit = -1, \ 73 .intr_status_bit = -1, \ 74 .intr_target_bit = -1, \ 75 .intr_raw_status_bit = -1, \ 76 .intr_polarity_bit = -1, \ 77 .intr_detection_bit = -1, \ 78 .intr_detection_width = -1, \ 79 } 80 81#define UFS_RESET(pg_name, offset) \ 82 { \ 83 .grp = PINCTRL_PINGROUP(#pg_name, \ 84 pg_name##_pins, \ 85 ARRAY_SIZE(pg_name##_pins)), \ 86 .ctl_reg = offset, \ 87 .io_reg = offset + 0x4, \ 88 .intr_cfg_reg = 0, \ 89 .intr_status_reg = 0, \ 90 .intr_target_reg = 0, \ 91 .mux_bit = -1, \ 92 .pull_bit = 3, \ 93 .drv_bit = 0, \ 94 .oe_bit = -1, \ 95 .in_bit = -1, \ 96 .out_bit = 0, \ 97 .intr_enable_bit = -1, \ 98 .intr_status_bit = -1, \ 99 .intr_target_bit = -1, \ 100 .intr_raw_status_bit = -1, \ 101 .intr_polarity_bit = -1, \ 102 .intr_detection_bit = -1, \ 103 .intr_detection_width = -1, \ 104 } 105 106#define QUP_I3C(qup_mode, qup_offset) \ 107 { \ 108 .mode = qup_mode, \ 109 .offset = qup_offset, \ 110 } 111 112#define QUP_I3C_6_MODE_OFFSET 0xAF000 113#define QUP_I3C_7_MODE_OFFSET 0xB0000 114#define QUP_I3C_13_MODE_OFFSET 0xB1000 115#define QUP_I3C_14_MODE_OFFSET 0xB2000 116 117static const struct pinctrl_pin_desc sa8775p_pins[] = { 118 PINCTRL_PIN(0, "GPIO_0"), 119 PINCTRL_PIN(1, "GPIO_1"), 120 PINCTRL_PIN(2, "GPIO_2"), 121 PINCTRL_PIN(3, "GPIO_3"), 122 PINCTRL_PIN(4, "GPIO_4"), 123 PINCTRL_PIN(5, "GPIO_5"), 124 PINCTRL_PIN(6, "GPIO_6"), 125 PINCTRL_PIN(7, "GPIO_7"), 126 PINCTRL_PIN(8, "GPIO_8"), 127 PINCTRL_PIN(9, "GPIO_9"), 128 PINCTRL_PIN(10, "GPIO_10"), 129 PINCTRL_PIN(11, "GPIO_11"), 130 PINCTRL_PIN(12, "GPIO_12"), 131 PINCTRL_PIN(13, "GPIO_13"), 132 PINCTRL_PIN(14, "GPIO_14"), 133 PINCTRL_PIN(15, "GPIO_15"), 134 PINCTRL_PIN(16, "GPIO_16"), 135 PINCTRL_PIN(17, "GPIO_17"), 136 PINCTRL_PIN(18, "GPIO_18"), 137 PINCTRL_PIN(19, "GPIO_19"), 138 PINCTRL_PIN(20, "GPIO_20"), 139 PINCTRL_PIN(21, "GPIO_21"), 140 PINCTRL_PIN(22, "GPIO_22"), 141 PINCTRL_PIN(23, "GPIO_23"), 142 PINCTRL_PIN(24, "GPIO_24"), 143 PINCTRL_PIN(25, "GPIO_25"), 144 PINCTRL_PIN(26, "GPIO_26"), 145 PINCTRL_PIN(27, "GPIO_27"), 146 PINCTRL_PIN(28, "GPIO_28"), 147 PINCTRL_PIN(29, "GPIO_29"), 148 PINCTRL_PIN(30, "GPIO_30"), 149 PINCTRL_PIN(31, "GPIO_31"), 150 PINCTRL_PIN(32, "GPIO_32"), 151 PINCTRL_PIN(33, "GPIO_33"), 152 PINCTRL_PIN(34, "GPIO_34"), 153 PINCTRL_PIN(35, "GPIO_35"), 154 PINCTRL_PIN(36, "GPIO_36"), 155 PINCTRL_PIN(37, "GPIO_37"), 156 PINCTRL_PIN(38, "GPIO_38"), 157 PINCTRL_PIN(39, "GPIO_39"), 158 PINCTRL_PIN(40, "GPIO_40"), 159 PINCTRL_PIN(41, "GPIO_41"), 160 PINCTRL_PIN(42, "GPIO_42"), 161 PINCTRL_PIN(43, "GPIO_43"), 162 PINCTRL_PIN(44, "GPIO_44"), 163 PINCTRL_PIN(45, "GPIO_45"), 164 PINCTRL_PIN(46, "GPIO_46"), 165 PINCTRL_PIN(47, "GPIO_47"), 166 PINCTRL_PIN(48, "GPIO_48"), 167 PINCTRL_PIN(49, "GPIO_49"), 168 PINCTRL_PIN(50, "GPIO_50"), 169 PINCTRL_PIN(51, "GPIO_51"), 170 PINCTRL_PIN(52, "GPIO_52"), 171 PINCTRL_PIN(53, "GPIO_53"), 172 PINCTRL_PIN(54, "GPIO_54"), 173 PINCTRL_PIN(55, "GPIO_55"), 174 PINCTRL_PIN(56, "GPIO_56"), 175 PINCTRL_PIN(57, "GPIO_57"), 176 PINCTRL_PIN(58, "GPIO_58"), 177 PINCTRL_PIN(59, "GPIO_59"), 178 PINCTRL_PIN(60, "GPIO_60"), 179 PINCTRL_PIN(61, "GPIO_61"), 180 PINCTRL_PIN(62, "GPIO_62"), 181 PINCTRL_PIN(63, "GPIO_63"), 182 PINCTRL_PIN(64, "GPIO_64"), 183 PINCTRL_PIN(65, "GPIO_65"), 184 PINCTRL_PIN(66, "GPIO_66"), 185 PINCTRL_PIN(67, "GPIO_67"), 186 PINCTRL_PIN(68, "GPIO_68"), 187 PINCTRL_PIN(69, "GPIO_69"), 188 PINCTRL_PIN(70, "GPIO_70"), 189 PINCTRL_PIN(71, "GPIO_71"), 190 PINCTRL_PIN(72, "GPIO_72"), 191 PINCTRL_PIN(73, "GPIO_73"), 192 PINCTRL_PIN(74, "GPIO_74"), 193 PINCTRL_PIN(75, "GPIO_75"), 194 PINCTRL_PIN(76, "GPIO_76"), 195 PINCTRL_PIN(77, "GPIO_77"), 196 PINCTRL_PIN(78, "GPIO_78"), 197 PINCTRL_PIN(79, "GPIO_79"), 198 PINCTRL_PIN(80, "GPIO_80"), 199 PINCTRL_PIN(81, "GPIO_81"), 200 PINCTRL_PIN(82, "GPIO_82"), 201 PINCTRL_PIN(83, "GPIO_83"), 202 PINCTRL_PIN(84, "GPIO_84"), 203 PINCTRL_PIN(85, "GPIO_85"), 204 PINCTRL_PIN(86, "GPIO_86"), 205 PINCTRL_PIN(87, "GPIO_87"), 206 PINCTRL_PIN(88, "GPIO_88"), 207 PINCTRL_PIN(89, "GPIO_89"), 208 PINCTRL_PIN(90, "GPIO_90"), 209 PINCTRL_PIN(91, "GPIO_91"), 210 PINCTRL_PIN(92, "GPIO_92"), 211 PINCTRL_PIN(93, "GPIO_93"), 212 PINCTRL_PIN(94, "GPIO_94"), 213 PINCTRL_PIN(95, "GPIO_95"), 214 PINCTRL_PIN(96, "GPIO_96"), 215 PINCTRL_PIN(97, "GPIO_97"), 216 PINCTRL_PIN(98, "GPIO_98"), 217 PINCTRL_PIN(99, "GPIO_99"), 218 PINCTRL_PIN(100, "GPIO_100"), 219 PINCTRL_PIN(101, "GPIO_101"), 220 PINCTRL_PIN(102, "GPIO_102"), 221 PINCTRL_PIN(103, "GPIO_103"), 222 PINCTRL_PIN(104, "GPIO_104"), 223 PINCTRL_PIN(105, "GPIO_105"), 224 PINCTRL_PIN(106, "GPIO_106"), 225 PINCTRL_PIN(107, "GPIO_107"), 226 PINCTRL_PIN(108, "GPIO_108"), 227 PINCTRL_PIN(109, "GPIO_109"), 228 PINCTRL_PIN(110, "GPIO_110"), 229 PINCTRL_PIN(111, "GPIO_111"), 230 PINCTRL_PIN(112, "GPIO_112"), 231 PINCTRL_PIN(113, "GPIO_113"), 232 PINCTRL_PIN(114, "GPIO_114"), 233 PINCTRL_PIN(115, "GPIO_115"), 234 PINCTRL_PIN(116, "GPIO_116"), 235 PINCTRL_PIN(117, "GPIO_117"), 236 PINCTRL_PIN(118, "GPIO_118"), 237 PINCTRL_PIN(119, "GPIO_119"), 238 PINCTRL_PIN(120, "GPIO_120"), 239 PINCTRL_PIN(121, "GPIO_121"), 240 PINCTRL_PIN(122, "GPIO_122"), 241 PINCTRL_PIN(123, "GPIO_123"), 242 PINCTRL_PIN(124, "GPIO_124"), 243 PINCTRL_PIN(125, "GPIO_125"), 244 PINCTRL_PIN(126, "GPIO_126"), 245 PINCTRL_PIN(127, "GPIO_127"), 246 PINCTRL_PIN(128, "GPIO_128"), 247 PINCTRL_PIN(129, "GPIO_129"), 248 PINCTRL_PIN(130, "GPIO_130"), 249 PINCTRL_PIN(131, "GPIO_131"), 250 PINCTRL_PIN(132, "GPIO_132"), 251 PINCTRL_PIN(133, "GPIO_133"), 252 PINCTRL_PIN(134, "GPIO_134"), 253 PINCTRL_PIN(135, "GPIO_135"), 254 PINCTRL_PIN(136, "GPIO_136"), 255 PINCTRL_PIN(137, "GPIO_137"), 256 PINCTRL_PIN(138, "GPIO_138"), 257 PINCTRL_PIN(139, "GPIO_139"), 258 PINCTRL_PIN(140, "GPIO_140"), 259 PINCTRL_PIN(141, "GPIO_141"), 260 PINCTRL_PIN(142, "GPIO_142"), 261 PINCTRL_PIN(143, "GPIO_143"), 262 PINCTRL_PIN(144, "GPIO_144"), 263 PINCTRL_PIN(145, "GPIO_145"), 264 PINCTRL_PIN(146, "GPIO_146"), 265 PINCTRL_PIN(147, "GPIO_147"), 266 PINCTRL_PIN(148, "GPIO_148"), 267 PINCTRL_PIN(149, "UFS_RESET"), 268 PINCTRL_PIN(150, "SDC1_RCLK"), 269 PINCTRL_PIN(151, "SDC1_CLK"), 270 PINCTRL_PIN(152, "SDC1_CMD"), 271 PINCTRL_PIN(153, "SDC1_DATA"), 272}; 273 274#define DECLARE_MSM_GPIO_PINS(pin) \ 275 static const unsigned int gpio##pin##_pins[] = { pin } 276DECLARE_MSM_GPIO_PINS(0); 277DECLARE_MSM_GPIO_PINS(1); 278DECLARE_MSM_GPIO_PINS(2); 279DECLARE_MSM_GPIO_PINS(3); 280DECLARE_MSM_GPIO_PINS(4); 281DECLARE_MSM_GPIO_PINS(5); 282DECLARE_MSM_GPIO_PINS(6); 283DECLARE_MSM_GPIO_PINS(7); 284DECLARE_MSM_GPIO_PINS(8); 285DECLARE_MSM_GPIO_PINS(9); 286DECLARE_MSM_GPIO_PINS(10); 287DECLARE_MSM_GPIO_PINS(11); 288DECLARE_MSM_GPIO_PINS(12); 289DECLARE_MSM_GPIO_PINS(13); 290DECLARE_MSM_GPIO_PINS(14); 291DECLARE_MSM_GPIO_PINS(15); 292DECLARE_MSM_GPIO_PINS(16); 293DECLARE_MSM_GPIO_PINS(17); 294DECLARE_MSM_GPIO_PINS(18); 295DECLARE_MSM_GPIO_PINS(19); 296DECLARE_MSM_GPIO_PINS(20); 297DECLARE_MSM_GPIO_PINS(21); 298DECLARE_MSM_GPIO_PINS(22); 299DECLARE_MSM_GPIO_PINS(23); 300DECLARE_MSM_GPIO_PINS(24); 301DECLARE_MSM_GPIO_PINS(25); 302DECLARE_MSM_GPIO_PINS(26); 303DECLARE_MSM_GPIO_PINS(27); 304DECLARE_MSM_GPIO_PINS(28); 305DECLARE_MSM_GPIO_PINS(29); 306DECLARE_MSM_GPIO_PINS(30); 307DECLARE_MSM_GPIO_PINS(31); 308DECLARE_MSM_GPIO_PINS(32); 309DECLARE_MSM_GPIO_PINS(33); 310DECLARE_MSM_GPIO_PINS(34); 311DECLARE_MSM_GPIO_PINS(35); 312DECLARE_MSM_GPIO_PINS(36); 313DECLARE_MSM_GPIO_PINS(37); 314DECLARE_MSM_GPIO_PINS(38); 315DECLARE_MSM_GPIO_PINS(39); 316DECLARE_MSM_GPIO_PINS(40); 317DECLARE_MSM_GPIO_PINS(41); 318DECLARE_MSM_GPIO_PINS(42); 319DECLARE_MSM_GPIO_PINS(43); 320DECLARE_MSM_GPIO_PINS(44); 321DECLARE_MSM_GPIO_PINS(45); 322DECLARE_MSM_GPIO_PINS(46); 323DECLARE_MSM_GPIO_PINS(47); 324DECLARE_MSM_GPIO_PINS(48); 325DECLARE_MSM_GPIO_PINS(49); 326DECLARE_MSM_GPIO_PINS(50); 327DECLARE_MSM_GPIO_PINS(51); 328DECLARE_MSM_GPIO_PINS(52); 329DECLARE_MSM_GPIO_PINS(53); 330DECLARE_MSM_GPIO_PINS(54); 331DECLARE_MSM_GPIO_PINS(55); 332DECLARE_MSM_GPIO_PINS(56); 333DECLARE_MSM_GPIO_PINS(57); 334DECLARE_MSM_GPIO_PINS(58); 335DECLARE_MSM_GPIO_PINS(59); 336DECLARE_MSM_GPIO_PINS(60); 337DECLARE_MSM_GPIO_PINS(61); 338DECLARE_MSM_GPIO_PINS(62); 339DECLARE_MSM_GPIO_PINS(63); 340DECLARE_MSM_GPIO_PINS(64); 341DECLARE_MSM_GPIO_PINS(65); 342DECLARE_MSM_GPIO_PINS(66); 343DECLARE_MSM_GPIO_PINS(67); 344DECLARE_MSM_GPIO_PINS(68); 345DECLARE_MSM_GPIO_PINS(69); 346DECLARE_MSM_GPIO_PINS(70); 347DECLARE_MSM_GPIO_PINS(71); 348DECLARE_MSM_GPIO_PINS(72); 349DECLARE_MSM_GPIO_PINS(73); 350DECLARE_MSM_GPIO_PINS(74); 351DECLARE_MSM_GPIO_PINS(75); 352DECLARE_MSM_GPIO_PINS(76); 353DECLARE_MSM_GPIO_PINS(77); 354DECLARE_MSM_GPIO_PINS(78); 355DECLARE_MSM_GPIO_PINS(79); 356DECLARE_MSM_GPIO_PINS(80); 357DECLARE_MSM_GPIO_PINS(81); 358DECLARE_MSM_GPIO_PINS(82); 359DECLARE_MSM_GPIO_PINS(83); 360DECLARE_MSM_GPIO_PINS(84); 361DECLARE_MSM_GPIO_PINS(85); 362DECLARE_MSM_GPIO_PINS(86); 363DECLARE_MSM_GPIO_PINS(87); 364DECLARE_MSM_GPIO_PINS(88); 365DECLARE_MSM_GPIO_PINS(89); 366DECLARE_MSM_GPIO_PINS(90); 367DECLARE_MSM_GPIO_PINS(91); 368DECLARE_MSM_GPIO_PINS(92); 369DECLARE_MSM_GPIO_PINS(93); 370DECLARE_MSM_GPIO_PINS(94); 371DECLARE_MSM_GPIO_PINS(95); 372DECLARE_MSM_GPIO_PINS(96); 373DECLARE_MSM_GPIO_PINS(97); 374DECLARE_MSM_GPIO_PINS(98); 375DECLARE_MSM_GPIO_PINS(99); 376DECLARE_MSM_GPIO_PINS(100); 377DECLARE_MSM_GPIO_PINS(101); 378DECLARE_MSM_GPIO_PINS(102); 379DECLARE_MSM_GPIO_PINS(103); 380DECLARE_MSM_GPIO_PINS(104); 381DECLARE_MSM_GPIO_PINS(105); 382DECLARE_MSM_GPIO_PINS(106); 383DECLARE_MSM_GPIO_PINS(107); 384DECLARE_MSM_GPIO_PINS(108); 385DECLARE_MSM_GPIO_PINS(109); 386DECLARE_MSM_GPIO_PINS(110); 387DECLARE_MSM_GPIO_PINS(111); 388DECLARE_MSM_GPIO_PINS(112); 389DECLARE_MSM_GPIO_PINS(113); 390DECLARE_MSM_GPIO_PINS(114); 391DECLARE_MSM_GPIO_PINS(115); 392DECLARE_MSM_GPIO_PINS(116); 393DECLARE_MSM_GPIO_PINS(117); 394DECLARE_MSM_GPIO_PINS(118); 395DECLARE_MSM_GPIO_PINS(119); 396DECLARE_MSM_GPIO_PINS(120); 397DECLARE_MSM_GPIO_PINS(121); 398DECLARE_MSM_GPIO_PINS(122); 399DECLARE_MSM_GPIO_PINS(123); 400DECLARE_MSM_GPIO_PINS(124); 401DECLARE_MSM_GPIO_PINS(125); 402DECLARE_MSM_GPIO_PINS(126); 403DECLARE_MSM_GPIO_PINS(127); 404DECLARE_MSM_GPIO_PINS(128); 405DECLARE_MSM_GPIO_PINS(129); 406DECLARE_MSM_GPIO_PINS(130); 407DECLARE_MSM_GPIO_PINS(131); 408DECLARE_MSM_GPIO_PINS(132); 409DECLARE_MSM_GPIO_PINS(133); 410DECLARE_MSM_GPIO_PINS(134); 411DECLARE_MSM_GPIO_PINS(135); 412DECLARE_MSM_GPIO_PINS(136); 413DECLARE_MSM_GPIO_PINS(137); 414DECLARE_MSM_GPIO_PINS(138); 415DECLARE_MSM_GPIO_PINS(139); 416DECLARE_MSM_GPIO_PINS(140); 417DECLARE_MSM_GPIO_PINS(141); 418DECLARE_MSM_GPIO_PINS(142); 419DECLARE_MSM_GPIO_PINS(143); 420DECLARE_MSM_GPIO_PINS(144); 421DECLARE_MSM_GPIO_PINS(145); 422DECLARE_MSM_GPIO_PINS(146); 423DECLARE_MSM_GPIO_PINS(147); 424DECLARE_MSM_GPIO_PINS(148); 425 426static const unsigned int ufs_reset_pins[] = { 149 }; 427static const unsigned int sdc1_rclk_pins[] = { 150 }; 428static const unsigned int sdc1_clk_pins[] = { 151 }; 429static const unsigned int sdc1_cmd_pins[] = { 152 }; 430static const unsigned int sdc1_data_pins[] = { 153 }; 431 432enum sa8775p_functions { 433 msm_mux_gpio, 434 msm_mux_atest_char, 435 msm_mux_atest_usb2, 436 msm_mux_audio_ref, 437 msm_mux_cam_mclk, 438 msm_mux_cci_async, 439 msm_mux_cci_i2c, 440 msm_mux_cci_timer0, 441 msm_mux_cci_timer1, 442 msm_mux_cci_timer2, 443 msm_mux_cci_timer3, 444 msm_mux_cci_timer4, 445 msm_mux_cci_timer5, 446 msm_mux_cci_timer6, 447 msm_mux_cci_timer7, 448 msm_mux_cci_timer8, 449 msm_mux_cci_timer9, 450 msm_mux_cri_trng, 451 msm_mux_cri_trng0, 452 msm_mux_cri_trng1, 453 msm_mux_dbg_out, 454 msm_mux_ddr_bist, 455 msm_mux_ddr_pxi0, 456 msm_mux_ddr_pxi1, 457 msm_mux_ddr_pxi2, 458 msm_mux_ddr_pxi3, 459 msm_mux_ddr_pxi4, 460 msm_mux_ddr_pxi5, 461 msm_mux_edp0_hot, 462 msm_mux_edp0_lcd, 463 msm_mux_edp1_hot, 464 msm_mux_edp1_lcd, 465 msm_mux_edp2_hot, 466 msm_mux_edp2_lcd, 467 msm_mux_edp3_hot, 468 msm_mux_edp3_lcd, 469 msm_mux_emac0_mcg0, 470 msm_mux_emac0_mcg1, 471 msm_mux_emac0_mcg2, 472 msm_mux_emac0_mcg3, 473 msm_mux_emac0_mdc, 474 msm_mux_emac0_mdio, 475 msm_mux_emac0_ptp_aux, 476 msm_mux_emac0_ptp_pps, 477 msm_mux_emac1_mcg0, 478 msm_mux_emac1_mcg1, 479 msm_mux_emac1_mcg2, 480 msm_mux_emac1_mcg3, 481 msm_mux_emac1_mdc, 482 msm_mux_emac1_mdio, 483 msm_mux_emac1_ptp_aux, 484 msm_mux_emac1_ptp_pps, 485 msm_mux_gcc_gp1, 486 msm_mux_gcc_gp2, 487 msm_mux_gcc_gp3, 488 msm_mux_gcc_gp4, 489 msm_mux_gcc_gp5, 490 msm_mux_hs0_mi2s, 491 msm_mux_hs1_mi2s, 492 msm_mux_hs2_mi2s, 493 msm_mux_ibi_i3c, 494 msm_mux_jitter_bist, 495 msm_mux_mdp0_vsync0, 496 msm_mux_mdp0_vsync1, 497 msm_mux_mdp0_vsync2, 498 msm_mux_mdp0_vsync3, 499 msm_mux_mdp0_vsync4, 500 msm_mux_mdp0_vsync5, 501 msm_mux_mdp0_vsync6, 502 msm_mux_mdp0_vsync7, 503 msm_mux_mdp0_vsync8, 504 msm_mux_mdp1_vsync0, 505 msm_mux_mdp1_vsync1, 506 msm_mux_mdp1_vsync2, 507 msm_mux_mdp1_vsync3, 508 msm_mux_mdp1_vsync4, 509 msm_mux_mdp1_vsync5, 510 msm_mux_mdp1_vsync6, 511 msm_mux_mdp1_vsync7, 512 msm_mux_mdp1_vsync8, 513 msm_mux_mdp_vsync, 514 msm_mux_mi2s1_data0, 515 msm_mux_mi2s1_data1, 516 msm_mux_mi2s1_sck, 517 msm_mux_mi2s1_ws, 518 msm_mux_mi2s2_data0, 519 msm_mux_mi2s2_data1, 520 msm_mux_mi2s2_sck, 521 msm_mux_mi2s2_ws, 522 msm_mux_mi2s_mclk0, 523 msm_mux_mi2s_mclk1, 524 msm_mux_pcie0_clkreq, 525 msm_mux_pcie1_clkreq, 526 msm_mux_phase_flag, 527 msm_mux_pll_bist, 528 msm_mux_pll_clk, 529 msm_mux_prng_rosc0, 530 msm_mux_prng_rosc1, 531 msm_mux_prng_rosc2, 532 msm_mux_prng_rosc3, 533 msm_mux_qdss_cti, 534 msm_mux_qdss_gpio, 535 msm_mux_qup0_se0, 536 msm_mux_qup0_se1, 537 msm_mux_qup0_se2, 538 msm_mux_qup0_se3, 539 msm_mux_qup0_se4, 540 msm_mux_qup0_se5, 541 msm_mux_qup1_se0, 542 msm_mux_qup1_se1, 543 msm_mux_qup1_se2, 544 msm_mux_qup1_se3, 545 msm_mux_qup1_se4, 546 msm_mux_qup1_se5, 547 msm_mux_qup1_se6, 548 msm_mux_qup2_se0, 549 msm_mux_qup2_se1, 550 msm_mux_qup2_se2, 551 msm_mux_qup2_se3, 552 msm_mux_qup2_se4, 553 msm_mux_qup2_se5, 554 msm_mux_qup2_se6, 555 msm_mux_qup3_se0, 556 msm_mux_sail_top, 557 msm_mux_sailss_emac0, 558 msm_mux_sailss_ospi, 559 msm_mux_sgmii_phy, 560 msm_mux_tb_trig, 561 msm_mux_tgu_ch0, 562 msm_mux_tgu_ch1, 563 msm_mux_tgu_ch2, 564 msm_mux_tgu_ch3, 565 msm_mux_tgu_ch4, 566 msm_mux_tgu_ch5, 567 msm_mux_tsense_pwm1, 568 msm_mux_tsense_pwm2, 569 msm_mux_tsense_pwm3, 570 msm_mux_tsense_pwm4, 571 msm_mux_usb2phy_ac, 572 msm_mux_vsense_trigger, 573 msm_mux__, 574}; 575 576static const char * const gpio_groups[] = { 577 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 578 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 579 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 580 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 581 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 582 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 583 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 584 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 585 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 586 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 587 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 588 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 589 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 590 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 591 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 592 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 593 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 594 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", 595 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", 596 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", 597 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", 598 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", 599 "gpio147", "gpio148", 600}; 601 602static const char * const atest_char_groups[] = { 603 "gpio27", "gpio58", "gpio59", "gpio89", "gpio90", 604}; 605 606static const char * const atest_usb2_groups[] = { 607 "gpio58", "gpio59", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", 608 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", 609 "gpio105", 610}; 611 612static const char * const audio_ref_groups[] = { 613 "gpio113", 614}; 615 616static const char * const cam_mclk_groups[] = { 617 "gpio72", "gpio73", "gpio74", "gpio75", 618}; 619 620static const char * const cci_async_groups[] = { 621 "gpio50", "gpio66", "gpio68", "gpio69", "gpio70", "gpio71", 622}; 623 624static const char * const cci_i2c_groups[] = { 625 "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", 626 "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", 627 "gpio66", "gpio67", 628}; 629 630static const char * const cci_timer0_groups[] = { 631 "gpio68", 632}; 633 634static const char * const cci_timer1_groups[] = { 635 "gpio69", 636}; 637 638static const char * const cci_timer2_groups[] = { 639 "gpio70", 640}; 641 642static const char * const cci_timer3_groups[] = { 643 "gpio71", 644}; 645 646static const char * const cci_timer4_groups[] = { 647 "gpio52", 648}; 649 650static const char * const cci_timer5_groups[] = { 651 "gpio53", 652}; 653 654static const char * const cci_timer6_groups[] = { 655 "gpio54", 656}; 657 658static const char * const cci_timer7_groups[] = { 659 "gpio55", 660}; 661 662static const char * const cci_timer8_groups[] = { 663 "gpio56", 664}; 665 666static const char * const cci_timer9_groups[] = { 667 "gpio57", 668}; 669 670static const char * const cri_trng_groups[] = { 671 "gpio99", 672}; 673 674static const char * const cri_trng0_groups[] = { 675 "gpio97", 676}; 677 678static const char * const cri_trng1_groups[] = { 679 "gpio98", 680}; 681 682static const char * const dbg_out_groups[] = { 683 "gpio144", 684}; 685 686static const char * const ddr_bist_groups[] = { 687 "gpio56", "gpio57", "gpio58", "gpio59", 688}; 689 690static const char * const ddr_pxi0_groups[] = { 691 "gpio33", "gpio34", 692}; 693 694static const char * const ddr_pxi1_groups[] = { 695 "gpio52", "gpio53", 696}; 697 698static const char * const ddr_pxi2_groups[] = { 699 "gpio55", "gpio86", 700}; 701 702static const char * const ddr_pxi3_groups[] = { 703 "gpio87", "gpio88", 704}; 705 706static const char * const ddr_pxi4_groups[] = { 707 "gpio89", "gpio90", 708}; 709 710static const char * const ddr_pxi5_groups[] = { 711 "gpio118", "gpio119", 712}; 713 714static const char * const edp0_hot_groups[] = { 715 "gpio101", 716}; 717 718static const char * const edp0_lcd_groups[] = { 719 "gpio44", 720}; 721 722static const char * const edp1_hot_groups[] = { 723 "gpio102", 724}; 725 726static const char * const edp1_lcd_groups[] = { 727 "gpio45", 728}; 729 730static const char * const edp2_hot_groups[] = { 731 "gpio104", 732}; 733 734static const char * const edp2_lcd_groups[] = { 735 "gpio48", 736}; 737 738static const char * const edp3_hot_groups[] = { 739 "gpio103", 740}; 741 742static const char * const edp3_lcd_groups[] = { 743 "gpio49", 744}; 745 746static const char * const emac0_mcg0_groups[] = { 747 "gpio12", 748}; 749 750static const char * const emac0_mcg1_groups[] = { 751 "gpio13", 752}; 753 754static const char * const emac0_mcg2_groups[] = { 755 "gpio14", 756}; 757 758static const char * const emac0_mcg3_groups[] = { 759 "gpio15", 760}; 761 762static const char * const emac0_mdc_groups[] = { 763 "gpio8", 764}; 765 766static const char * const emac0_mdio_groups[] = { 767 "gpio9", 768}; 769 770static const char * const emac0_ptp_aux_groups[] = { 771 "gpio6", "gpio10", "gpio11", "gpio12", 772}; 773 774static const char * const emac0_ptp_pps_groups[] = { 775 "gpio6", "gpio10", "gpio11", "gpio12", 776}; 777 778static const char * const emac1_mcg0_groups[] = { 779 "gpio16", 780 781}; 782 783static const char * const emac1_mcg1_groups[] = { 784 "gpio17", 785}; 786 787static const char * const emac1_mcg2_groups[] = { 788 "gpio18", 789}; 790 791static const char * const emac1_mcg3_groups[] = { 792 "gpio19", 793}; 794 795static const char * const emac1_mdc_groups[] = { 796 "gpio20", 797}; 798 799static const char * const emac1_mdio_groups[] = { 800 "gpio21", 801}; 802 803static const char * const emac1_ptp_aux_groups[] = { 804 "gpio6", "gpio10", "gpio11", "gpio12", 805}; 806 807static const char * const emac1_ptp_pps_groups[] = { 808 "gpio6", "gpio10", "gpio11", "gpio12", 809}; 810 811static const char * const gcc_gp1_groups[] = { 812 "gpio51", "gpio82", 813}; 814 815static const char * const gcc_gp2_groups[] = { 816 "gpio52", "gpio83", 817}; 818 819static const char * const gcc_gp3_groups[] = { 820 "gpio53", "gpio84", 821}; 822 823static const char * const gcc_gp4_groups[] = { 824 "gpio33", "gpio55", 825}; 826 827static const char * const gcc_gp5_groups[] = { 828 "gpio34", "gpio42", 829}; 830 831static const char * const hs0_mi2s_groups[] = { 832 "gpio114", "gpio115", "gpio116", "gpio117", 833}; 834 835static const char * const hs1_mi2s_groups[] = { 836 "gpio118", "gpio119", "gpio120", "gpio121", 837}; 838 839static const char * const hs2_mi2s_groups[] = { 840 "gpio122", "gpio123", "gpio124", "gpio125", 841}; 842 843static const char * const ibi_i3c_groups[] = { 844 "gpio40", "gpio41", "gpio42", "gpio43", "gpio80", "gpio81", "gpio84", 845 "gpio85", 846}; 847 848static const char * const jitter_bist_groups[] = { 849 "gpio86", 850}; 851 852static const char * const mdp0_vsync0_groups[] = { 853 "gpio57", 854}; 855 856static const char * const mdp0_vsync1_groups[] = { 857 "gpio58", 858}; 859 860static const char * const mdp0_vsync2_groups[] = { 861 "gpio59", 862}; 863 864static const char * const mdp0_vsync3_groups[] = { 865 "gpio80", 866}; 867 868static const char * const mdp0_vsync4_groups[] = { 869 "gpio81", 870}; 871 872static const char * const mdp0_vsync5_groups[] = { 873 "gpio91", 874}; 875 876static const char * const mdp0_vsync6_groups[] = { 877 "gpio92", 878}; 879 880static const char * const mdp0_vsync7_groups[] = { 881 "gpio93", 882}; 883 884static const char * const mdp0_vsync8_groups[] = { 885 "gpio94", 886}; 887 888static const char * const mdp1_vsync0_groups[] = { 889 "gpio40", 890}; 891 892static const char * const mdp1_vsync1_groups[] = { 893 "gpio41", 894}; 895 896static const char * const mdp1_vsync2_groups[] = { 897 "gpio42", 898}; 899 900static const char * const mdp1_vsync3_groups[] = { 901 "gpio43", 902}; 903 904static const char * const mdp1_vsync4_groups[] = { 905 "gpio46", 906}; 907 908static const char * const mdp1_vsync5_groups[] = { 909 "gpio47", 910}; 911 912static const char * const mdp1_vsync6_groups[] = { 913 "gpio51", 914}; 915 916static const char * const mdp1_vsync7_groups[] = { 917 "gpio52", 918}; 919 920static const char * const mdp1_vsync8_groups[] = { 921 "gpio50", 922}; 923 924static const char * const mdp_vsync_groups[] = { 925 "gpio82", "gpio83", "gpio84", 926}; 927 928static const char * const mi2s1_data0_groups[] = { 929 "gpio108", 930}; 931 932static const char * const mi2s1_data1_groups[] = { 933 "gpio109", 934}; 935 936static const char * const mi2s1_sck_groups[] = { 937 "gpio106", 938}; 939 940static const char * const mi2s1_ws_groups[] = { 941 "gpio107", 942}; 943 944static const char * const mi2s2_data0_groups[] = { 945 "gpio112", 946}; 947 948static const char * const mi2s2_data1_groups[] = { 949 "gpio113", 950}; 951 952static const char * const mi2s2_sck_groups[] = { 953 "gpio110", 954}; 955 956static const char * const mi2s2_ws_groups[] = { 957 "gpio111", 958}; 959 960static const char * const mi2s_mclk0_groups[] = { 961 "gpio105", 962}; 963 964static const char * const mi2s_mclk1_groups[] = { 965 "gpio117", 966}; 967 968static const char * const pcie0_clkreq_groups[] = { 969 "gpio1", 970}; 971 972static const char * const pcie1_clkreq_groups[] = { 973 "gpio3", 974}; 975 976static const char * const phase_flag_groups[] = { 977 "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", 978 "gpio32", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio56", 979 "gpio57", "gpio98", "gpio99", "gpio106", "gpio107", "gpio108", 980 "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", 981 "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", 982}; 983 984static const char * const pll_bist_groups[] = { 985 "gpio114", 986}; 987 988static const char * const pll_clk_groups[] = { 989 "gpio87", 990}; 991 992static const char * const prng_rosc0_groups[] = { 993 "gpio101", 994}; 995 996static const char * const prng_rosc1_groups[] = { 997 "gpio102", 998}; 999 1000static const char * const prng_rosc2_groups[] = { 1001 "gpio103", 1002}; 1003 1004static const char * const prng_rosc3_groups[] = { 1005 "gpio104", 1006}; 1007 1008static const char * const qdss_cti_groups[] = { 1009 "gpio26", "gpio27", "gpio38", "gpio39", "gpio48", "gpio49", "gpio50", 1010 "gpio51", 1011}; 1012 1013static const char * const qdss_gpio_groups[] = { 1014 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio28", 1015 "gpio29", "gpio30", "gpio31", "gpio60", "gpio61", "gpio62", "gpio63", 1016 "gpio64", "gpio65", "gpio66", "gpio67", "gpio105", "gpio106", "gpio107", 1017 "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", 1018 "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", 1019 "gpio120", "gpio121", "gpio122", 1020}; 1021 1022static const char * const qup0_se0_groups[] = { 1023 "gpio20", "gpio21", "gpio22", "gpio23", 1024}; 1025 1026static const char * const qup0_se1_groups[] = { 1027 "gpio24", "gpio25", "gpio26", "gpio27", 1028}; 1029 1030static const char * const qup0_se2_groups[] = { 1031 "gpio36", "gpio37", "gpio38", "gpio39", 1032}; 1033 1034static const char * const qup0_se3_groups[] = { 1035 "gpio28", "gpio29", "gpio30", "gpio31", 1036}; 1037 1038static const char * const qup0_se4_groups[] = { 1039 "gpio32", "gpio33", "gpio34", "gpio35", 1040}; 1041 1042static const char * const qup0_se5_groups[] = { 1043 "gpio36", "gpio37", "gpio38", "gpio39", 1044}; 1045 1046static const char * const qup1_se0_groups[] = { 1047 "gpio40", "gpio41", "gpio42", "gpio43", 1048}; 1049 1050static const char * const qup1_se1_groups[] = { 1051 "gpio40", "gpio41", "gpio42", "gpio43", 1052}; 1053 1054static const char * const qup1_se2_groups[] = { 1055 "gpio44", "gpio45", "gpio46", "gpio47", 1056}; 1057 1058static const char * const qup1_se3_groups[] = { 1059 "gpio44", "gpio45", "gpio46", "gpio47", 1060}; 1061 1062static const char * const qup1_se4_groups[] = { 1063 "gpio48", "gpio49", "gpio50", "gpio51", 1064}; 1065 1066static const char * const qup1_se5_groups[] = { 1067 "gpio52", "gpio53", "gpio54", "gpio55", 1068}; 1069 1070static const char * const qup1_se6_groups[] = { 1071 "gpio56", "gpio56", "gpio57", "gpio57", 1072}; 1073 1074static const char * const qup2_se0_groups[] = { 1075 "gpio80", "gpio81", "gpio82", "gpio83", 1076}; 1077 1078static const char * const qup2_se1_groups[] = { 1079 "gpio84", "gpio85", "gpio99", "gpio100", 1080}; 1081 1082static const char * const qup2_se2_groups[] = { 1083 "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", 1084}; 1085 1086static const char * const qup2_se3_groups[] = { 1087 "gpio91", "gpio92", "gpio93", "gpio94", 1088}; 1089 1090static const char * const qup2_se4_groups[] = { 1091 "gpio95", "gpio96", "gpio97", "gpio98", 1092}; 1093 1094static const char * const qup2_se5_groups[] = { 1095 "gpio84", "gpio85", "gpio99", "gpio100", 1096}; 1097 1098static const char * const qup2_se6_groups[] = { 1099 "gpio95", "gpio96", "gpio97", "gpio98", 1100}; 1101 1102static const char * const qup3_se0_groups[] = { 1103 "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", 1104}; 1105 1106static const char * const sail_top_groups[] = { 1107 "gpio13", "gpio14", "gpio15", "gpio16", 1108}; 1109 1110static const char * const sailss_emac0_groups[] = { 1111 "gpio18", "gpio19", 1112}; 1113 1114static const char * const sailss_ospi_groups[] = { 1115 "gpio18", "gpio19", 1116}; 1117 1118static const char * const sgmii_phy_groups[] = { 1119 "gpio7", "gpio26", 1120}; 1121 1122static const char * const tb_trig_groups[] = { 1123 "gpio17", "gpio17", 1124}; 1125 1126static const char * const tgu_ch0_groups[] = { 1127 "gpio46", 1128}; 1129 1130static const char * const tgu_ch1_groups[] = { 1131 "gpio47", 1132}; 1133 1134static const char * const tgu_ch2_groups[] = { 1135 "gpio36", 1136}; 1137 1138static const char * const tgu_ch3_groups[] = { 1139 "gpio37", 1140}; 1141 1142static const char * const tgu_ch4_groups[] = { 1143 "gpio38", 1144}; 1145 1146static const char * const tgu_ch5_groups[] = { 1147 "gpio39", 1148}; 1149 1150static const char * const tsense_pwm1_groups[] = { 1151 "gpio104", 1152}; 1153 1154static const char * const tsense_pwm2_groups[] = { 1155 "gpio103", 1156}; 1157 1158static const char * const tsense_pwm3_groups[] = { 1159 "gpio102", 1160}; 1161 1162static const char * const tsense_pwm4_groups[] = { 1163 "gpio101", 1164}; 1165 1166static const char * const usb2phy_ac_groups[] = { 1167 "gpio10", "gpio11", "gpio12", 1168}; 1169 1170static const char * const vsense_trigger_groups[] = { 1171 "gpio111", 1172}; 1173 1174static const struct pinfunction sa8775p_functions[] = { 1175 MSM_PIN_FUNCTION(gpio), 1176 MSM_PIN_FUNCTION(atest_char), 1177 MSM_PIN_FUNCTION(atest_usb2), 1178 MSM_PIN_FUNCTION(audio_ref), 1179 MSM_PIN_FUNCTION(cam_mclk), 1180 MSM_PIN_FUNCTION(cci_async), 1181 MSM_PIN_FUNCTION(cci_i2c), 1182 MSM_PIN_FUNCTION(cci_timer0), 1183 MSM_PIN_FUNCTION(cci_timer1), 1184 MSM_PIN_FUNCTION(cci_timer2), 1185 MSM_PIN_FUNCTION(cci_timer3), 1186 MSM_PIN_FUNCTION(cci_timer4), 1187 MSM_PIN_FUNCTION(cci_timer5), 1188 MSM_PIN_FUNCTION(cci_timer6), 1189 MSM_PIN_FUNCTION(cci_timer7), 1190 MSM_PIN_FUNCTION(cci_timer8), 1191 MSM_PIN_FUNCTION(cci_timer9), 1192 MSM_PIN_FUNCTION(cri_trng), 1193 MSM_PIN_FUNCTION(cri_trng0), 1194 MSM_PIN_FUNCTION(cri_trng1), 1195 MSM_PIN_FUNCTION(dbg_out), 1196 MSM_PIN_FUNCTION(ddr_bist), 1197 MSM_PIN_FUNCTION(ddr_pxi0), 1198 MSM_PIN_FUNCTION(ddr_pxi1), 1199 MSM_PIN_FUNCTION(ddr_pxi2), 1200 MSM_PIN_FUNCTION(ddr_pxi3), 1201 MSM_PIN_FUNCTION(ddr_pxi4), 1202 MSM_PIN_FUNCTION(ddr_pxi5), 1203 MSM_PIN_FUNCTION(edp0_hot), 1204 MSM_PIN_FUNCTION(edp0_lcd), 1205 MSM_PIN_FUNCTION(edp1_hot), 1206 MSM_PIN_FUNCTION(edp1_lcd), 1207 MSM_PIN_FUNCTION(edp2_hot), 1208 MSM_PIN_FUNCTION(edp2_lcd), 1209 MSM_PIN_FUNCTION(edp3_hot), 1210 MSM_PIN_FUNCTION(edp3_lcd), 1211 MSM_PIN_FUNCTION(emac0_mcg0), 1212 MSM_PIN_FUNCTION(emac0_mcg1), 1213 MSM_PIN_FUNCTION(emac0_mcg2), 1214 MSM_PIN_FUNCTION(emac0_mcg3), 1215 MSM_PIN_FUNCTION(emac0_mdc), 1216 MSM_PIN_FUNCTION(emac0_mdio), 1217 MSM_PIN_FUNCTION(emac0_ptp_aux), 1218 MSM_PIN_FUNCTION(emac0_ptp_pps), 1219 MSM_PIN_FUNCTION(emac1_mcg0), 1220 MSM_PIN_FUNCTION(emac1_mcg1), 1221 MSM_PIN_FUNCTION(emac1_mcg2), 1222 MSM_PIN_FUNCTION(emac1_mcg3), 1223 MSM_PIN_FUNCTION(emac1_mdc), 1224 MSM_PIN_FUNCTION(emac1_mdio), 1225 MSM_PIN_FUNCTION(emac1_ptp_aux), 1226 MSM_PIN_FUNCTION(emac1_ptp_pps), 1227 MSM_PIN_FUNCTION(gcc_gp1), 1228 MSM_PIN_FUNCTION(gcc_gp2), 1229 MSM_PIN_FUNCTION(gcc_gp3), 1230 MSM_PIN_FUNCTION(gcc_gp4), 1231 MSM_PIN_FUNCTION(gcc_gp5), 1232 MSM_PIN_FUNCTION(hs0_mi2s), 1233 MSM_PIN_FUNCTION(hs1_mi2s), 1234 MSM_PIN_FUNCTION(hs2_mi2s), 1235 MSM_PIN_FUNCTION(ibi_i3c), 1236 MSM_PIN_FUNCTION(jitter_bist), 1237 MSM_PIN_FUNCTION(mdp0_vsync0), 1238 MSM_PIN_FUNCTION(mdp0_vsync1), 1239 MSM_PIN_FUNCTION(mdp0_vsync2), 1240 MSM_PIN_FUNCTION(mdp0_vsync3), 1241 MSM_PIN_FUNCTION(mdp0_vsync4), 1242 MSM_PIN_FUNCTION(mdp0_vsync5), 1243 MSM_PIN_FUNCTION(mdp0_vsync6), 1244 MSM_PIN_FUNCTION(mdp0_vsync7), 1245 MSM_PIN_FUNCTION(mdp0_vsync8), 1246 MSM_PIN_FUNCTION(mdp1_vsync0), 1247 MSM_PIN_FUNCTION(mdp1_vsync1), 1248 MSM_PIN_FUNCTION(mdp1_vsync2), 1249 MSM_PIN_FUNCTION(mdp1_vsync3), 1250 MSM_PIN_FUNCTION(mdp1_vsync4), 1251 MSM_PIN_FUNCTION(mdp1_vsync5), 1252 MSM_PIN_FUNCTION(mdp1_vsync6), 1253 MSM_PIN_FUNCTION(mdp1_vsync7), 1254 MSM_PIN_FUNCTION(mdp1_vsync8), 1255 MSM_PIN_FUNCTION(mdp_vsync), 1256 MSM_PIN_FUNCTION(mi2s1_data0), 1257 MSM_PIN_FUNCTION(mi2s1_data1), 1258 MSM_PIN_FUNCTION(mi2s1_sck), 1259 MSM_PIN_FUNCTION(mi2s1_ws), 1260 MSM_PIN_FUNCTION(mi2s2_data0), 1261 MSM_PIN_FUNCTION(mi2s2_data1), 1262 MSM_PIN_FUNCTION(mi2s2_sck), 1263 MSM_PIN_FUNCTION(mi2s2_ws), 1264 MSM_PIN_FUNCTION(mi2s_mclk0), 1265 MSM_PIN_FUNCTION(mi2s_mclk1), 1266 MSM_PIN_FUNCTION(pcie0_clkreq), 1267 MSM_PIN_FUNCTION(pcie1_clkreq), 1268 MSM_PIN_FUNCTION(phase_flag), 1269 MSM_PIN_FUNCTION(pll_bist), 1270 MSM_PIN_FUNCTION(pll_clk), 1271 MSM_PIN_FUNCTION(prng_rosc0), 1272 MSM_PIN_FUNCTION(prng_rosc1), 1273 MSM_PIN_FUNCTION(prng_rosc2), 1274 MSM_PIN_FUNCTION(prng_rosc3), 1275 MSM_PIN_FUNCTION(qdss_cti), 1276 MSM_PIN_FUNCTION(qdss_gpio), 1277 MSM_PIN_FUNCTION(qup0_se0), 1278 MSM_PIN_FUNCTION(qup0_se1), 1279 MSM_PIN_FUNCTION(qup0_se2), 1280 MSM_PIN_FUNCTION(qup0_se3), 1281 MSM_PIN_FUNCTION(qup0_se4), 1282 MSM_PIN_FUNCTION(qup0_se5), 1283 MSM_PIN_FUNCTION(qup1_se0), 1284 MSM_PIN_FUNCTION(qup1_se1), 1285 MSM_PIN_FUNCTION(qup1_se2), 1286 MSM_PIN_FUNCTION(qup1_se3), 1287 MSM_PIN_FUNCTION(qup1_se4), 1288 MSM_PIN_FUNCTION(qup1_se5), 1289 MSM_PIN_FUNCTION(qup1_se6), 1290 MSM_PIN_FUNCTION(qup2_se0), 1291 MSM_PIN_FUNCTION(qup2_se1), 1292 MSM_PIN_FUNCTION(qup2_se2), 1293 MSM_PIN_FUNCTION(qup2_se3), 1294 MSM_PIN_FUNCTION(qup2_se4), 1295 MSM_PIN_FUNCTION(qup2_se5), 1296 MSM_PIN_FUNCTION(qup2_se6), 1297 MSM_PIN_FUNCTION(qup3_se0), 1298 MSM_PIN_FUNCTION(sail_top), 1299 MSM_PIN_FUNCTION(sailss_emac0), 1300 MSM_PIN_FUNCTION(sailss_ospi), 1301 MSM_PIN_FUNCTION(sgmii_phy), 1302 MSM_PIN_FUNCTION(tb_trig), 1303 MSM_PIN_FUNCTION(tgu_ch0), 1304 MSM_PIN_FUNCTION(tgu_ch1), 1305 MSM_PIN_FUNCTION(tgu_ch2), 1306 MSM_PIN_FUNCTION(tgu_ch3), 1307 MSM_PIN_FUNCTION(tgu_ch4), 1308 MSM_PIN_FUNCTION(tgu_ch5), 1309 MSM_PIN_FUNCTION(tsense_pwm1), 1310 MSM_PIN_FUNCTION(tsense_pwm2), 1311 MSM_PIN_FUNCTION(tsense_pwm3), 1312 MSM_PIN_FUNCTION(tsense_pwm4), 1313 MSM_PIN_FUNCTION(usb2phy_ac), 1314 MSM_PIN_FUNCTION(vsense_trigger), 1315}; 1316 1317/* 1318 * Every pin is maintained as a single group, and missing or non-existing pin 1319 * would be maintained as dummy group to synchronize pin group index with 1320 * pin descriptor registered with pinctrl core. 1321 * Clients would not be able to request these dummy pin groups. 1322 */ 1323static const struct msm_pingroup sa8775p_groups[] = { 1324 [0] = PINGROUP(0, _, _, _, _, _, _, _, _, _), 1325 [1] = PINGROUP(1, pcie0_clkreq, _, _, _, _, _, _, _, _), 1326 [2] = PINGROUP(2, _, _, _, _, _, _, _, _, _), 1327 [3] = PINGROUP(3, pcie1_clkreq, _, _, _, _, _, _, _, _), 1328 [4] = PINGROUP(4, _, _, _, _, _, _, _, _, _), 1329 [5] = PINGROUP(5, _, _, _, _, _, _, _, _, _), 1330 [6] = PINGROUP(6, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, 1331 _, _, _, _, _), 1332 [7] = PINGROUP(7, sgmii_phy, _, _, _, _, _, _, _, _), 1333 [8] = PINGROUP(8, emac0_mdc, _, _, _, _, _, _, _, _), 1334 [9] = PINGROUP(9, emac0_mdio, _, _, _, _, _, _, _, _), 1335 [10] = PINGROUP(10, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, 1336 _, _, _, _), 1337 [11] = PINGROUP(11, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, 1338 _, _, _, _), 1339 [12] = PINGROUP(12, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, 1340 emac0_mcg0, _, _, _), 1341 [13] = PINGROUP(13, qup3_se0, emac0_mcg1, _, _, sail_top, _, _, _, _), 1342 [14] = PINGROUP(14, qup3_se0, emac0_mcg2, _, _, sail_top, _, _, _, _), 1343 [15] = PINGROUP(15, qup3_se0, emac0_mcg3, _, _, sail_top, _, _, _, _), 1344 [16] = PINGROUP(16, qup3_se0, emac1_mcg0, _, _, sail_top, _, _, _, _), 1345 [17] = PINGROUP(17, qup3_se0, tb_trig, tb_trig, emac1_mcg1, _, _, _, _, _), 1346 [18] = PINGROUP(18, qup3_se0, emac1_mcg2, _, _, sailss_ospi, sailss_emac0, _, _, _), 1347 [19] = PINGROUP(19, qup3_se0, emac1_mcg3, _, _, sailss_ospi, sailss_emac0, _, _, _), 1348 [20] = PINGROUP(20, qup0_se0, emac1_mdc, qdss_gpio, _, _, _, _, _, _), 1349 [21] = PINGROUP(21, qup0_se0, emac1_mdio, qdss_gpio, _, _, _, _, _, _), 1350 [22] = PINGROUP(22, qup0_se0, qdss_gpio, _, _, _, _, _, _, _), 1351 [23] = PINGROUP(23, qup0_se0, qdss_gpio, _, _, _, _, _, _, _), 1352 [24] = PINGROUP(24, qup0_se1, qdss_gpio, _, _, _, _, _, _, _), 1353 [25] = PINGROUP(25, qup0_se1, phase_flag, _, qdss_gpio, _, _, _, _, _), 1354 [26] = PINGROUP(26, sgmii_phy, qup0_se1, qdss_cti, phase_flag, _, _, _, _, _), 1355 [27] = PINGROUP(27, qup0_se1, qdss_cti, phase_flag, _, atest_char, _, _, _, _), 1356 [28] = PINGROUP(28, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), 1357 [29] = PINGROUP(29, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), 1358 [30] = PINGROUP(30, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), 1359 [31] = PINGROUP(31, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), 1360 [32] = PINGROUP(32, qup0_se4, phase_flag, _, _, _, _, _, _, _), 1361 [33] = PINGROUP(33, qup0_se4, gcc_gp4, _, ddr_pxi0, _, _, _, _, _), 1362 [34] = PINGROUP(34, qup0_se4, gcc_gp5, _, ddr_pxi0, _, _, _, _, _), 1363 [35] = PINGROUP(35, qup0_se4, phase_flag, _, _, _, _, _, _, _), 1364 [36] = PINGROUP(36, qup0_se2, qup0_se5, phase_flag, tgu_ch2, _, _, _, _, _), 1365 [37] = PINGROUP(37, qup0_se2, qup0_se5, phase_flag, tgu_ch3, _, _, _, _, _), 1366 [38] = PINGROUP(38, qup0_se5, qup0_se2, qdss_cti, phase_flag, tgu_ch4, _, _, _, _), 1367 [39] = PINGROUP(39, qup0_se5, qup0_se2, qdss_cti, phase_flag, tgu_ch5, _, _, _, _), 1368 [40] = PINGROUP(40, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync0, _, _, _, _, _), 1369 [41] = PINGROUP(41, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync1, _, _, _, _, _), 1370 [42] = PINGROUP(42, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync2, gcc_gp5, _, _, _, _), 1371 [43] = PINGROUP(43, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync3, _, _, _, _, _), 1372 [44] = PINGROUP(44, qup1_se2, qup1_se3, edp0_lcd, _, _, _, _, _, _), 1373 [45] = PINGROUP(45, qup1_se2, qup1_se3, edp1_lcd, _, _, _, _, _, _), 1374 [46] = PINGROUP(46, qup1_se3, qup1_se2, mdp1_vsync4, tgu_ch0, _, _, _, _, _), 1375 [47] = PINGROUP(47, qup1_se3, qup1_se2, mdp1_vsync5, tgu_ch1, _, _, _, _, _), 1376 [48] = PINGROUP(48, qup1_se4, qdss_cti, edp2_lcd, _, _, _, _, _, _), 1377 [49] = PINGROUP(49, qup1_se4, qdss_cti, edp3_lcd, _, _, _, _, _, _), 1378 [50] = PINGROUP(50, qup1_se4, cci_async, qdss_cti, mdp1_vsync8, _, _, _, _, _), 1379 [51] = PINGROUP(51, qup1_se4, qdss_cti, mdp1_vsync6, gcc_gp1, _, _, _, _, _), 1380 [52] = PINGROUP(52, qup1_se5, cci_timer4, cci_i2c, mdp1_vsync7, gcc_gp2, _, ddr_pxi1, _, _), 1381 [53] = PINGROUP(53, qup1_se5, cci_timer5, cci_i2c, gcc_gp3, _, ddr_pxi1, _, _, _), 1382 [54] = PINGROUP(54, qup1_se5, cci_timer6, cci_i2c, _, _, _, _, _, _), 1383 [55] = PINGROUP(55, qup1_se5, cci_timer7, cci_i2c, gcc_gp4, _, ddr_pxi2, _, _, _), 1384 [56] = PINGROUP(56, qup1_se6, qup1_se6, cci_timer8, cci_i2c, phase_flag, 1385 ddr_bist, _, _, _), 1386 [57] = PINGROUP(57, qup1_se6, qup1_se6, cci_timer9, cci_i2c, mdp0_vsync0, 1387 phase_flag, ddr_bist, _, _), 1388 [58] = PINGROUP(58, cci_i2c, mdp0_vsync1, ddr_bist, _, atest_usb2, atest_char, _, _, _), 1389 [59] = PINGROUP(59, cci_i2c, mdp0_vsync2, ddr_bist, _, atest_usb2, atest_char, _, _, _), 1390 [60] = PINGROUP(60, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1391 [61] = PINGROUP(61, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1392 [62] = PINGROUP(62, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1393 [63] = PINGROUP(63, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1394 [64] = PINGROUP(64, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1395 [65] = PINGROUP(65, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1396 [66] = PINGROUP(66, cci_i2c, cci_async, qdss_gpio, _, _, _, _, _, _), 1397 [67] = PINGROUP(67, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1398 [68] = PINGROUP(68, cci_timer0, cci_async, _, _, _, _, _, _, _), 1399 [69] = PINGROUP(69, cci_timer1, cci_async, _, _, _, _, _, _, _), 1400 [70] = PINGROUP(70, cci_timer2, cci_async, _, _, _, _, _, _, _), 1401 [71] = PINGROUP(71, cci_timer3, cci_async, _, _, _, _, _, _, _), 1402 [72] = PINGROUP(72, cam_mclk, _, _, _, _, _, _, _, _), 1403 [73] = PINGROUP(73, cam_mclk, _, _, _, _, _, _, _, _), 1404 [74] = PINGROUP(74, cam_mclk, _, _, _, _, _, _, _, _), 1405 [75] = PINGROUP(75, cam_mclk, _, _, _, _, _, _, _, _), 1406 [76] = PINGROUP(76, _, _, _, _, _, _, _, _, _), 1407 [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _), 1408 [78] = PINGROUP(78, _, _, _, _, _, _, _, _, _), 1409 [79] = PINGROUP(79, _, _, _, _, _, _, _, _, _), 1410 [80] = PINGROUP(80, qup2_se0, ibi_i3c, mdp0_vsync3, _, _, _, _, _, _), 1411 [81] = PINGROUP(81, qup2_se0, ibi_i3c, mdp0_vsync4, _, _, _, _, _, _), 1412 [82] = PINGROUP(82, qup2_se0, mdp_vsync, gcc_gp1, _, _, _, _, _, _), 1413 [83] = PINGROUP(83, qup2_se0, mdp_vsync, gcc_gp2, _, _, _, _, _, _), 1414 [84] = PINGROUP(84, qup2_se1, qup2_se5, ibi_i3c, mdp_vsync, gcc_gp3, _, _, _, _), 1415 [85] = PINGROUP(85, qup2_se1, qup2_se5, ibi_i3c, _, _, _, _, _, _), 1416 [86] = PINGROUP(86, qup2_se2, jitter_bist, atest_usb2, ddr_pxi2, _, _, _, _, _), 1417 [87] = PINGROUP(87, qup2_se2, pll_clk, atest_usb2, ddr_pxi3, _, _, _, _, _), 1418 [88] = PINGROUP(88, qup2_se2, _, atest_usb2, ddr_pxi3, _, _, _, _, _), 1419 [89] = PINGROUP(89, qup2_se2, _, atest_usb2, ddr_pxi4, atest_char, _, _, _, _), 1420 [90] = PINGROUP(90, qup2_se2, _, atest_usb2, ddr_pxi4, atest_char, _, _, _, _), 1421 [91] = PINGROUP(91, qup2_se3, mdp0_vsync5, _, atest_usb2, _, _, _, _, _), 1422 [92] = PINGROUP(92, qup2_se3, mdp0_vsync6, _, atest_usb2, _, _, _, _, _), 1423 [93] = PINGROUP(93, qup2_se3, mdp0_vsync7, _, atest_usb2, _, _, _, _, _), 1424 [94] = PINGROUP(94, qup2_se3, mdp0_vsync8, _, atest_usb2, _, _, _, _, _), 1425 [95] = PINGROUP(95, qup2_se4, qup2_se6, _, atest_usb2, _, _, _, _, _), 1426 [96] = PINGROUP(96, qup2_se4, qup2_se6, _, atest_usb2, _, _, _, _, _), 1427 [97] = PINGROUP(97, qup2_se6, qup2_se4, cri_trng0, _, atest_usb2, _, _, _, _), 1428 [98] = PINGROUP(98, qup2_se6, qup2_se4, phase_flag, cri_trng1, _, _, _, _, _), 1429 [99] = PINGROUP(99, qup2_se5, qup2_se1, phase_flag, cri_trng, _, _, _, _, _), 1430 [100] = PINGROUP(100, qup2_se5, qup2_se1, _, _, _, _, _, _, _), 1431 [101] = PINGROUP(101, edp0_hot, prng_rosc0, tsense_pwm4, _, _, _, _, _, _), 1432 [102] = PINGROUP(102, edp1_hot, prng_rosc1, tsense_pwm3, _, _, _, _, _, _), 1433 [103] = PINGROUP(103, edp3_hot, prng_rosc2, tsense_pwm2, _, _, _, _, _, _), 1434 [104] = PINGROUP(104, edp2_hot, prng_rosc3, tsense_pwm1, _, _, _, _, _, _), 1435 [105] = PINGROUP(105, mi2s_mclk0, _, qdss_gpio, atest_usb2, _, _, _, _, _), 1436 [106] = PINGROUP(106, mi2s1_sck, phase_flag, _, qdss_gpio, _, _, _, _, _), 1437 [107] = PINGROUP(107, mi2s1_ws, phase_flag, _, qdss_gpio, _, _, _, _, _), 1438 [108] = PINGROUP(108, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, _, _, _), 1439 [109] = PINGROUP(109, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, _, _, _), 1440 [110] = PINGROUP(110, mi2s2_sck, phase_flag, _, qdss_gpio, _, _, _, _, _), 1441 [111] = PINGROUP(111, mi2s2_ws, phase_flag, _, qdss_gpio, vsense_trigger, _, _, _, _), 1442 [112] = PINGROUP(112, mi2s2_data0, phase_flag, _, qdss_gpio, _, _, _, _, _), 1443 [113] = PINGROUP(113, mi2s2_data1, audio_ref, phase_flag, _, qdss_gpio, _, _, _, _), 1444 [114] = PINGROUP(114, hs0_mi2s, pll_bist, phase_flag, _, qdss_gpio, _, _, _, _), 1445 [115] = PINGROUP(115, hs0_mi2s, _, qdss_gpio, _, _, _, _, _, _), 1446 [116] = PINGROUP(116, hs0_mi2s, _, qdss_gpio, _, _, _, _, _, _), 1447 [117] = PINGROUP(117, hs0_mi2s, mi2s_mclk1, _, qdss_gpio, _, _, _, _, _), 1448 [118] = PINGROUP(118, hs1_mi2s, _, qdss_gpio, ddr_pxi5, _, _, _, _, _), 1449 [119] = PINGROUP(119, hs1_mi2s, _, qdss_gpio, ddr_pxi5, _, _, _, _, _), 1450 [120] = PINGROUP(120, hs1_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _), 1451 [121] = PINGROUP(121, hs1_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _), 1452 [122] = PINGROUP(122, hs2_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _), 1453 [123] = PINGROUP(123, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), 1454 [124] = PINGROUP(124, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), 1455 [125] = PINGROUP(125, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), 1456 [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _), 1457 [127] = PINGROUP(127, _, _, _, _, _, _, _, _, _), 1458 [128] = PINGROUP(128, _, _, _, _, _, _, _, _, _), 1459 [129] = PINGROUP(129, _, _, _, _, _, _, _, _, _), 1460 [130] = PINGROUP(130, _, _, _, _, _, _, _, _, _), 1461 [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _), 1462 [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _), 1463 [133] = PINGROUP(133, _, _, _, _, _, _, _, _, _), 1464 [134] = PINGROUP(134, _, _, _, _, _, _, _, _, _), 1465 [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _), 1466 [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _), 1467 [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _), 1468 [138] = PINGROUP(138, _, _, _, _, _, _, _, _, _), 1469 [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _), 1470 [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _), 1471 [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _), 1472 [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _), 1473 [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _), 1474 [144] = PINGROUP(144, dbg_out, _, _, _, _, _, _, _, _), 1475 [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _), 1476 [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), 1477 [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), 1478 [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _), 1479 [149] = UFS_RESET(ufs_reset, 0x1a2000), 1480 [150] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x199000, 15, 0), 1481 [151] = SDC_QDSD_PINGROUP(sdc1_clk, 0x199000, 13, 6), 1482 [152] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x199000, 11, 3), 1483 [153] = SDC_QDSD_PINGROUP(sdc1_data, 0x199000, 9, 0), 1484}; 1485 1486static const struct msm_gpio_wakeirq_map sa8775p_pdc_map[] = { 1487 { 0, 169 }, { 1, 174 }, { 2, 170 }, { 3, 175 }, { 4, 171 }, { 5, 173 }, 1488 { 6, 172 }, { 7, 182 }, { 10, 220 }, { 11, 213 }, { 12, 221 }, 1489 { 16, 230 }, { 19, 231 }, { 20, 232 }, { 23, 233 }, { 24, 234 }, 1490 { 26, 223 }, { 27, 235 }, { 28, 209 }, { 29, 176 }, { 30, 200 }, 1491 { 31, 201 }, { 32, 212 }, { 35, 177 }, { 36, 178 }, { 39, 184 }, 1492 { 40, 185 }, { 41, 227 }, { 42, 186 }, { 43, 228 }, { 45, 187 }, 1493 { 47, 188 }, { 48, 194 }, { 51, 195 }, { 52, 196 }, { 55, 197 }, 1494 { 56, 198 }, { 57, 236 }, { 58, 192 }, { 59, 193 }, { 72, 179 }, 1495 { 73, 180 }, { 74, 181 }, { 75, 202 }, { 76, 183 }, { 77, 189 }, 1496 { 78, 190 }, { 79, 191 }, { 80, 199 }, { 83, 204 }, { 84, 205 }, 1497 { 85, 229 }, { 86, 206 }, { 89, 207 }, { 91, 208 }, { 94, 214 }, 1498 { 95, 215 }, { 96, 237 }, { 97, 216 }, { 98, 238 }, { 99, 217 }, 1499 { 100, 239 }, { 105, 219 }, { 106, 210 }, { 107, 211 }, { 108, 222 }, 1500 { 109, 203 }, { 145, 225 }, { 146, 226 }, 1501}; 1502 1503static const struct msm_pinctrl_soc_data sa8775p_pinctrl = { 1504 .pins = sa8775p_pins, 1505 .npins = ARRAY_SIZE(sa8775p_pins), 1506 .functions = sa8775p_functions, 1507 .nfunctions = ARRAY_SIZE(sa8775p_functions), 1508 .groups = sa8775p_groups, 1509 .ngroups = ARRAY_SIZE(sa8775p_groups), 1510 .ngpios = 150, 1511 .wakeirq_map = sa8775p_pdc_map, 1512 .nwakeirq_map = ARRAY_SIZE(sa8775p_pdc_map), 1513}; 1514 1515static int sa8775p_pinctrl_probe(struct platform_device *pdev) 1516{ 1517 return msm_pinctrl_probe(pdev, &sa8775p_pinctrl); 1518} 1519 1520static const struct of_device_id sa8775p_pinctrl_of_match[] = { 1521 { .compatible = "qcom,sa8775p-tlmm", }, 1522 { }, 1523}; 1524MODULE_DEVICE_TABLE(of, sa8775p_pinctrl_of_match); 1525 1526static struct platform_driver sa8775p_pinctrl_driver = { 1527 .driver = { 1528 .name = "sa8775p-tlmm", 1529 .of_match_table = sa8775p_pinctrl_of_match, 1530 }, 1531 .probe = sa8775p_pinctrl_probe, 1532 .remove = msm_pinctrl_remove, 1533}; 1534 1535static int __init sa8775p_pinctrl_init(void) 1536{ 1537 return platform_driver_register(&sa8775p_pinctrl_driver); 1538} 1539arch_initcall(sa8775p_pinctrl_init); 1540 1541static void __exit sa8775p_pinctrl_exit(void) 1542{ 1543 platform_driver_unregister(&sa8775p_pinctrl_driver); 1544} 1545module_exit(sa8775p_pinctrl_exit); 1546 1547MODULE_DESCRIPTION("QTI SA8775P pinctrl driver"); 1548MODULE_LICENSE("GPL");