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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 Linaro Ltd
4 */
5
6#ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H
7#define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H
8
9#include <dt-bindings/interconnect/qcom,icc.h>
10
11#define RPM_BUS_MASTER_REQ 0x73616d62
12#define RPM_BUS_SLAVE_REQ 0x766c7362
13
14#define to_qcom_provider(_provider) \
15 container_of(_provider, struct qcom_icc_provider, provider)
16
17enum qcom_icc_type {
18 QCOM_ICC_NOC,
19 QCOM_ICC_BIMC,
20 QCOM_ICC_QNOC,
21};
22
23#define NUM_BUS_CLKS 2
24
25/**
26 * struct qcom_icc_provider - Qualcomm specific interconnect provider
27 * @provider: generic interconnect provider
28 * @num_bus_clks: the total number of bus_clks clk_bulk_data entries (0 or 2)
29 * @num_intf_clks: the total number of intf_clks clk_bulk_data entries
30 * @type: the ICC provider type
31 * @regmap: regmap for QoS registers read/write access
32 * @qos_offset: offset to QoS registers
33 * @bus_clk_rate: bus clock rate in Hz
34 * @bus_clks: the clk_bulk_data table of bus clocks
35 * @intf_clks: a clk_bulk_data array of interface clocks
36 * @is_on: whether the bus is powered on
37 */
38struct qcom_icc_provider {
39 struct icc_provider provider;
40 int num_bus_clks;
41 int num_intf_clks;
42 enum qcom_icc_type type;
43 struct regmap *regmap;
44 unsigned int qos_offset;
45 u64 bus_clk_rate[NUM_BUS_CLKS];
46 struct clk_bulk_data bus_clks[NUM_BUS_CLKS];
47 struct clk_bulk_data *intf_clks;
48 bool is_on;
49};
50
51/**
52 * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters
53 * @areq_prio: node requests priority
54 * @prio_level: priority level for bus communication
55 * @limit_commands: activate/deactivate limiter mode during runtime
56 * @ap_owned: indicates if the node is owned by the AP or by the RPM
57 * @qos_mode: default qos mode for this node
58 * @qos_port: qos port number for finding qos registers of this node
59 * @urg_fwd_en: enable urgent forwarding
60 */
61struct qcom_icc_qos {
62 u32 areq_prio;
63 u32 prio_level;
64 bool limit_commands;
65 bool ap_owned;
66 int qos_mode;
67 int qos_port;
68 bool urg_fwd_en;
69};
70
71/**
72 * struct qcom_icc_node - Qualcomm specific interconnect nodes
73 * @name: the node name used in debugfs
74 * @id: a unique node identifier
75 * @links: an array of nodes where we can go next while traversing
76 * @num_links: the total number of @links
77 * @channels: number of channels at this node (e.g. DDR channels)
78 * @buswidth: width of the interconnect between a node and the bus (bytes)
79 * @sum_avg: current sum aggregate value of all avg bw requests
80 * @max_peak: current max aggregate value of all peak bw requests
81 * @mas_rpm_id: RPM id for devices that are bus masters
82 * @slv_rpm_id: RPM id for devices that are bus slaves
83 * @qos: NoC QoS setting parameters
84 */
85struct qcom_icc_node {
86 unsigned char *name;
87 u16 id;
88 const u16 *links;
89 u16 num_links;
90 u16 channels;
91 u16 buswidth;
92 u64 sum_avg[QCOM_ICC_NUM_BUCKETS];
93 u64 max_peak[QCOM_ICC_NUM_BUCKETS];
94 int mas_rpm_id;
95 int slv_rpm_id;
96 struct qcom_icc_qos qos;
97};
98
99struct qcom_icc_desc {
100 struct qcom_icc_node * const *nodes;
101 size_t num_nodes;
102 const char * const *bus_clocks;
103 const char * const *intf_clocks;
104 size_t num_intf_clocks;
105 bool no_clk_scaling;
106 enum qcom_icc_type type;
107 const struct regmap_config *regmap_cfg;
108 unsigned int qos_offset;
109};
110
111/* Valid for all bus types */
112enum qos_mode {
113 NOC_QOS_MODE_INVALID = 0,
114 NOC_QOS_MODE_FIXED,
115 NOC_QOS_MODE_BYPASS,
116};
117
118int qnoc_probe(struct platform_device *pdev);
119int qnoc_remove(struct platform_device *pdev);
120
121#endif