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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * QMC management
4 *
5 * Copyright 2022 CS GROUP France
6 *
7 * Author: Herve Codina <herve.codina@bootlin.com>
8 */
9#ifndef __SOC_FSL_QMC_H__
10#define __SOC_FSL_QMC_H__
11
12#include <linux/types.h>
13
14struct device_node;
15struct device;
16struct qmc_chan;
17
18struct qmc_chan *qmc_chan_get_byphandle(struct device_node *np, const char *phandle_name);
19void qmc_chan_put(struct qmc_chan *chan);
20struct qmc_chan *devm_qmc_chan_get_byphandle(struct device *dev, struct device_node *np,
21 const char *phandle_name);
22
23enum qmc_mode {
24 QMC_TRANSPARENT,
25 QMC_HDLC,
26};
27
28struct qmc_chan_info {
29 enum qmc_mode mode;
30 unsigned long rx_fs_rate;
31 unsigned long rx_bit_rate;
32 u8 nb_rx_ts;
33 unsigned long tx_fs_rate;
34 unsigned long tx_bit_rate;
35 u8 nb_tx_ts;
36};
37
38int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info);
39
40struct qmc_chan_param {
41 enum qmc_mode mode;
42 union {
43 struct {
44 u16 max_rx_buf_size;
45 u16 max_rx_frame_size;
46 bool is_crc32;
47 } hdlc;
48 struct {
49 u16 max_rx_buf_size;
50 } transp;
51 };
52};
53
54int qmc_chan_set_param(struct qmc_chan *chan, const struct qmc_chan_param *param);
55
56int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
57 void (*complete)(void *context), void *context);
58
59int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
60 void (*complete)(void *context, size_t length),
61 void *context);
62
63#define QMC_CHAN_READ (1<<0)
64#define QMC_CHAN_WRITE (1<<1)
65#define QMC_CHAN_ALL (QMC_CHAN_READ | QMC_CHAN_WRITE)
66
67int qmc_chan_start(struct qmc_chan *chan, int direction);
68int qmc_chan_stop(struct qmc_chan *chan, int direction);
69int qmc_chan_reset(struct qmc_chan *chan, int direction);
70
71#endif /* __SOC_FSL_QMC_H__ */