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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (PCIe, IPQ8074)
8
9maintainers:
10 - Vinod Koul <vkoul@kernel.org>
11
12description:
13 QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16 Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see
17 qcom,sc8280xp-qmp-pcie-phy.yaml.
18
19properties:
20 compatible:
21 enum:
22 - qcom,ipq6018-qmp-pcie-phy
23 - qcom,ipq8074-qmp-gen3-pcie-phy
24 - qcom,ipq8074-qmp-pcie-phy
25 - qcom,msm8998-qmp-pcie-phy
26 - qcom,sc8180x-qmp-pcie-phy
27 - qcom,sdm845-qhp-pcie-phy
28 - qcom,sdm845-qmp-pcie-phy
29 - qcom,sdx55-qmp-pcie-phy
30 - qcom,sm8250-qmp-gen3x1-pcie-phy
31 - qcom,sm8250-qmp-gen3x2-pcie-phy
32 - qcom,sm8250-qmp-modem-pcie-phy
33 - qcom,sm8450-qmp-gen3x1-pcie-phy
34 - qcom,sm8450-qmp-gen4x2-pcie-phy
35
36 reg:
37 items:
38 - description: serdes
39
40 "#address-cells":
41 enum: [ 1, 2 ]
42
43 "#size-cells":
44 enum: [ 1, 2 ]
45
46 ranges: true
47
48 clocks:
49 minItems: 2
50 maxItems: 4
51
52 clock-names:
53 minItems: 2
54 maxItems: 4
55
56 resets:
57 minItems: 1
58 maxItems: 2
59
60 reset-names:
61 minItems: 1
62 maxItems: 2
63
64 vdda-phy-supply: true
65
66 vdda-pll-supply: true
67
68 vddp-ref-clk-supply: true
69
70patternProperties:
71 "^phy@[0-9a-f]+$":
72 type: object
73 description: single PHY-provider child node
74 properties:
75 reg:
76 minItems: 3
77 maxItems: 6
78
79 clocks:
80 items:
81 - description: PIPE clock
82
83 clock-names:
84 deprecated: true
85 items:
86 - const: pipe0
87
88 "#clock-cells":
89 const: 0
90
91 clock-output-names:
92 maxItems: 1
93
94 "#phy-cells":
95 const: 0
96
97 required:
98 - reg
99 - clocks
100 - "#clock-cells"
101 - clock-output-names
102 - "#phy-cells"
103
104 additionalProperties: false
105
106required:
107 - compatible
108 - reg
109 - "#address-cells"
110 - "#size-cells"
111 - ranges
112 - clocks
113 - clock-names
114 - resets
115 - reset-names
116
117additionalProperties: false
118
119allOf:
120 - if:
121 properties:
122 compatible:
123 contains:
124 enum:
125 - qcom,msm8998-qmp-pcie-phy
126 then:
127 properties:
128 clocks:
129 maxItems: 3
130 clock-names:
131 items:
132 - const: aux
133 - const: cfg_ahb
134 - const: ref
135 resets:
136 maxItems: 2
137 reset-names:
138 items:
139 - const: phy
140 - const: common
141 required:
142 - vdda-phy-supply
143 - vdda-pll-supply
144
145 - if:
146 properties:
147 compatible:
148 contains:
149 enum:
150 - qcom,ipq6018-qmp-pcie-phy
151 - qcom,ipq8074-qmp-gen3-pcie-phy
152 - qcom,ipq8074-qmp-pcie-phy
153 then:
154 properties:
155 clocks:
156 maxItems: 2
157 clock-names:
158 items:
159 - const: aux
160 - const: cfg_ahb
161 resets:
162 maxItems: 2
163 reset-names:
164 items:
165 - const: phy
166 - const: common
167
168 - if:
169 properties:
170 compatible:
171 contains:
172 enum:
173 - qcom,sc8180x-qmp-pcie-phy
174 - qcom,sdm845-qhp-pcie-phy
175 - qcom,sdm845-qmp-pcie-phy
176 - qcom,sdx55-qmp-pcie-phy
177 - qcom,sm8250-qmp-gen3x1-pcie-phy
178 - qcom,sm8250-qmp-gen3x2-pcie-phy
179 - qcom,sm8250-qmp-modem-pcie-phy
180 - qcom,sm8450-qmp-gen3x1-pcie-phy
181 - qcom,sm8450-qmp-gen4x2-pcie-phy
182 then:
183 properties:
184 clocks:
185 maxItems: 4
186 clock-names:
187 items:
188 - const: aux
189 - const: cfg_ahb
190 - const: ref
191 - const: refgen
192 resets:
193 maxItems: 1
194 reset-names:
195 items:
196 - const: phy
197 required:
198 - vdda-phy-supply
199 - vdda-pll-supply
200
201 - if:
202 properties:
203 compatible:
204 contains:
205 enum:
206 - qcom,sc8180x-qmp-pcie-phy
207 - qcom,sm8250-qmp-gen3x2-pcie-phy
208 - qcom,sm8250-qmp-modem-pcie-phy
209 - qcom,sm8450-qmp-gen4x2-pcie-phy
210 then:
211 patternProperties:
212 "^phy@[0-9a-f]+$":
213 properties:
214 reg:
215 items:
216 - description: TX lane 1
217 - description: RX lane 1
218 - description: PCS
219 - description: TX lane 2
220 - description: RX lane 2
221 - description: PCS_MISC
222
223 - if:
224 properties:
225 compatible:
226 contains:
227 enum:
228 - qcom,sdm845-qmp-pcie-phy
229 - qcom,sdx55-qmp-pcie-phy
230 - qcom,sm8250-qmp-gen3x1-pcie-phy
231 - qcom,sm8450-qmp-gen3x1-pcie-phy
232 then:
233 patternProperties:
234 "^phy@[0-9a-f]+$":
235 properties:
236 reg:
237 items:
238 - description: TX
239 - description: RX
240 - description: PCS
241 - description: PCS_MISC
242
243 - if:
244 properties:
245 compatible:
246 contains:
247 enum:
248 - qcom,ipq6018-qmp-pcie-phy
249 - qcom,ipq8074-qmp-pcie-phy
250 - qcom,msm8998-qmp-pcie-phy
251 - qcom,sdm845-qhp-pcie-phy
252 then:
253 patternProperties:
254 "^phy@[0-9a-f]+$":
255 properties:
256 reg:
257 items:
258 - description: TX
259 - description: RX
260 - description: PCS
261
262examples:
263 - |
264 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
265 phy-wrapper@1c0e000 {
266 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
267 reg = <0x01c0e000 0x1c0>;
268 #address-cells = <1>;
269 #size-cells = <1>;
270 ranges = <0x0 0x01c0e000 0x1000>;
271
272 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
273 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
274 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
275 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
276 clock-names = "aux", "cfg_ahb", "ref", "refgen";
277
278 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
279 reset-names = "phy";
280
281 vdda-phy-supply = <&vreg_l10c_0p88>;
282 vdda-pll-supply = <&vreg_l6b_1p2>;
283
284 phy@200 {
285 reg = <0x200 0x170>,
286 <0x400 0x200>,
287 <0xa00 0x1f0>,
288 <0x600 0x170>,
289 <0x800 0x200>,
290 <0xe00 0xf4>;
291
292 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
293
294 #clock-cells = <0>;
295 clock-output-names = "pcie_1_pipe_clk";
296
297 #phy-cells = <0>;
298 };
299 };