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Linux kernel mirror (for testing)
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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_GFX_H__
25#define __AMDGPU_GFX_H__
26
27/*
28 * GFX stuff
29 */
30#include "clearstate_defs.h"
31#include "amdgpu_ring.h"
32#include "amdgpu_rlc.h"
33#include "amdgpu_imu.h"
34#include "soc15.h"
35#include "amdgpu_ras.h"
36#include "amdgpu_ring_mux.h"
37
38/* GFX current status */
39#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
40#define AMDGPU_GFX_SAFE_MODE 0x00000001L
41#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
42#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
43#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
44
45#define AMDGPU_MAX_GC_INSTANCES 8
46
47#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
48#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
49
50enum amdgpu_gfx_pipe_priority {
51 AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1,
52 AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2
53};
54
55#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
56#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
57
58enum amdgpu_gfx_partition {
59 AMDGPU_SPX_PARTITION_MODE = 0,
60 AMDGPU_DPX_PARTITION_MODE = 1,
61 AMDGPU_TPX_PARTITION_MODE = 2,
62 AMDGPU_QPX_PARTITION_MODE = 3,
63 AMDGPU_CPX_PARTITION_MODE = 4,
64 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE = -1,
65 /* Automatically choose the right mode */
66 AMDGPU_AUTO_COMPUTE_PARTITION_MODE = -2,
67};
68
69#define NUM_XCC(x) hweight16(x)
70
71enum amdgpu_pkg_type {
72 AMDGPU_PKG_TYPE_APU = 2,
73 AMDGPU_PKG_TYPE_UNKNOWN,
74};
75
76enum amdgpu_gfx_ras_mem_id_type {
77 AMDGPU_GFX_CP_MEM = 0,
78 AMDGPU_GFX_GCEA_MEM,
79 AMDGPU_GFX_GC_CANE_MEM,
80 AMDGPU_GFX_GCUTCL2_MEM,
81 AMDGPU_GFX_GDS_MEM,
82 AMDGPU_GFX_LDS_MEM,
83 AMDGPU_GFX_RLC_MEM,
84 AMDGPU_GFX_SP_MEM,
85 AMDGPU_GFX_SPI_MEM,
86 AMDGPU_GFX_SQC_MEM,
87 AMDGPU_GFX_SQ_MEM,
88 AMDGPU_GFX_TA_MEM,
89 AMDGPU_GFX_TCC_MEM,
90 AMDGPU_GFX_TCA_MEM,
91 AMDGPU_GFX_TCI_MEM,
92 AMDGPU_GFX_TCP_MEM,
93 AMDGPU_GFX_TD_MEM,
94 AMDGPU_GFX_TCX_MEM,
95 AMDGPU_GFX_ATC_L2_MEM,
96 AMDGPU_GFX_UTCL2_MEM,
97 AMDGPU_GFX_VML2_MEM,
98 AMDGPU_GFX_VML2_WALKER_MEM,
99 AMDGPU_GFX_MEM_TYPE_NUM
100};
101
102struct amdgpu_mec {
103 struct amdgpu_bo *hpd_eop_obj;
104 u64 hpd_eop_gpu_addr;
105 struct amdgpu_bo *mec_fw_obj;
106 u64 mec_fw_gpu_addr;
107 struct amdgpu_bo *mec_fw_data_obj;
108 u64 mec_fw_data_gpu_addr;
109
110 u32 num_mec;
111 u32 num_pipe_per_mec;
112 u32 num_queue_per_pipe;
113 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES];
114};
115
116struct amdgpu_mec_bitmap {
117 /* These are the resources for which amdgpu takes ownership */
118 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
119};
120
121enum amdgpu_unmap_queues_action {
122 PREEMPT_QUEUES = 0,
123 RESET_QUEUES,
124 DISABLE_PROCESS_QUEUES,
125 PREEMPT_QUEUES_NO_UNMAP,
126};
127
128struct kiq_pm4_funcs {
129 /* Support ASIC-specific kiq pm4 packets*/
130 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring,
131 uint64_t queue_mask);
132 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring,
133 struct amdgpu_ring *ring);
134 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring,
135 struct amdgpu_ring *ring,
136 enum amdgpu_unmap_queues_action action,
137 u64 gpu_addr, u64 seq);
138 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring,
139 struct amdgpu_ring *ring,
140 u64 addr,
141 u64 seq);
142 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,
143 uint16_t pasid, uint32_t flush_type,
144 bool all_hub);
145 /* Packet sizes */
146 int set_resources_size;
147 int map_queues_size;
148 int unmap_queues_size;
149 int query_status_size;
150 int invalidate_tlbs_size;
151};
152
153struct amdgpu_kiq {
154 u64 eop_gpu_addr;
155 struct amdgpu_bo *eop_obj;
156 spinlock_t ring_lock;
157 struct amdgpu_ring ring;
158 struct amdgpu_irq_src irq;
159 const struct kiq_pm4_funcs *pmf;
160 void *mqd_backup;
161};
162
163/*
164 * GFX configurations
165 */
166#define AMDGPU_GFX_MAX_SE 4
167#define AMDGPU_GFX_MAX_SH_PER_SE 2
168
169struct amdgpu_rb_config {
170 uint32_t rb_backend_disable;
171 uint32_t user_rb_backend_disable;
172 uint32_t raster_config;
173 uint32_t raster_config_1;
174};
175
176struct gb_addr_config {
177 uint16_t pipe_interleave_size;
178 uint8_t num_pipes;
179 uint8_t max_compress_frags;
180 uint8_t num_banks;
181 uint8_t num_se;
182 uint8_t num_rb_per_se;
183 uint8_t num_pkrs;
184};
185
186struct amdgpu_gfx_config {
187 unsigned max_shader_engines;
188 unsigned max_tile_pipes;
189 unsigned max_cu_per_sh;
190 unsigned max_sh_per_se;
191 unsigned max_backends_per_se;
192 unsigned max_texture_channel_caches;
193 unsigned max_gprs;
194 unsigned max_gs_threads;
195 unsigned max_hw_contexts;
196 unsigned sc_prim_fifo_size_frontend;
197 unsigned sc_prim_fifo_size_backend;
198 unsigned sc_hiz_tile_fifo_size;
199 unsigned sc_earlyz_tile_fifo_size;
200
201 unsigned num_tile_pipes;
202 unsigned backend_enable_mask;
203 unsigned mem_max_burst_length_bytes;
204 unsigned mem_row_size_in_kb;
205 unsigned shader_engine_tile_size;
206 unsigned num_gpus;
207 unsigned multi_gpu_tile_size;
208 unsigned mc_arb_ramcfg;
209 unsigned num_banks;
210 unsigned num_ranks;
211 unsigned gb_addr_config;
212 unsigned num_rbs;
213 unsigned gs_vgt_table_depth;
214 unsigned gs_prim_buffer_depth;
215
216 uint32_t tile_mode_array[32];
217 uint32_t macrotile_mode_array[16];
218
219 struct gb_addr_config gb_addr_config_fields;
220 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
221
222 /* gfx configure feature */
223 uint32_t double_offchip_lds_buf;
224 /* cached value of DB_DEBUG2 */
225 uint32_t db_debug2;
226 /* gfx10 specific config */
227 uint32_t num_sc_per_sh;
228 uint32_t num_packer_per_sc;
229 uint32_t pa_sc_tile_steering_override;
230 /* Whether texture coordinate truncation is conformant. */
231 bool ta_cntl2_truncate_coord_mode;
232 uint64_t tcc_disabled_mask;
233 uint32_t gc_num_tcp_per_sa;
234 uint32_t gc_num_sdp_interface;
235 uint32_t gc_num_tcps;
236 uint32_t gc_num_tcp_per_wpg;
237 uint32_t gc_tcp_l1_size;
238 uint32_t gc_num_sqc_per_wgp;
239 uint32_t gc_l1_instruction_cache_size_per_sqc;
240 uint32_t gc_l1_data_cache_size_per_sqc;
241 uint32_t gc_gl1c_per_sa;
242 uint32_t gc_gl1c_size_per_instance;
243 uint32_t gc_gl2c_per_gpu;
244};
245
246struct amdgpu_cu_info {
247 uint32_t simd_per_cu;
248 uint32_t max_waves_per_simd;
249 uint32_t wave_front_size;
250 uint32_t max_scratch_slots_per_cu;
251 uint32_t lds_size;
252
253 /* total active CU number */
254 uint32_t number;
255 uint32_t ao_cu_mask;
256 uint32_t ao_cu_bitmap[4][4];
257 uint32_t bitmap[4][4];
258};
259
260struct amdgpu_gfx_ras {
261 struct amdgpu_ras_block_object ras_block;
262 void (*enable_watchdog_timer)(struct amdgpu_device *adev);
263 bool (*query_utcl2_poison_status)(struct amdgpu_device *adev);
264 int (*rlc_gc_fed_irq)(struct amdgpu_device *adev,
265 struct amdgpu_irq_src *source,
266 struct amdgpu_iv_entry *entry);
267 int (*poison_consumption_handler)(struct amdgpu_device *adev,
268 struct amdgpu_iv_entry *entry);
269};
270
271struct amdgpu_gfx_shadow_info {
272 u32 shadow_size;
273 u32 shadow_alignment;
274 u32 csa_size;
275 u32 csa_alignment;
276};
277
278struct amdgpu_gfx_funcs {
279 /* get the gpu clock counter */
280 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
281 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
282 u32 sh_num, u32 instance, int xcc_id);
283 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
284 uint32_t wave, uint32_t *dst, int *no_fields);
285 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
286 uint32_t wave, uint32_t thread, uint32_t start,
287 uint32_t size, uint32_t *dst);
288 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
289 uint32_t wave, uint32_t start, uint32_t size,
290 uint32_t *dst);
291 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
292 u32 queue, u32 vmid, u32 xcc_id);
293 void (*init_spm_golden)(struct amdgpu_device *adev);
294 void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
295 int (*get_gfx_shadow_info)(struct amdgpu_device *adev,
296 struct amdgpu_gfx_shadow_info *shadow_info);
297 enum amdgpu_gfx_partition
298 (*query_partition_mode)(struct amdgpu_device *adev);
299 int (*switch_partition_mode)(struct amdgpu_device *adev,
300 int num_xccs_per_xcp);
301 int (*ih_node_to_logical_xcc)(struct amdgpu_device *adev, int ih_node);
302};
303
304struct sq_work {
305 struct work_struct work;
306 unsigned ih_data;
307};
308
309struct amdgpu_pfp {
310 struct amdgpu_bo *pfp_fw_obj;
311 uint64_t pfp_fw_gpu_addr;
312 uint32_t *pfp_fw_ptr;
313
314 struct amdgpu_bo *pfp_fw_data_obj;
315 uint64_t pfp_fw_data_gpu_addr;
316 uint32_t *pfp_fw_data_ptr;
317};
318
319struct amdgpu_ce {
320 struct amdgpu_bo *ce_fw_obj;
321 uint64_t ce_fw_gpu_addr;
322 uint32_t *ce_fw_ptr;
323};
324
325struct amdgpu_me {
326 struct amdgpu_bo *me_fw_obj;
327 uint64_t me_fw_gpu_addr;
328 uint32_t *me_fw_ptr;
329
330 struct amdgpu_bo *me_fw_data_obj;
331 uint64_t me_fw_data_gpu_addr;
332 uint32_t *me_fw_data_ptr;
333
334 uint32_t num_me;
335 uint32_t num_pipe_per_me;
336 uint32_t num_queue_per_pipe;
337 void *mqd_backup[AMDGPU_MAX_GFX_RINGS];
338
339 /* These are the resources for which amdgpu takes ownership */
340 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
341};
342
343struct amdgpu_gfx {
344 struct mutex gpu_clock_mutex;
345 struct amdgpu_gfx_config config;
346 struct amdgpu_rlc rlc;
347 struct amdgpu_pfp pfp;
348 struct amdgpu_ce ce;
349 struct amdgpu_me me;
350 struct amdgpu_mec mec;
351 struct amdgpu_mec_bitmap mec_bitmap[AMDGPU_MAX_GC_INSTANCES];
352 struct amdgpu_kiq kiq[AMDGPU_MAX_GC_INSTANCES];
353 struct amdgpu_imu imu;
354 bool rs64_enable; /* firmware format */
355 const struct firmware *me_fw; /* ME firmware */
356 uint32_t me_fw_version;
357 const struct firmware *pfp_fw; /* PFP firmware */
358 uint32_t pfp_fw_version;
359 const struct firmware *ce_fw; /* CE firmware */
360 uint32_t ce_fw_version;
361 const struct firmware *rlc_fw; /* RLC firmware */
362 uint32_t rlc_fw_version;
363 const struct firmware *mec_fw; /* MEC firmware */
364 uint32_t mec_fw_version;
365 const struct firmware *mec2_fw; /* MEC2 firmware */
366 uint32_t mec2_fw_version;
367 const struct firmware *imu_fw; /* IMU firmware */
368 uint32_t imu_fw_version;
369 uint32_t me_feature_version;
370 uint32_t ce_feature_version;
371 uint32_t pfp_feature_version;
372 uint32_t rlc_feature_version;
373 uint32_t rlc_srlc_fw_version;
374 uint32_t rlc_srlc_feature_version;
375 uint32_t rlc_srlg_fw_version;
376 uint32_t rlc_srlg_feature_version;
377 uint32_t rlc_srls_fw_version;
378 uint32_t rlc_srls_feature_version;
379 uint32_t rlcp_ucode_version;
380 uint32_t rlcp_ucode_feature_version;
381 uint32_t rlcv_ucode_version;
382 uint32_t rlcv_ucode_feature_version;
383 uint32_t mec_feature_version;
384 uint32_t mec2_feature_version;
385 bool mec_fw_write_wait;
386 bool me_fw_write_wait;
387 bool cp_fw_write_wait;
388 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
389 unsigned num_gfx_rings;
390 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES];
391 unsigned num_compute_rings;
392 struct amdgpu_irq_src eop_irq;
393 struct amdgpu_irq_src priv_reg_irq;
394 struct amdgpu_irq_src priv_inst_irq;
395 struct amdgpu_irq_src cp_ecc_error_irq;
396 struct amdgpu_irq_src sq_irq;
397 struct amdgpu_irq_src rlc_gc_fed_irq;
398 struct sq_work sq_work;
399
400 /* gfx status */
401 uint32_t gfx_current_status;
402 /* ce ram size*/
403 unsigned ce_ram_size;
404 struct amdgpu_cu_info cu_info;
405 const struct amdgpu_gfx_funcs *funcs;
406
407 /* reset mask */
408 uint32_t grbm_soft_reset;
409 uint32_t srbm_soft_reset;
410
411 /* gfx off */
412 bool gfx_off_state; /* true: enabled, false: disabled */
413 struct mutex gfx_off_mutex; /* mutex to change gfxoff state */
414 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
415 struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */
416 uint32_t gfx_off_residency; /* last logged residency */
417 uint64_t gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */
418
419 /* pipe reservation */
420 struct mutex pipe_reserve_mutex;
421 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
422
423 /*ras */
424 struct ras_common_if *ras_if;
425 struct amdgpu_gfx_ras *ras;
426
427 bool is_poweron;
428
429 struct amdgpu_ring sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS];
430 struct amdgpu_ring_mux muxer;
431
432 bool cp_gfx_shadow; /* for gfx11 */
433
434 uint16_t xcc_mask;
435 uint32_t num_xcc_per_xcp;
436 struct mutex partition_mutex;
437 bool mcbp; /* mid command buffer preemption */
438};
439
440struct amdgpu_gfx_ras_reg_entry {
441 struct amdgpu_ras_err_status_reg_entry reg_entry;
442 enum amdgpu_gfx_ras_mem_id_type mem_id_type;
443 uint32_t se_num;
444};
445
446struct amdgpu_gfx_ras_mem_id_entry {
447 const struct amdgpu_ras_memory_id_entry *mem_id_ent;
448 uint32_t size;
449};
450
451#define AMDGPU_GFX_MEMID_ENT(x) {(x), ARRAY_SIZE(x)},
452
453#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
454#define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id)))
455#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id)))
456#define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
457#define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si)))
458
459/**
460 * amdgpu_gfx_create_bitmask - create a bitmask
461 *
462 * @bit_width: length of the mask
463 *
464 * create a variable length bit mask.
465 * Returns the bitmask.
466 */
467static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
468{
469 return (u32)((1ULL << bit_width) - 1);
470}
471
472void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
473 unsigned max_sh);
474
475int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
476 struct amdgpu_ring *ring,
477 struct amdgpu_irq_src *irq, int xcc_id);
478
479void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
480
481void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id);
482int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
483 unsigned hpd_size, int xcc_id);
484
485int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
486 unsigned mqd_size, int xcc_id);
487void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id);
488int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id);
489int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id);
490int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id);
491int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id);
492
493void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
494void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
495
496int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
497 int pipe, int queue);
498void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
499 int *mec, int *pipe, int *queue);
500bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id,
501 int mec, int pipe, int queue);
502bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
503 struct amdgpu_ring *ring);
504bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
505 struct amdgpu_ring *ring);
506int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
507 int pipe, int queue);
508void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
509 int *me, int *pipe, int *queue);
510bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
511 int pipe, int queue);
512void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
513int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
514int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
515void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
516int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value);
517int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency);
518int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value);
519int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
520 void *err_data,
521 struct amdgpu_iv_entry *entry);
522int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
523 struct amdgpu_irq_src *source,
524 struct amdgpu_iv_entry *entry);
525uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
526void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
527int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
528void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);
529
530int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev);
531int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
532 struct amdgpu_iv_entry *entry);
533
534bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id);
535int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev);
536void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev);
537void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev,
538 void *ras_error_status,
539 void (*func)(struct amdgpu_device *adev, void *ras_error_status,
540 int xcc_id));
541
542static inline const char *amdgpu_gfx_compute_mode_desc(int mode)
543{
544 switch (mode) {
545 case AMDGPU_SPX_PARTITION_MODE:
546 return "SPX";
547 case AMDGPU_DPX_PARTITION_MODE:
548 return "DPX";
549 case AMDGPU_TPX_PARTITION_MODE:
550 return "TPX";
551 case AMDGPU_QPX_PARTITION_MODE:
552 return "QPX";
553 case AMDGPU_CPX_PARTITION_MODE:
554 return "CPX";
555 default:
556 return "UNKNOWN";
557 }
558
559 return "UNKNOWN";
560}
561
562#endif