tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2020-2023 Intel Corporation
4 */
5
6#ifndef __IVPU_DRV_H__
7#define __IVPU_DRV_H__
8
9#include <drm/drm_device.h>
10#include <drm/drm_drv.h>
11#include <drm/drm_managed.h>
12#include <drm/drm_mm.h>
13#include <drm/drm_print.h>
14
15#include <linux/pci.h>
16#include <linux/xarray.h>
17#include <uapi/drm/ivpu_accel.h>
18
19#include "ivpu_mmu_context.h"
20
21#define DRIVER_NAME "intel_vpu"
22#define DRIVER_DESC "Driver for Intel Versatile Processing Unit (VPU)"
23#define DRIVER_DATE "20230117"
24
25#define PCI_DEVICE_ID_MTL 0x7d1d
26
27#define IVPU_GLOBAL_CONTEXT_MMU_SSID 0
28/* SSID 1 is used by the VPU to represent invalid context */
29#define IVPU_USER_CONTEXT_MIN_SSID 2
30#define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63)
31
32#define IVPU_NUM_ENGINES 2
33
34#define IVPU_PLATFORM_SILICON 0
35#define IVPU_PLATFORM_SIMICS 2
36#define IVPU_PLATFORM_FPGA 3
37#define IVPU_PLATFORM_INVALID 8
38
39#define IVPU_DBG_REG BIT(0)
40#define IVPU_DBG_IRQ BIT(1)
41#define IVPU_DBG_MMU BIT(2)
42#define IVPU_DBG_FILE BIT(3)
43#define IVPU_DBG_MISC BIT(4)
44#define IVPU_DBG_FW_BOOT BIT(5)
45#define IVPU_DBG_PM BIT(6)
46#define IVPU_DBG_IPC BIT(7)
47#define IVPU_DBG_BO BIT(8)
48#define IVPU_DBG_JOB BIT(9)
49#define IVPU_DBG_JSM BIT(10)
50#define IVPU_DBG_KREF BIT(11)
51#define IVPU_DBG_RPM BIT(12)
52
53#define ivpu_err(vdev, fmt, ...) \
54 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
55
56#define ivpu_err_ratelimited(vdev, fmt, ...) \
57 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
58
59#define ivpu_warn(vdev, fmt, ...) \
60 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
61
62#define ivpu_warn_ratelimited(vdev, fmt, ...) \
63 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
64
65#define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
66
67#define ivpu_dbg(vdev, type, fmt, args...) do { \
68 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \
69 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \
70} while (0)
71
72#define IVPU_WA(wa_name) (vdev->wa.wa_name)
73
74struct ivpu_wa_table {
75 bool punit_disabled;
76 bool clear_runtime_mem;
77 bool d3hot_after_power_off;
78 bool interrupt_clear_with_0;
79};
80
81struct ivpu_hw_info;
82struct ivpu_mmu_info;
83struct ivpu_fw_info;
84struct ivpu_ipc_info;
85struct ivpu_pm_info;
86
87struct ivpu_device {
88 struct drm_device drm;
89 void __iomem *regb;
90 void __iomem *regv;
91 u32 platform;
92 u32 irq;
93
94 struct ivpu_wa_table wa;
95 struct ivpu_hw_info *hw;
96 struct ivpu_mmu_info *mmu;
97 struct ivpu_fw_info *fw;
98 struct ivpu_ipc_info *ipc;
99 struct ivpu_pm_info *pm;
100
101 struct ivpu_mmu_context gctx;
102 struct xarray context_xa;
103 struct xa_limit context_xa_limit;
104
105 struct xarray submitted_jobs_xa;
106 struct task_struct *job_done_thread;
107
108 atomic64_t unique_id_counter;
109
110 struct {
111 int boot;
112 int jsm;
113 int tdr;
114 int reschedule_suspend;
115 } timeout;
116};
117
118/*
119 * file_priv has its own refcount (ref) that allows user space to close the fd
120 * without blocking even if VPU is still processing some jobs.
121 */
122struct ivpu_file_priv {
123 struct kref ref;
124 struct ivpu_device *vdev;
125 struct mutex lock; /* Protects cmdq */
126 struct ivpu_cmdq *cmdq[IVPU_NUM_ENGINES];
127 struct ivpu_mmu_context ctx;
128 u32 priority;
129 bool has_mmu_faults;
130};
131
132extern int ivpu_dbg_mask;
133extern u8 ivpu_pll_min_ratio;
134extern u8 ivpu_pll_max_ratio;
135
136#define IVPU_TEST_MODE_DISABLED 0
137#define IVPU_TEST_MODE_FW_TEST 1
138#define IVPU_TEST_MODE_NULL_HW 2
139extern int ivpu_test_mode;
140
141struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
142struct ivpu_file_priv *ivpu_file_priv_get_by_ctx_id(struct ivpu_device *vdev, unsigned long id);
143void ivpu_file_priv_put(struct ivpu_file_priv **link);
144
145int ivpu_boot(struct ivpu_device *vdev);
146int ivpu_shutdown(struct ivpu_device *vdev);
147
148static inline bool ivpu_is_mtl(struct ivpu_device *vdev)
149{
150 return to_pci_dev(vdev->drm.dev)->device == PCI_DEVICE_ID_MTL;
151}
152
153static inline u8 ivpu_revision(struct ivpu_device *vdev)
154{
155 return to_pci_dev(vdev->drm.dev)->revision;
156}
157
158static inline u16 ivpu_device_id(struct ivpu_device *vdev)
159{
160 return to_pci_dev(vdev->drm.dev)->device;
161}
162
163static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
164{
165 return container_of(dev, struct ivpu_device, drm);
166}
167
168static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
169{
170 struct xa_limit ctx_limit = vdev->context_xa_limit;
171
172 return (ctx_limit.max - ctx_limit.min + 1);
173}
174
175static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
176{
177 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
178 return vdev->platform;
179}
180
181static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
182{
183 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
184}
185
186static inline bool ivpu_is_simics(struct ivpu_device *vdev)
187{
188 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
189}
190
191static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
192{
193 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;
194}
195
196#endif /* __IVPU_DRV_H__ */