tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare XPCS helpers
5 *
6 * Author: Jose Abreu <Jose.Abreu@synopsys.com>
7 */
8
9#include <linux/delay.h>
10#include <linux/pcs/pcs-xpcs.h>
11#include <linux/mdio.h>
12#include <linux/phylink.h>
13#include <linux/workqueue.h>
14#include "pcs-xpcs.h"
15
16#define phylink_pcs_to_xpcs(pl_pcs) \
17 container_of((pl_pcs), struct dw_xpcs, pcs)
18
19static const int xpcs_usxgmii_features[] = {
20 ETHTOOL_LINK_MODE_Pause_BIT,
21 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
22 ETHTOOL_LINK_MODE_Autoneg_BIT,
23 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
24 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
25 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
26 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
27 __ETHTOOL_LINK_MODE_MASK_NBITS,
28};
29
30static const int xpcs_10gkr_features[] = {
31 ETHTOOL_LINK_MODE_Pause_BIT,
32 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
33 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
34 __ETHTOOL_LINK_MODE_MASK_NBITS,
35};
36
37static const int xpcs_xlgmii_features[] = {
38 ETHTOOL_LINK_MODE_Pause_BIT,
39 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
40 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
41 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
42 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
43 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
44 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
45 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
46 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
47 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
48 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
49 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
50 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
51 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
52 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
53 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
54 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
55 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
56 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
57 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
58 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
59 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
60 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
61 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
62 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
63 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
64 __ETHTOOL_LINK_MODE_MASK_NBITS,
65};
66
67static const int xpcs_10gbaser_features[] = {
68 ETHTOOL_LINK_MODE_Pause_BIT,
69 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
70 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
71 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
72 ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
73 ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
74 __ETHTOOL_LINK_MODE_MASK_NBITS,
75};
76
77static const int xpcs_sgmii_features[] = {
78 ETHTOOL_LINK_MODE_Pause_BIT,
79 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
80 ETHTOOL_LINK_MODE_Autoneg_BIT,
81 ETHTOOL_LINK_MODE_10baseT_Half_BIT,
82 ETHTOOL_LINK_MODE_10baseT_Full_BIT,
83 ETHTOOL_LINK_MODE_100baseT_Half_BIT,
84 ETHTOOL_LINK_MODE_100baseT_Full_BIT,
85 ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
86 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
87 __ETHTOOL_LINK_MODE_MASK_NBITS,
88};
89
90static const int xpcs_1000basex_features[] = {
91 ETHTOOL_LINK_MODE_Pause_BIT,
92 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
93 ETHTOOL_LINK_MODE_Autoneg_BIT,
94 ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
95 __ETHTOOL_LINK_MODE_MASK_NBITS,
96};
97
98static const int xpcs_2500basex_features[] = {
99 ETHTOOL_LINK_MODE_Pause_BIT,
100 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
101 ETHTOOL_LINK_MODE_Autoneg_BIT,
102 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
103 ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
104 __ETHTOOL_LINK_MODE_MASK_NBITS,
105};
106
107static const phy_interface_t xpcs_usxgmii_interfaces[] = {
108 PHY_INTERFACE_MODE_USXGMII,
109};
110
111static const phy_interface_t xpcs_10gkr_interfaces[] = {
112 PHY_INTERFACE_MODE_10GKR,
113};
114
115static const phy_interface_t xpcs_xlgmii_interfaces[] = {
116 PHY_INTERFACE_MODE_XLGMII,
117};
118
119static const phy_interface_t xpcs_10gbaser_interfaces[] = {
120 PHY_INTERFACE_MODE_10GBASER,
121};
122
123static const phy_interface_t xpcs_sgmii_interfaces[] = {
124 PHY_INTERFACE_MODE_SGMII,
125};
126
127static const phy_interface_t xpcs_1000basex_interfaces[] = {
128 PHY_INTERFACE_MODE_1000BASEX,
129};
130
131static const phy_interface_t xpcs_2500basex_interfaces[] = {
132 PHY_INTERFACE_MODE_2500BASEX,
133 PHY_INTERFACE_MODE_MAX,
134};
135
136enum {
137 DW_XPCS_USXGMII,
138 DW_XPCS_10GKR,
139 DW_XPCS_XLGMII,
140 DW_XPCS_10GBASER,
141 DW_XPCS_SGMII,
142 DW_XPCS_1000BASEX,
143 DW_XPCS_2500BASEX,
144 DW_XPCS_INTERFACE_MAX,
145};
146
147struct xpcs_compat {
148 const int *supported;
149 const phy_interface_t *interface;
150 int num_interfaces;
151 int an_mode;
152 int (*pma_config)(struct dw_xpcs *xpcs);
153};
154
155struct xpcs_id {
156 u32 id;
157 u32 mask;
158 const struct xpcs_compat *compat;
159};
160
161static const struct xpcs_compat *xpcs_find_compat(const struct xpcs_id *id,
162 phy_interface_t interface)
163{
164 int i, j;
165
166 for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) {
167 const struct xpcs_compat *compat = &id->compat[i];
168
169 for (j = 0; j < compat->num_interfaces; j++)
170 if (compat->interface[j] == interface)
171 return compat;
172 }
173
174 return NULL;
175}
176
177int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface)
178{
179 const struct xpcs_compat *compat;
180
181 compat = xpcs_find_compat(xpcs->id, interface);
182 if (!compat)
183 return -ENODEV;
184
185 return compat->an_mode;
186}
187EXPORT_SYMBOL_GPL(xpcs_get_an_mode);
188
189static bool __xpcs_linkmode_supported(const struct xpcs_compat *compat,
190 enum ethtool_link_mode_bit_indices linkmode)
191{
192 int i;
193
194 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
195 if (compat->supported[i] == linkmode)
196 return true;
197
198 return false;
199}
200
201#define xpcs_linkmode_supported(compat, mode) \
202 __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT)
203
204int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg)
205{
206 return mdiodev_c45_read(xpcs->mdiodev, dev, reg);
207}
208
209int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val)
210{
211 return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val);
212}
213
214static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg,
215 u16 mask, u16 set)
216{
217 return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set);
218}
219
220static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)
221{
222 return xpcs_read(xpcs, dev, DW_VENDOR | reg);
223}
224
225static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg,
226 u16 val)
227{
228 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val);
229}
230
231static int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg)
232{
233 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg);
234}
235
236static int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val)
237{
238 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val);
239}
240
241static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev)
242{
243 /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
244 unsigned int retries = 12;
245 int ret;
246
247 do {
248 msleep(50);
249 ret = xpcs_read(xpcs, dev, MDIO_CTRL1);
250 if (ret < 0)
251 return ret;
252 } while (ret & MDIO_CTRL1_RESET && --retries);
253
254 return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0;
255}
256
257static int xpcs_soft_reset(struct dw_xpcs *xpcs,
258 const struct xpcs_compat *compat)
259{
260 int ret, dev;
261
262 switch (compat->an_mode) {
263 case DW_AN_C73:
264 case DW_10GBASER:
265 dev = MDIO_MMD_PCS;
266 break;
267 case DW_AN_C37_SGMII:
268 case DW_2500BASEX:
269 case DW_AN_C37_1000BASEX:
270 dev = MDIO_MMD_VEND2;
271 break;
272 default:
273 return -1;
274 }
275
276 ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET);
277 if (ret < 0)
278 return ret;
279
280 return xpcs_poll_reset(xpcs, dev);
281}
282
283#define xpcs_warn(__xpcs, __state, __args...) \
284({ \
285 if ((__state)->link) \
286 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \
287})
288
289static int xpcs_read_fault_c73(struct dw_xpcs *xpcs,
290 struct phylink_link_state *state,
291 u16 pcs_stat1)
292{
293 int ret;
294
295 if (pcs_stat1 & MDIO_STAT1_FAULT) {
296 xpcs_warn(xpcs, state, "Link fault condition detected!\n");
297 return -EFAULT;
298 }
299
300 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2);
301 if (ret < 0)
302 return ret;
303
304 if (ret & MDIO_STAT2_RXFAULT)
305 xpcs_warn(xpcs, state, "Receiver fault detected!\n");
306 if (ret & MDIO_STAT2_TXFAULT)
307 xpcs_warn(xpcs, state, "Transmitter fault detected!\n");
308
309 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS);
310 if (ret < 0)
311 return ret;
312
313 if (ret & DW_RXFIFO_ERR) {
314 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n");
315 return -EFAULT;
316 }
317
318 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1);
319 if (ret < 0)
320 return ret;
321
322 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK))
323 xpcs_warn(xpcs, state, "Link is not locked!\n");
324
325 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2);
326 if (ret < 0)
327 return ret;
328
329 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) {
330 xpcs_warn(xpcs, state, "Link has errors!\n");
331 return -EFAULT;
332 }
333
334 return 0;
335}
336
337static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed)
338{
339 int ret, speed_sel;
340
341 switch (speed) {
342 case SPEED_10:
343 speed_sel = DW_USXGMII_10;
344 break;
345 case SPEED_100:
346 speed_sel = DW_USXGMII_100;
347 break;
348 case SPEED_1000:
349 speed_sel = DW_USXGMII_1000;
350 break;
351 case SPEED_2500:
352 speed_sel = DW_USXGMII_2500;
353 break;
354 case SPEED_5000:
355 speed_sel = DW_USXGMII_5000;
356 break;
357 case SPEED_10000:
358 speed_sel = DW_USXGMII_10000;
359 break;
360 default:
361 /* Nothing to do here */
362 return;
363 }
364
365 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
366 if (ret < 0)
367 goto out;
368
369 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN);
370 if (ret < 0)
371 goto out;
372
373 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
374 if (ret < 0)
375 goto out;
376
377 ret &= ~DW_USXGMII_SS_MASK;
378 ret |= speed_sel | DW_USXGMII_FULL;
379
380 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
381 if (ret < 0)
382 goto out;
383
384 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
385 if (ret < 0)
386 goto out;
387
388 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST);
389 if (ret < 0)
390 goto out;
391
392 return;
393
394out:
395 pr_err("%s: XPCS access returned %pe\n", __func__, ERR_PTR(ret));
396}
397
398static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
399 const struct xpcs_compat *compat)
400{
401 int ret, adv;
402
403 /* By default, in USXGMII mode XPCS operates at 10G baud and
404 * replicates data to achieve lower speeds. Hereby, in this
405 * default configuration we need to advertise all supported
406 * modes and not only the ones we want to use.
407 */
408
409 /* SR_AN_ADV3 */
410 adv = 0;
411 if (xpcs_linkmode_supported(compat, 2500baseX_Full))
412 adv |= DW_C73_2500KX;
413
414 /* TODO: 5000baseKR */
415
416 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv);
417 if (ret < 0)
418 return ret;
419
420 /* SR_AN_ADV2 */
421 adv = 0;
422 if (xpcs_linkmode_supported(compat, 1000baseKX_Full))
423 adv |= DW_C73_1000KX;
424 if (xpcs_linkmode_supported(compat, 10000baseKX4_Full))
425 adv |= DW_C73_10000KX4;
426 if (xpcs_linkmode_supported(compat, 10000baseKR_Full))
427 adv |= DW_C73_10000KR;
428
429 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv);
430 if (ret < 0)
431 return ret;
432
433 /* SR_AN_ADV1 */
434 adv = DW_C73_AN_ADV_SF;
435 if (xpcs_linkmode_supported(compat, Pause))
436 adv |= DW_C73_PAUSE;
437 if (xpcs_linkmode_supported(compat, Asym_Pause))
438 adv |= DW_C73_ASYM_PAUSE;
439
440 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv);
441}
442
443static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
444 const struct xpcs_compat *compat)
445{
446 int ret;
447
448 ret = _xpcs_config_aneg_c73(xpcs, compat);
449 if (ret < 0)
450 return ret;
451
452 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1);
453 if (ret < 0)
454 return ret;
455
456 ret |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART;
457
458 return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret);
459}
460
461static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs,
462 struct phylink_link_state *state,
463 const struct xpcs_compat *compat, u16 an_stat1)
464{
465 int ret;
466
467 if (an_stat1 & MDIO_AN_STAT1_COMPLETE) {
468 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA);
469 if (ret < 0)
470 return ret;
471
472 /* Check if Aneg outcome is valid */
473 if (!(ret & DW_C73_AN_ADV_SF)) {
474 xpcs_config_aneg_c73(xpcs, compat);
475 return 0;
476 }
477
478 return 1;
479 }
480
481 return 0;
482}
483
484static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs,
485 struct phylink_link_state *state, u16 an_stat1)
486{
487 u16 lpa[3];
488 int i, ret;
489
490 if (!(an_stat1 & MDIO_AN_STAT1_LPABLE)) {
491 phylink_clear(state->lp_advertising, Autoneg);
492 return 0;
493 }
494
495 phylink_set(state->lp_advertising, Autoneg);
496
497 /* Read Clause 73 link partner advertisement */
498 for (i = ARRAY_SIZE(lpa); --i >= 0; ) {
499 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i);
500 if (ret < 0)
501 return ret;
502
503 lpa[i] = ret;
504 }
505
506 mii_c73_mod_linkmode(state->lp_advertising, lpa);
507
508 return 0;
509}
510
511static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs,
512 struct phylink_link_state *state)
513{
514 unsigned long *adv = state->advertising;
515 int speed = SPEED_UNKNOWN;
516 int bit;
517
518 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) {
519 int new_speed = SPEED_UNKNOWN;
520
521 switch (bit) {
522 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
523 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
524 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
525 new_speed = SPEED_25000;
526 break;
527 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
528 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
529 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
530 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
531 new_speed = SPEED_40000;
532 break;
533 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT:
534 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT:
535 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT:
536 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
537 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
538 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
539 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
540 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT:
541 new_speed = SPEED_50000;
542 break;
543 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
544 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
545 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
546 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
547 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT:
548 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT:
549 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT:
550 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT:
551 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT:
552 new_speed = SPEED_100000;
553 break;
554 default:
555 continue;
556 }
557
558 if (new_speed > speed)
559 speed = new_speed;
560 }
561
562 return speed;
563}
564
565static void xpcs_resolve_pma(struct dw_xpcs *xpcs,
566 struct phylink_link_state *state)
567{
568 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
569 state->duplex = DUPLEX_FULL;
570
571 switch (state->interface) {
572 case PHY_INTERFACE_MODE_10GKR:
573 state->speed = SPEED_10000;
574 break;
575 case PHY_INTERFACE_MODE_XLGMII:
576 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state);
577 break;
578 default:
579 state->speed = SPEED_UNKNOWN;
580 break;
581 }
582}
583
584static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported,
585 const struct phylink_link_state *state)
586{
587 __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported) = { 0, };
588 const struct xpcs_compat *compat;
589 struct dw_xpcs *xpcs;
590 int i;
591
592 xpcs = phylink_pcs_to_xpcs(pcs);
593 compat = xpcs_find_compat(xpcs->id, state->interface);
594
595 /* Populate the supported link modes for this PHY interface type.
596 * FIXME: what about the port modes and autoneg bit? This masks
597 * all those away.
598 */
599 if (compat)
600 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
601 set_bit(compat->supported[i], xpcs_supported);
602
603 linkmode_and(supported, supported, xpcs_supported);
604
605 return 0;
606}
607
608void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces)
609{
610 int i, j;
611
612 for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) {
613 const struct xpcs_compat *compat = &xpcs->id->compat[i];
614
615 for (j = 0; j < compat->num_interfaces; j++)
616 if (compat->interface[j] < PHY_INTERFACE_MODE_MAX)
617 __set_bit(compat->interface[j], interfaces);
618 }
619}
620EXPORT_SYMBOL_GPL(xpcs_get_interfaces);
621
622int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable)
623{
624 int ret;
625
626 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0);
627 if (ret < 0)
628 return ret;
629
630 if (enable) {
631 /* Enable EEE */
632 ret = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
633 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
634 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
635 mult_fact_100ns << DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT;
636 } else {
637 ret &= ~(DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
638 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
639 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
640 DW_VR_MII_EEE_MULT_FACT_100NS);
641 }
642
643 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret);
644 if (ret < 0)
645 return ret;
646
647 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1);
648 if (ret < 0)
649 return ret;
650
651 if (enable)
652 ret |= DW_VR_MII_EEE_TRN_LPI;
653 else
654 ret &= ~DW_VR_MII_EEE_TRN_LPI;
655
656 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret);
657}
658EXPORT_SYMBOL_GPL(xpcs_config_eee);
659
660static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs,
661 unsigned int neg_mode)
662{
663 int ret, mdio_ctrl;
664
665 /* For AN for C37 SGMII mode, the settings are :-
666 * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case
667 it is already enabled)
668 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN)
669 * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII)
670 * DW xPCS used with DW EQoS MAC is always MAC side SGMII.
671 * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic
672 * speed/duplex mode change by HW after SGMII AN complete)
673 * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN)
674 *
675 * Note: Since it is MAC side SGMII, there is no need to set
676 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from
677 * PHY about the link state change after C28 AN is completed
678 * between PHY and Link Partner. There is also no need to
679 * trigger AN restart for MAC-side SGMII.
680 */
681 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
682 if (mdio_ctrl < 0)
683 return mdio_ctrl;
684
685 if (mdio_ctrl & AN_CL37_EN) {
686 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
687 mdio_ctrl & ~AN_CL37_EN);
688 if (ret < 0)
689 return ret;
690 }
691
692 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
693 if (ret < 0)
694 return ret;
695
696 ret &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK);
697 ret |= (DW_VR_MII_PCS_MODE_C37_SGMII <<
698 DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT &
699 DW_VR_MII_PCS_MODE_MASK);
700 ret |= (DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII <<
701 DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT &
702 DW_VR_MII_TX_CONFIG_MASK);
703 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
704 if (ret < 0)
705 return ret;
706
707 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
708 if (ret < 0)
709 return ret;
710
711 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
712 ret |= DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
713 else
714 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
715
716 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
717 if (ret < 0)
718 return ret;
719
720 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
721 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
722 mdio_ctrl | AN_CL37_EN);
723
724 return ret;
725}
726
727static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs,
728 unsigned int neg_mode,
729 const unsigned long *advertising)
730{
731 phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX;
732 int ret, mdio_ctrl, adv;
733 bool changed = 0;
734
735 /* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must
736 * be disabled first:-
737 * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b
738 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37)
739 */
740 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
741 if (mdio_ctrl < 0)
742 return mdio_ctrl;
743
744 if (mdio_ctrl & AN_CL37_EN) {
745 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
746 mdio_ctrl & ~AN_CL37_EN);
747 if (ret < 0)
748 return ret;
749 }
750
751 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
752 if (ret < 0)
753 return ret;
754
755 ret &= ~DW_VR_MII_PCS_MODE_MASK;
756 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
757 if (ret < 0)
758 return ret;
759
760 /* Check for advertising changes and update the C45 MII ADV
761 * register accordingly.
762 */
763 adv = phylink_mii_c22_pcs_encode_advertisement(interface,
764 advertising);
765 if (adv >= 0) {
766 ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2,
767 MII_ADVERTISE, 0xffff, adv);
768 if (ret < 0)
769 return ret;
770
771 changed = ret;
772 }
773
774 /* Clear CL37 AN complete status */
775 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
776 if (ret < 0)
777 return ret;
778
779 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
780 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
781 mdio_ctrl | AN_CL37_EN);
782 if (ret < 0)
783 return ret;
784 }
785
786 return changed;
787}
788
789static int xpcs_config_2500basex(struct dw_xpcs *xpcs)
790{
791 int ret;
792
793 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
794 if (ret < 0)
795 return ret;
796 ret |= DW_VR_MII_DIG_CTRL1_2G5_EN;
797 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
798 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
799 if (ret < 0)
800 return ret;
801
802 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
803 if (ret < 0)
804 return ret;
805 ret &= ~AN_CL37_EN;
806 ret |= SGMII_SPEED_SS6;
807 ret &= ~SGMII_SPEED_SS13;
808 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret);
809}
810
811int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
812 const unsigned long *advertising, unsigned int neg_mode)
813{
814 const struct xpcs_compat *compat;
815 int ret;
816
817 compat = xpcs_find_compat(xpcs->id, interface);
818 if (!compat)
819 return -ENODEV;
820
821 switch (compat->an_mode) {
822 case DW_10GBASER:
823 break;
824 case DW_AN_C73:
825 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
826 ret = xpcs_config_aneg_c73(xpcs, compat);
827 if (ret)
828 return ret;
829 }
830 break;
831 case DW_AN_C37_SGMII:
832 ret = xpcs_config_aneg_c37_sgmii(xpcs, neg_mode);
833 if (ret)
834 return ret;
835 break;
836 case DW_AN_C37_1000BASEX:
837 ret = xpcs_config_aneg_c37_1000basex(xpcs, neg_mode,
838 advertising);
839 if (ret)
840 return ret;
841 break;
842 case DW_2500BASEX:
843 ret = xpcs_config_2500basex(xpcs);
844 if (ret)
845 return ret;
846 break;
847 default:
848 return -1;
849 }
850
851 if (compat->pma_config) {
852 ret = compat->pma_config(xpcs);
853 if (ret)
854 return ret;
855 }
856
857 return 0;
858}
859EXPORT_SYMBOL_GPL(xpcs_do_config);
860
861static int xpcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
862 phy_interface_t interface,
863 const unsigned long *advertising,
864 bool permit_pause_to_mac)
865{
866 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
867
868 return xpcs_do_config(xpcs, interface, advertising, neg_mode);
869}
870
871static int xpcs_get_state_c73(struct dw_xpcs *xpcs,
872 struct phylink_link_state *state,
873 const struct xpcs_compat *compat)
874{
875 bool an_enabled;
876 int pcs_stat1;
877 int an_stat1;
878 int ret;
879
880 /* The link status bit is latching-low, so it is important to
881 * avoid unnecessary re-reads of this register to avoid missing
882 * a link-down event.
883 */
884 pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
885 if (pcs_stat1 < 0) {
886 state->link = false;
887 return pcs_stat1;
888 }
889
890 /* Link needs to be read first ... */
891 state->link = !!(pcs_stat1 & MDIO_STAT1_LSTATUS);
892
893 /* ... and then we check the faults. */
894 ret = xpcs_read_fault_c73(xpcs, state, pcs_stat1);
895 if (ret) {
896 ret = xpcs_soft_reset(xpcs, compat);
897 if (ret)
898 return ret;
899
900 state->link = 0;
901
902 return xpcs_do_config(xpcs, state->interface, NULL,
903 PHYLINK_PCS_NEG_INBAND_ENABLED);
904 }
905
906 /* There is no point doing anything else if the link is down. */
907 if (!state->link)
908 return 0;
909
910 an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
911 state->advertising);
912 if (an_enabled) {
913 /* The link status bit is latching-low, so it is important to
914 * avoid unnecessary re-reads of this register to avoid missing
915 * a link-down event.
916 */
917 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
918 if (an_stat1 < 0) {
919 state->link = false;
920 return an_stat1;
921 }
922
923 state->an_complete = xpcs_aneg_done_c73(xpcs, state, compat,
924 an_stat1);
925 if (!state->an_complete) {
926 state->link = false;
927 return 0;
928 }
929
930 ret = xpcs_read_lpa_c73(xpcs, state, an_stat1);
931 if (ret < 0) {
932 state->link = false;
933 return ret;
934 }
935
936 phylink_resolve_c73(state);
937 } else {
938 xpcs_resolve_pma(xpcs, state);
939 }
940
941 return 0;
942}
943
944static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
945 struct phylink_link_state *state)
946{
947 int ret;
948
949 /* Reset link_state */
950 state->link = false;
951 state->speed = SPEED_UNKNOWN;
952 state->duplex = DUPLEX_UNKNOWN;
953 state->pause = 0;
954
955 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link
956 * status, speed and duplex.
957 */
958 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
959 if (ret < 0)
960 return ret;
961
962 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) {
963 int speed_value;
964
965 state->link = true;
966
967 speed_value = (ret & DW_VR_MII_AN_STS_C37_ANSGM_SP) >>
968 DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT;
969 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000)
970 state->speed = SPEED_1000;
971 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100)
972 state->speed = SPEED_100;
973 else
974 state->speed = SPEED_10;
975
976 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD)
977 state->duplex = DUPLEX_FULL;
978 else
979 state->duplex = DUPLEX_HALF;
980 }
981
982 return 0;
983}
984
985static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs,
986 struct phylink_link_state *state)
987{
988 int lpa, bmsr;
989
990 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
991 state->advertising)) {
992 /* Reset link state */
993 state->link = false;
994
995 lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA);
996 if (lpa < 0 || lpa & LPA_RFAULT)
997 return lpa;
998
999 bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR);
1000 if (bmsr < 0)
1001 return bmsr;
1002
1003 phylink_mii_c22_pcs_decode_state(state, bmsr, lpa);
1004 }
1005
1006 return 0;
1007}
1008
1009static void xpcs_get_state(struct phylink_pcs *pcs,
1010 struct phylink_link_state *state)
1011{
1012 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1013 const struct xpcs_compat *compat;
1014 int ret;
1015
1016 compat = xpcs_find_compat(xpcs->id, state->interface);
1017 if (!compat)
1018 return;
1019
1020 switch (compat->an_mode) {
1021 case DW_10GBASER:
1022 phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state);
1023 break;
1024 case DW_AN_C73:
1025 ret = xpcs_get_state_c73(xpcs, state, compat);
1026 if (ret) {
1027 pr_err("xpcs_get_state_c73 returned %pe\n",
1028 ERR_PTR(ret));
1029 return;
1030 }
1031 break;
1032 case DW_AN_C37_SGMII:
1033 ret = xpcs_get_state_c37_sgmii(xpcs, state);
1034 if (ret) {
1035 pr_err("xpcs_get_state_c37_sgmii returned %pe\n",
1036 ERR_PTR(ret));
1037 }
1038 break;
1039 case DW_AN_C37_1000BASEX:
1040 ret = xpcs_get_state_c37_1000basex(xpcs, state);
1041 if (ret) {
1042 pr_err("xpcs_get_state_c37_1000basex returned %pe\n",
1043 ERR_PTR(ret));
1044 }
1045 break;
1046 default:
1047 return;
1048 }
1049}
1050
1051static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int neg_mode,
1052 int speed, int duplex)
1053{
1054 int val, ret;
1055
1056 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
1057 return;
1058
1059 val = mii_bmcr_encode_fixed(speed, duplex);
1060 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
1061 if (ret)
1062 pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
1063}
1064
1065static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, unsigned int neg_mode,
1066 int speed, int duplex)
1067{
1068 int val, ret;
1069
1070 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
1071 return;
1072
1073 switch (speed) {
1074 case SPEED_1000:
1075 val = BMCR_SPEED1000;
1076 break;
1077 case SPEED_100:
1078 case SPEED_10:
1079 default:
1080 pr_err("%s: speed = %d\n", __func__, speed);
1081 return;
1082 }
1083
1084 if (duplex == DUPLEX_FULL)
1085 val |= BMCR_FULLDPLX;
1086 else
1087 pr_err("%s: half duplex not supported\n", __func__);
1088
1089 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
1090 if (ret)
1091 pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
1092}
1093
1094void xpcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
1095 phy_interface_t interface, int speed, int duplex)
1096{
1097 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1098
1099 if (interface == PHY_INTERFACE_MODE_USXGMII)
1100 return xpcs_config_usxgmii(xpcs, speed);
1101 if (interface == PHY_INTERFACE_MODE_SGMII)
1102 return xpcs_link_up_sgmii(xpcs, neg_mode, speed, duplex);
1103 if (interface == PHY_INTERFACE_MODE_1000BASEX)
1104 return xpcs_link_up_1000basex(xpcs, neg_mode, speed, duplex);
1105}
1106EXPORT_SYMBOL_GPL(xpcs_link_up);
1107
1108static void xpcs_an_restart(struct phylink_pcs *pcs)
1109{
1110 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1111 int ret;
1112
1113 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
1114 if (ret >= 0) {
1115 ret |= BMCR_ANRESTART;
1116 xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
1117 }
1118}
1119
1120static u32 xpcs_get_id(struct dw_xpcs *xpcs)
1121{
1122 int ret;
1123 u32 id;
1124
1125 /* First, search C73 PCS using PCS MMD */
1126 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1);
1127 if (ret < 0)
1128 return 0xffffffff;
1129
1130 id = ret << 16;
1131
1132 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2);
1133 if (ret < 0)
1134 return 0xffffffff;
1135
1136 /* If Device IDs are not all zeros or all ones,
1137 * we found C73 AN-type device
1138 */
1139 if ((id | ret) && (id | ret) != 0xffffffff)
1140 return id | ret;
1141
1142 /* Next, search C37 PCS using Vendor-Specific MII MMD */
1143 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1);
1144 if (ret < 0)
1145 return 0xffffffff;
1146
1147 id = ret << 16;
1148
1149 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2);
1150 if (ret < 0)
1151 return 0xffffffff;
1152
1153 /* If Device IDs are not all zeros, we found C37 AN-type device */
1154 if (id | ret)
1155 return id | ret;
1156
1157 return 0xffffffff;
1158}
1159
1160static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1161 [DW_XPCS_USXGMII] = {
1162 .supported = xpcs_usxgmii_features,
1163 .interface = xpcs_usxgmii_interfaces,
1164 .num_interfaces = ARRAY_SIZE(xpcs_usxgmii_interfaces),
1165 .an_mode = DW_AN_C73,
1166 },
1167 [DW_XPCS_10GKR] = {
1168 .supported = xpcs_10gkr_features,
1169 .interface = xpcs_10gkr_interfaces,
1170 .num_interfaces = ARRAY_SIZE(xpcs_10gkr_interfaces),
1171 .an_mode = DW_AN_C73,
1172 },
1173 [DW_XPCS_XLGMII] = {
1174 .supported = xpcs_xlgmii_features,
1175 .interface = xpcs_xlgmii_interfaces,
1176 .num_interfaces = ARRAY_SIZE(xpcs_xlgmii_interfaces),
1177 .an_mode = DW_AN_C73,
1178 },
1179 [DW_XPCS_10GBASER] = {
1180 .supported = xpcs_10gbaser_features,
1181 .interface = xpcs_10gbaser_interfaces,
1182 .num_interfaces = ARRAY_SIZE(xpcs_10gbaser_interfaces),
1183 .an_mode = DW_10GBASER,
1184 },
1185 [DW_XPCS_SGMII] = {
1186 .supported = xpcs_sgmii_features,
1187 .interface = xpcs_sgmii_interfaces,
1188 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1189 .an_mode = DW_AN_C37_SGMII,
1190 },
1191 [DW_XPCS_1000BASEX] = {
1192 .supported = xpcs_1000basex_features,
1193 .interface = xpcs_1000basex_interfaces,
1194 .num_interfaces = ARRAY_SIZE(xpcs_1000basex_interfaces),
1195 .an_mode = DW_AN_C37_1000BASEX,
1196 },
1197 [DW_XPCS_2500BASEX] = {
1198 .supported = xpcs_2500basex_features,
1199 .interface = xpcs_2500basex_interfaces,
1200 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces),
1201 .an_mode = DW_2500BASEX,
1202 },
1203};
1204
1205static const struct xpcs_compat nxp_sja1105_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1206 [DW_XPCS_SGMII] = {
1207 .supported = xpcs_sgmii_features,
1208 .interface = xpcs_sgmii_interfaces,
1209 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1210 .an_mode = DW_AN_C37_SGMII,
1211 .pma_config = nxp_sja1105_sgmii_pma_config,
1212 },
1213};
1214
1215static const struct xpcs_compat nxp_sja1110_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1216 [DW_XPCS_SGMII] = {
1217 .supported = xpcs_sgmii_features,
1218 .interface = xpcs_sgmii_interfaces,
1219 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1220 .an_mode = DW_AN_C37_SGMII,
1221 .pma_config = nxp_sja1110_sgmii_pma_config,
1222 },
1223 [DW_XPCS_2500BASEX] = {
1224 .supported = xpcs_2500basex_features,
1225 .interface = xpcs_2500basex_interfaces,
1226 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces),
1227 .an_mode = DW_2500BASEX,
1228 .pma_config = nxp_sja1110_2500basex_pma_config,
1229 },
1230};
1231
1232static const struct xpcs_id xpcs_id_list[] = {
1233 {
1234 .id = SYNOPSYS_XPCS_ID,
1235 .mask = SYNOPSYS_XPCS_MASK,
1236 .compat = synopsys_xpcs_compat,
1237 }, {
1238 .id = NXP_SJA1105_XPCS_ID,
1239 .mask = SYNOPSYS_XPCS_MASK,
1240 .compat = nxp_sja1105_xpcs_compat,
1241 }, {
1242 .id = NXP_SJA1110_XPCS_ID,
1243 .mask = SYNOPSYS_XPCS_MASK,
1244 .compat = nxp_sja1110_xpcs_compat,
1245 },
1246};
1247
1248static const struct phylink_pcs_ops xpcs_phylink_ops = {
1249 .pcs_validate = xpcs_validate,
1250 .pcs_config = xpcs_config,
1251 .pcs_get_state = xpcs_get_state,
1252 .pcs_an_restart = xpcs_an_restart,
1253 .pcs_link_up = xpcs_link_up,
1254};
1255
1256static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev,
1257 phy_interface_t interface)
1258{
1259 struct dw_xpcs *xpcs;
1260 u32 xpcs_id;
1261 int i, ret;
1262
1263 xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL);
1264 if (!xpcs)
1265 return ERR_PTR(-ENOMEM);
1266
1267 mdio_device_get(mdiodev);
1268 xpcs->mdiodev = mdiodev;
1269
1270 xpcs_id = xpcs_get_id(xpcs);
1271
1272 for (i = 0; i < ARRAY_SIZE(xpcs_id_list); i++) {
1273 const struct xpcs_id *entry = &xpcs_id_list[i];
1274 const struct xpcs_compat *compat;
1275
1276 if ((xpcs_id & entry->mask) != entry->id)
1277 continue;
1278
1279 xpcs->id = entry;
1280
1281 compat = xpcs_find_compat(entry, interface);
1282 if (!compat) {
1283 ret = -ENODEV;
1284 goto out;
1285 }
1286
1287 xpcs->pcs.ops = &xpcs_phylink_ops;
1288 xpcs->pcs.neg_mode = true;
1289 if (compat->an_mode == DW_10GBASER)
1290 return xpcs;
1291
1292 xpcs->pcs.poll = true;
1293
1294 ret = xpcs_soft_reset(xpcs, compat);
1295 if (ret)
1296 goto out;
1297
1298 return xpcs;
1299 }
1300
1301 ret = -ENODEV;
1302
1303out:
1304 mdio_device_put(mdiodev);
1305 kfree(xpcs);
1306
1307 return ERR_PTR(ret);
1308}
1309
1310void xpcs_destroy(struct dw_xpcs *xpcs)
1311{
1312 if (xpcs)
1313 mdio_device_put(xpcs->mdiodev);
1314 kfree(xpcs);
1315}
1316EXPORT_SYMBOL_GPL(xpcs_destroy);
1317
1318struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr,
1319 phy_interface_t interface)
1320{
1321 struct mdio_device *mdiodev;
1322 struct dw_xpcs *xpcs;
1323
1324 mdiodev = mdio_device_create(bus, addr);
1325 if (IS_ERR(mdiodev))
1326 return ERR_CAST(mdiodev);
1327
1328 xpcs = xpcs_create(mdiodev, interface);
1329
1330 /* xpcs_create() has taken a refcount on the mdiodev if it was
1331 * successful. If xpcs_create() fails, this will free the mdio
1332 * device here. In any case, we don't need to hold our reference
1333 * anymore, and putting it here will allow mdio_device_put() in
1334 * xpcs_destroy() to automatically free the mdio device.
1335 */
1336 mdio_device_put(mdiodev);
1337
1338 return xpcs;
1339}
1340EXPORT_SYMBOL_GPL(xpcs_create_mdiodev);
1341
1342MODULE_LICENSE("GPL v2");