Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
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linux
1/* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */
2/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3#ifndef _USR_IDXD_H_
4#define _USR_IDXD_H_
5
6#ifdef __KERNEL__
7#include <linux/types.h>
8#else
9#include <stdint.h>
10#endif
11
12/* Driver command error status */
13enum idxd_scmd_stat {
14 IDXD_SCMD_DEV_ENABLED = 0x80000010,
15 IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020,
16 IDXD_SCMD_WQ_ENABLED = 0x80000021,
17 IDXD_SCMD_DEV_DMA_ERR = 0x80020000,
18 IDXD_SCMD_WQ_NO_GRP = 0x80030000,
19 IDXD_SCMD_WQ_NO_NAME = 0x80040000,
20 IDXD_SCMD_WQ_NO_SVM = 0x80050000,
21 IDXD_SCMD_WQ_NO_THRESH = 0x80060000,
22 IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000,
23 IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000,
24 IDXD_SCMD_PERCPU_ERR = 0x80090000,
25 IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000,
26 IDXD_SCMD_CDEV_ERR = 0x800b0000,
27 IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000,
28 IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000,
29 IDXD_SCMD_WQ_NO_SIZE = 0x800e0000,
30 IDXD_SCMD_WQ_NO_PRIV = 0x800f0000,
31 IDXD_SCMD_WQ_IRQ_ERR = 0x80100000,
32 IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000,
33 IDXD_SCMD_DEV_EVL_ERR = 0x80120000,
34};
35
36#define IDXD_SCMD_SOFTERR_MASK 0x80000000
37#define IDXD_SCMD_SOFTERR_SHIFT 16
38
39/* Descriptor flags */
40#define IDXD_OP_FLAG_FENCE 0x0001
41#define IDXD_OP_FLAG_BOF 0x0002
42#define IDXD_OP_FLAG_CRAV 0x0004
43#define IDXD_OP_FLAG_RCR 0x0008
44#define IDXD_OP_FLAG_RCI 0x0010
45#define IDXD_OP_FLAG_CRSTS 0x0020
46#define IDXD_OP_FLAG_CR 0x0080
47#define IDXD_OP_FLAG_CC 0x0100
48#define IDXD_OP_FLAG_ADDR1_TCS 0x0200
49#define IDXD_OP_FLAG_ADDR2_TCS 0x0400
50#define IDXD_OP_FLAG_ADDR3_TCS 0x0800
51#define IDXD_OP_FLAG_CR_TCS 0x1000
52#define IDXD_OP_FLAG_STORD 0x2000
53#define IDXD_OP_FLAG_DRDBK 0x4000
54#define IDXD_OP_FLAG_DSTS 0x8000
55
56/* IAX */
57#define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000
58#define IDXD_OP_FLAG_RD_SRC2_2ND 0x020000
59#define IDXD_OP_FLAG_WR_SRC2_AECS_COMP 0x040000
60#define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL 0x080000
61#define IDXD_OP_FLAG_SRC2_STS 0x100000
62#define IDXD_OP_FLAG_CRC_RFC3720 0x200000
63
64/* Opcode */
65enum dsa_opcode {
66 DSA_OPCODE_NOOP = 0,
67 DSA_OPCODE_BATCH,
68 DSA_OPCODE_DRAIN,
69 DSA_OPCODE_MEMMOVE,
70 DSA_OPCODE_MEMFILL,
71 DSA_OPCODE_COMPARE,
72 DSA_OPCODE_COMPVAL,
73 DSA_OPCODE_CR_DELTA,
74 DSA_OPCODE_AP_DELTA,
75 DSA_OPCODE_DUALCAST,
76 DSA_OPCODE_TRANSL_FETCH,
77 DSA_OPCODE_CRCGEN = 0x10,
78 DSA_OPCODE_COPY_CRC,
79 DSA_OPCODE_DIF_CHECK,
80 DSA_OPCODE_DIF_INS,
81 DSA_OPCODE_DIF_STRP,
82 DSA_OPCODE_DIF_UPDT,
83 DSA_OPCODE_DIX_GEN = 0x17,
84 DSA_OPCODE_CFLUSH = 0x20,
85};
86
87enum iax_opcode {
88 IAX_OPCODE_NOOP = 0,
89 IAX_OPCODE_DRAIN = 2,
90 IAX_OPCODE_MEMMOVE,
91 IAX_OPCODE_DECOMPRESS = 0x42,
92 IAX_OPCODE_COMPRESS,
93 IAX_OPCODE_CRC64,
94 IAX_OPCODE_ZERO_DECOMP_32 = 0x48,
95 IAX_OPCODE_ZERO_DECOMP_16,
96 IAX_OPCODE_ZERO_COMP_32 = 0x4c,
97 IAX_OPCODE_ZERO_COMP_16,
98 IAX_OPCODE_SCAN = 0x50,
99 IAX_OPCODE_SET_MEMBER,
100 IAX_OPCODE_EXTRACT,
101 IAX_OPCODE_SELECT,
102 IAX_OPCODE_RLE_BURST,
103 IAX_OPCODE_FIND_UNIQUE,
104 IAX_OPCODE_EXPAND,
105};
106
107/* Completion record status */
108enum dsa_completion_status {
109 DSA_COMP_NONE = 0,
110 DSA_COMP_SUCCESS,
111 DSA_COMP_SUCCESS_PRED,
112 DSA_COMP_PAGE_FAULT_NOBOF,
113 DSA_COMP_PAGE_FAULT_IR,
114 DSA_COMP_BATCH_FAIL,
115 DSA_COMP_BATCH_PAGE_FAULT,
116 DSA_COMP_DR_OFFSET_NOINC,
117 DSA_COMP_DR_OFFSET_ERANGE,
118 DSA_COMP_DIF_ERR,
119 DSA_COMP_BAD_OPCODE = 0x10,
120 DSA_COMP_INVALID_FLAGS,
121 DSA_COMP_NOZERO_RESERVE,
122 DSA_COMP_XFER_ERANGE,
123 DSA_COMP_DESC_CNT_ERANGE,
124 DSA_COMP_DR_ERANGE,
125 DSA_COMP_OVERLAP_BUFFERS,
126 DSA_COMP_DCAST_ERR,
127 DSA_COMP_DESCLIST_ALIGN,
128 DSA_COMP_INT_HANDLE_INVAL,
129 DSA_COMP_CRA_XLAT,
130 DSA_COMP_CRA_ALIGN,
131 DSA_COMP_ADDR_ALIGN,
132 DSA_COMP_PRIV_BAD,
133 DSA_COMP_TRAFFIC_CLASS_CONF,
134 DSA_COMP_PFAULT_RDBA,
135 DSA_COMP_HW_ERR1,
136 DSA_COMP_HW_ERR_DRB,
137 DSA_COMP_TRANSLATION_FAIL,
138 DSA_COMP_DRAIN_EVL = 0x26,
139 DSA_COMP_BATCH_EVL_ERR,
140};
141
142enum iax_completion_status {
143 IAX_COMP_NONE = 0,
144 IAX_COMP_SUCCESS,
145 IAX_COMP_PAGE_FAULT_IR = 0x04,
146 IAX_COMP_ANALYTICS_ERROR = 0x0a,
147 IAX_COMP_OUTBUF_OVERFLOW,
148 IAX_COMP_BAD_OPCODE = 0x10,
149 IAX_COMP_INVALID_FLAGS,
150 IAX_COMP_NOZERO_RESERVE,
151 IAX_COMP_INVALID_SIZE,
152 IAX_COMP_OVERLAP_BUFFERS = 0x16,
153 IAX_COMP_INT_HANDLE_INVAL = 0x19,
154 IAX_COMP_CRA_XLAT,
155 IAX_COMP_CRA_ALIGN,
156 IAX_COMP_ADDR_ALIGN,
157 IAX_COMP_PRIV_BAD,
158 IAX_COMP_TRAFFIC_CLASS_CONF,
159 IAX_COMP_PFAULT_RDBA,
160 IAX_COMP_HW_ERR1,
161 IAX_COMP_HW_ERR_DRB,
162 IAX_COMP_TRANSLATION_FAIL,
163 IAX_COMP_PRS_TIMEOUT,
164 IAX_COMP_WATCHDOG,
165 IAX_COMP_INVALID_COMP_FLAG = 0x30,
166 IAX_COMP_INVALID_FILTER_FLAG,
167 IAX_COMP_INVALID_INPUT_SIZE,
168 IAX_COMP_INVALID_NUM_ELEMS,
169 IAX_COMP_INVALID_SRC1_WIDTH,
170 IAX_COMP_INVALID_INVERT_OUT,
171};
172
173#define DSA_COMP_STATUS_MASK 0x7f
174#define DSA_COMP_STATUS_WRITE 0x80
175#define DSA_COMP_STATUS(status) ((status) & DSA_COMP_STATUS_MASK)
176
177struct dsa_hw_desc {
178 uint32_t pasid:20;
179 uint32_t rsvd:11;
180 uint32_t priv:1;
181 uint32_t flags:24;
182 uint32_t opcode:8;
183 uint64_t completion_addr;
184 union {
185 uint64_t src_addr;
186 uint64_t rdback_addr;
187 uint64_t pattern;
188 uint64_t desc_list_addr;
189 uint64_t pattern_lower;
190 uint64_t transl_fetch_addr;
191 };
192 union {
193 uint64_t dst_addr;
194 uint64_t rdback_addr2;
195 uint64_t src2_addr;
196 uint64_t comp_pattern;
197 };
198 union {
199 uint32_t xfer_size;
200 uint32_t desc_count;
201 uint32_t region_size;
202 };
203 uint16_t int_handle;
204 uint16_t rsvd1;
205 union {
206 uint8_t expected_res;
207 /* create delta record */
208 struct {
209 uint64_t delta_addr;
210 uint32_t max_delta_size;
211 uint32_t delt_rsvd;
212 uint8_t expected_res_mask;
213 };
214 uint32_t delta_rec_size;
215 uint64_t dest2;
216 /* CRC */
217 struct {
218 uint32_t crc_seed;
219 uint32_t crc_rsvd;
220 uint64_t seed_addr;
221 };
222 /* DIF check or strip */
223 struct {
224 uint8_t src_dif_flags;
225 uint8_t dif_chk_res;
226 uint8_t dif_chk_flags;
227 uint8_t dif_chk_res2[5];
228 uint32_t chk_ref_tag_seed;
229 uint16_t chk_app_tag_mask;
230 uint16_t chk_app_tag_seed;
231 };
232 /* DIF insert */
233 struct {
234 uint8_t dif_ins_res;
235 uint8_t dest_dif_flag;
236 uint8_t dif_ins_flags;
237 uint8_t dif_ins_res2[13];
238 uint32_t ins_ref_tag_seed;
239 uint16_t ins_app_tag_mask;
240 uint16_t ins_app_tag_seed;
241 };
242 /* DIF update */
243 struct {
244 uint8_t src_upd_flags;
245 uint8_t upd_dest_flags;
246 uint8_t dif_upd_flags;
247 uint8_t dif_upd_res[5];
248 uint32_t src_ref_tag_seed;
249 uint16_t src_app_tag_mask;
250 uint16_t src_app_tag_seed;
251 uint32_t dest_ref_tag_seed;
252 uint16_t dest_app_tag_mask;
253 uint16_t dest_app_tag_seed;
254 };
255
256 /* Fill */
257 uint64_t pattern_upper;
258
259 /* Translation fetch */
260 struct {
261 uint64_t transl_fetch_res;
262 uint32_t region_stride;
263 };
264
265 /* DIX generate */
266 struct {
267 uint8_t dix_gen_res;
268 uint8_t dest_dif_flags;
269 uint8_t dif_flags;
270 uint8_t dix_gen_res2[13];
271 uint32_t ref_tag_seed;
272 uint16_t app_tag_mask;
273 uint16_t app_tag_seed;
274 };
275
276 uint8_t op_specific[24];
277 };
278} __attribute__((packed));
279
280struct iax_hw_desc {
281 uint32_t pasid:20;
282 uint32_t rsvd:11;
283 uint32_t priv:1;
284 uint32_t flags:24;
285 uint32_t opcode:8;
286 uint64_t completion_addr;
287 uint64_t src1_addr;
288 uint64_t dst_addr;
289 uint32_t src1_size;
290 uint16_t int_handle;
291 union {
292 uint16_t compr_flags;
293 uint16_t decompr_flags;
294 };
295 uint64_t src2_addr;
296 uint32_t max_dst_size;
297 uint32_t src2_size;
298 uint32_t filter_flags;
299 uint32_t num_inputs;
300} __attribute__((packed));
301
302struct dsa_raw_desc {
303 uint64_t field[8];
304} __attribute__((packed));
305
306/*
307 * The status field will be modified by hardware, therefore it should be
308 * volatile and prevent the compiler from optimize the read.
309 */
310struct dsa_completion_record {
311 volatile uint8_t status;
312 union {
313 uint8_t result;
314 uint8_t dif_status;
315 };
316 uint8_t fault_info;
317 uint8_t rsvd;
318 union {
319 uint32_t bytes_completed;
320 uint32_t descs_completed;
321 };
322 uint64_t fault_addr;
323 union {
324 /* common record */
325 struct {
326 uint32_t invalid_flags:24;
327 uint32_t rsvd2:8;
328 };
329
330 uint32_t delta_rec_size;
331 uint64_t crc_val;
332
333 /* DIF check & strip */
334 struct {
335 uint32_t dif_chk_ref_tag;
336 uint16_t dif_chk_app_tag_mask;
337 uint16_t dif_chk_app_tag;
338 };
339
340 /* DIF insert */
341 struct {
342 uint64_t dif_ins_res;
343 uint32_t dif_ins_ref_tag;
344 uint16_t dif_ins_app_tag_mask;
345 uint16_t dif_ins_app_tag;
346 };
347
348 /* DIF update */
349 struct {
350 uint32_t dif_upd_src_ref_tag;
351 uint16_t dif_upd_src_app_tag_mask;
352 uint16_t dif_upd_src_app_tag;
353 uint32_t dif_upd_dest_ref_tag;
354 uint16_t dif_upd_dest_app_tag_mask;
355 uint16_t dif_upd_dest_app_tag;
356 };
357
358 /* DIX generate */
359 struct {
360 uint64_t dix_gen_res;
361 uint32_t dix_ref_tag;
362 uint16_t dix_app_tag_mask;
363 uint16_t dix_app_tag;
364 };
365
366 uint8_t op_specific[16];
367 };
368} __attribute__((packed));
369
370struct dsa_raw_completion_record {
371 uint64_t field[4];
372} __attribute__((packed));
373
374struct iax_completion_record {
375 volatile uint8_t status;
376 uint8_t error_code;
377 uint8_t fault_info;
378 uint8_t rsvd;
379 uint32_t bytes_completed;
380 uint64_t fault_addr;
381 uint32_t invalid_flags;
382 uint32_t rsvd2;
383 uint32_t output_size;
384 uint8_t output_bits;
385 uint8_t rsvd3;
386 uint16_t xor_csum;
387 uint32_t crc;
388 uint32_t min;
389 uint32_t max;
390 uint32_t sum;
391 uint64_t rsvd4[2];
392} __attribute__((packed));
393
394struct iax_raw_completion_record {
395 uint64_t field[8];
396} __attribute__((packed));
397
398#endif