tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
5 * Ryder Lee <ryder.lee@mediatek.com>
6 */
7
8#include <linux/clk.h>
9#include <linux/clk-provider.h>
10#include <linux/of.h>
11#include <linux/of_address.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14
15#include "clk-cpumux.h"
16#include "clk-gate.h"
17#include "clk-mtk.h"
18#include "clk-pll.h"
19
20#include <dt-bindings/clock/mt7629-clk.h>
21
22#define MT7629_PLL_FMAX (2500UL * MHZ)
23#define CON0_MT7629_RST_BAR BIT(24)
24
25#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
26 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
27 _pcw_shift, _div_table, _parent_name) { \
28 .id = _id, \
29 .name = _name, \
30 .reg = _reg, \
31 .pwr_reg = _pwr_reg, \
32 .en_mask = _en_mask, \
33 .flags = _flags, \
34 .rst_bar_mask = CON0_MT7629_RST_BAR, \
35 .fmax = MT7629_PLL_FMAX, \
36 .pcwbits = _pcwbits, \
37 .pd_reg = _pd_reg, \
38 .pd_shift = _pd_shift, \
39 .tuner_reg = _tuner_reg, \
40 .pcw_reg = _pcw_reg, \
41 .pcw_shift = _pcw_shift, \
42 .div_table = _div_table, \
43 .parent_name = _parent_name, \
44 }
45
46#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
47 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
48 _pcw_shift) \
49 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
50 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
51 NULL, "clk20m")
52
53#define GATE_APMIXED(_id, _name, _parent, _shift) \
54 GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
55
56#define GATE_INFRA(_id, _name, _parent, _shift) \
57 GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
58
59#define GATE_PERI0(_id, _name, _parent, _shift) \
60 GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
61
62#define GATE_PERI1(_id, _name, _parent, _shift) \
63 GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
64
65static DEFINE_SPINLOCK(mt7629_clk_lock);
66
67static const char * const axi_parents[] = {
68 "clkxtal",
69 "syspll1_d2",
70 "syspll_d5",
71 "syspll1_d4",
72 "univpll_d5",
73 "univpll2_d2",
74 "univpll_d7",
75 "dmpll_ck"
76};
77
78static const char * const mem_parents[] = {
79 "clkxtal",
80 "dmpll_ck"
81};
82
83static const char * const ddrphycfg_parents[] = {
84 "clkxtal",
85 "syspll1_d8"
86};
87
88static const char * const eth_parents[] = {
89 "clkxtal",
90 "syspll1_d2",
91 "univpll1_d2",
92 "syspll1_d4",
93 "univpll_d5",
94 "sgmiipll_d2",
95 "univpll_d7",
96 "dmpll_ck"
97};
98
99static const char * const pwm_parents[] = {
100 "clkxtal",
101 "univpll2_d4"
102};
103
104static const char * const f10m_ref_parents[] = {
105 "clkxtal",
106 "sgmiipll_d2"
107};
108
109static const char * const nfi_infra_parents[] = {
110 "clkxtal",
111 "clkxtal",
112 "clkxtal",
113 "clkxtal",
114 "clkxtal",
115 "clkxtal",
116 "univpll2_d8",
117 "univpll3_d4",
118 "syspll1_d8",
119 "univpll1_d8",
120 "syspll4_d2",
121 "syspll2_d4",
122 "univpll2_d4",
123 "univpll3_d2",
124 "syspll1_d4",
125 "syspll_d7"
126};
127
128static const char * const flash_parents[] = {
129 "clkxtal",
130 "univpll_d80_d4",
131 "syspll2_d8",
132 "syspll3_d4",
133 "univpll3_d4",
134 "univpll1_d8",
135 "syspll2_d4",
136 "univpll2_d4"
137};
138
139static const char * const uart_parents[] = {
140 "clkxtal",
141 "univpll2_d8"
142};
143
144static const char * const spi0_parents[] = {
145 "clkxtal",
146 "syspll3_d2",
147 "clkxtal",
148 "syspll2_d4",
149 "syspll4_d2",
150 "univpll2_d4",
151 "univpll1_d8",
152 "clkxtal"
153};
154
155static const char * const spi1_parents[] = {
156 "clkxtal",
157 "syspll3_d2",
158 "clkxtal",
159 "syspll4_d4",
160 "syspll4_d2",
161 "univpll2_d4",
162 "univpll1_d8",
163 "clkxtal"
164};
165
166static const char * const msdc30_0_parents[] = {
167 "clkxtal",
168 "univpll2_d16",
169 "univ48m"
170};
171
172static const char * const msdc30_1_parents[] = {
173 "clkxtal",
174 "univpll2_d16",
175 "univ48m",
176 "syspll2_d4",
177 "univpll2_d4",
178 "syspll_d7",
179 "syspll2_d2",
180 "univpll2_d2"
181};
182
183static const char * const ap2wbmcu_parents[] = {
184 "clkxtal",
185 "syspll1_d2",
186 "univ48m",
187 "syspll1_d8",
188 "univpll2_d4",
189 "syspll_d7",
190 "syspll2_d2",
191 "univpll2_d2"
192};
193
194static const char * const audio_parents[] = {
195 "clkxtal",
196 "syspll3_d4",
197 "syspll4_d4",
198 "syspll1_d16"
199};
200
201static const char * const aud_intbus_parents[] = {
202 "clkxtal",
203 "syspll1_d4",
204 "syspll4_d2",
205 "dmpll_d4"
206};
207
208static const char * const pmicspi_parents[] = {
209 "clkxtal",
210 "syspll1_d8",
211 "syspll3_d4",
212 "syspll1_d16",
213 "univpll3_d4",
214 "clkxtal",
215 "univpll2_d4",
216 "dmpll_d8"
217};
218
219static const char * const scp_parents[] = {
220 "clkxtal",
221 "syspll1_d8",
222 "univpll2_d2",
223 "univpll2_d4"
224};
225
226static const char * const atb_parents[] = {
227 "clkxtal",
228 "syspll1_d2",
229 "syspll_d5"
230};
231
232static const char * const hif_parents[] = {
233 "clkxtal",
234 "syspll1_d2",
235 "univpll1_d2",
236 "syspll1_d4",
237 "univpll_d5",
238 "clk_null",
239 "univpll_d7"
240};
241
242static const char * const sata_parents[] = {
243 "clkxtal",
244 "univpll2_d4"
245};
246
247static const char * const usb20_parents[] = {
248 "clkxtal",
249 "univpll3_d4",
250 "syspll1_d8"
251};
252
253static const char * const aud1_parents[] = {
254 "clkxtal"
255};
256
257static const char * const irrx_parents[] = {
258 "clkxtal",
259 "syspll4_d16"
260};
261
262static const char * const crypto_parents[] = {
263 "clkxtal",
264 "univpll_d3",
265 "univpll1_d2",
266 "syspll1_d2",
267 "univpll_d5",
268 "syspll_d5",
269 "univpll2_d2",
270 "syspll_d2"
271};
272
273static const char * const gpt10m_parents[] = {
274 "clkxtal",
275 "clkxtal_d4"
276};
277
278static const char * const peribus_ck_parents[] = {
279 "syspll1_d8",
280 "syspll1_d4"
281};
282
283static const char * const infra_mux1_parents[] = {
284 "clkxtal",
285 "armpll",
286 "main_core_en",
287 "armpll"
288};
289
290static const struct mtk_gate_regs apmixed_cg_regs = {
291 .set_ofs = 0x8,
292 .clr_ofs = 0x8,
293 .sta_ofs = 0x8,
294};
295
296static const struct mtk_gate_regs infra_cg_regs = {
297 .set_ofs = 0x40,
298 .clr_ofs = 0x44,
299 .sta_ofs = 0x48,
300};
301
302static const struct mtk_gate_regs peri0_cg_regs = {
303 .set_ofs = 0x8,
304 .clr_ofs = 0x10,
305 .sta_ofs = 0x18,
306};
307
308static const struct mtk_gate_regs peri1_cg_regs = {
309 .set_ofs = 0xC,
310 .clr_ofs = 0x14,
311 .sta_ofs = 0x1C,
312};
313
314static const struct mtk_pll_data plls[] = {
315 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
316 0, 21, 0x0204, 24, 0, 0x0204, 0),
317 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
318 HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
319 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
320 HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
321 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
322 0, 21, 0x0300, 1, 0, 0x0304, 0),
323 PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0,
324 0, 21, 0x0314, 1, 0, 0x0318, 0),
325 PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
326 0, 21, 0x0358, 1, 0, 0x035C, 0),
327};
328
329static const struct mtk_gate apmixed_clks[] = {
330 GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
331};
332
333static const struct mtk_gate infra_clks[] = {
334 GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "hd_faxi", 0),
335 GATE_INFRA(CLK_INFRA_TRNG_PD, "infra_trng_pd", "hd_faxi", 2),
336 GATE_INFRA(CLK_INFRA_DEVAPC_PD, "infra_devapc_pd", "hd_faxi", 4),
337 GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "infrao_10m", 18),
338 GATE_INFRA(CLK_INFRA_SEJ_PD, "infra_sej_pd", "infrao_10m", 19),
339};
340
341static const struct mtk_fixed_clk top_fixed_clks[] = {
342 FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
343 31250000),
344 FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
345 31250000),
346 FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
347 125000000),
348 FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
349 125000000),
350 FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
351 250000000),
352 FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
353 250000000),
354 FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
355 33333333),
356 FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
357 50000000),
358 FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
359 50000000),
360 FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
361 50000000),
362};
363
364static const struct mtk_fixed_factor top_divs[] = {
365 FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
366 FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
367 FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
368 FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
369 FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
370 FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
371 FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
372 FACTOR(CLK_TOP_PWM_QTR_26M, "pwm_qtr_26m", "clkxtal", 1, 1),
373 FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "cpum_tck", 1, 1),
374 FACTOR(CLK_TOP_TO_USB3_DA_TOP, "to_usb3_da_top", "clkxtal", 1, 1),
375 FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
376 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
377 FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "mempll", 1, 4),
378 FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "mempll", 1, 8),
379 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
380 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
381 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
382 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
383 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32),
384 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6),
385 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
386 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
387 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
388 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
389 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
390 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
391 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
392 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
393 FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
394 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
395 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
396 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
397 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
398 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
399 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
400 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
401 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
402 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
403 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
404 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
405 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
406 FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
407 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
408 FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
409 FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
410 FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
411 FACTOR(CLK_TOP_CLKXTAL_D4, "clkxtal_d4", "clkxtal", 1, 4),
412 FACTOR(CLK_TOP_HD_FAXI, "hd_faxi", "axi_sel", 1, 1),
413 FACTOR(CLK_TOP_FAXI, "faxi", "axi_sel", 1, 1),
414 FACTOR(CLK_TOP_F_FAUD_INTBUS, "f_faud_intbus", "aud_intbus_sel", 1, 1),
415 FACTOR(CLK_TOP_AP2WBHIF_HCLK, "ap2wbhif_hclk", "syspll1_d8", 1, 1),
416 FACTOR(CLK_TOP_10M_INFRAO, "infrao_10m", "gpt10m_sel", 1, 1),
417 FACTOR(CLK_TOP_MSDC30_1, "msdc30_1", "msdc30_1_sel", 1, 1),
418 FACTOR(CLK_TOP_SPI, "spi", "spi0_sel", 1, 1),
419 FACTOR(CLK_TOP_SF, "sf", "nfi_infra_sel", 1, 1),
420 FACTOR(CLK_TOP_FLASH, "flash", "flash_sel", 1, 1),
421 FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "sata_sel", 1, 4),
422 FACTOR(CLK_TOP_TO_USB3_MCU, "to_usb3_mcu", "axi_sel", 1, 1),
423 FACTOR(CLK_TOP_TO_USB3_DMA, "to_usb3_dma", "hif_sel", 1, 1),
424 FACTOR(CLK_TOP_FROM_TOP_AHB, "from_top_ahb", "axi_sel", 1, 1),
425 FACTOR(CLK_TOP_FROM_TOP_AXI, "from_top_axi", "hif_sel", 1, 1),
426 FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "sata_sel", 1, 1),
427 FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "sata_sel", 1, 1),
428};
429
430static const struct mtk_gate peri_clks[] = {
431 /* PERI0 */
432 GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "pwm_qtr_26m", 2),
433 GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "pwm_qtr_26m", 3),
434 GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "pwm_qtr_26m", 4),
435 GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "pwm_qtr_26m", 5),
436 GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "pwm_qtr_26m", 6),
437 GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "pwm_qtr_26m", 7),
438 GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "pwm_qtr_26m", 8),
439 GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "pwm_qtr_26m", 9),
440 GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "faxi", 12),
441 GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1", 14),
442 GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "faxi", 17),
443 GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "faxi", 18),
444 GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "faxi", 19),
445 GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "faxi", 20),
446 GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "faxi", 22),
447 GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "faxi", 23),
448 GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi", 28),
449 GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "sf", 29),
450 GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "faxi", 30),
451 GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "faxi", 31),
452 /* PERI1 */
453 GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash", 1),
454};
455
456static struct mtk_composite infra_muxes[] = {
457 /* INFRA_TOPCKGEN_CKMUXSEL */
458 MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000,
459 2, 2),
460};
461
462static struct mtk_composite top_muxes[] = {
463 /* CLK_CFG_0 */
464 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
465 0x040, 0, 3, 7),
466 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
467 0x040, 8, 1, 15),
468 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
469 0x040, 16, 1, 23),
470 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
471 0x040, 24, 3, 31),
472 /* CLK_CFG_1 */
473 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
474 0x050, 0, 2, 7),
475 MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
476 0x050, 8, 1, 15),
477 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
478 0x050, 16, 4, 23),
479 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
480 0x050, 24, 3, 31),
481 /* CLK_CFG_2 */
482 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
483 0x060, 0, 1, 7),
484 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
485 0x060, 8, 3, 15),
486 MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
487 0x060, 16, 3, 23),
488 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
489 0x060, 24, 3, 31),
490 /* CLK_CFG_3 */
491 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
492 0x070, 0, 3, 7),
493 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
494 0x070, 8, 3, 15),
495 MUX_GATE(CLK_TOP_AP2WBMCU_SEL, "ap2wbmcu_sel", ap2wbmcu_parents,
496 0x070, 16, 3, 23),
497 MUX_GATE(CLK_TOP_AP2WBHIF_SEL, "ap2wbhif_sel", ap2wbmcu_parents,
498 0x070, 24, 3, 31),
499 /* CLK_CFG_4 */
500 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
501 0x080, 0, 2, 7),
502 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
503 0x080, 8, 2, 15),
504 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
505 0x080, 16, 3, 23),
506 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
507 0x080, 24, 2, 31),
508 /* CLK_CFG_5 */
509 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
510 0x090, 0, 2, 7),
511 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", hif_parents,
512 0x090, 8, 3, 15),
513 MUX_GATE(CLK_TOP_SATA_SEL, "sata_sel", sata_parents,
514 0x090, 16, 1, 23),
515 MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
516 0x090, 24, 2, 31),
517 /* CLK_CFG_6 */
518 MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
519 0x0A0, 0, 1, 7),
520 MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud1_parents,
521 0x0A0, 8, 1, 15),
522 MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", irrx_parents,
523 0x0A0, 16, 1, 23),
524 MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", irrx_parents,
525 0x0A0, 24, 1, 31),
526 /* CLK_CFG_7 */
527 MUX_GATE(CLK_TOP_SATA_MCU_SEL, "sata_mcu_sel", scp_parents,
528 0x0B0, 0, 2, 7),
529 MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, "pcie0_mcu_sel", scp_parents,
530 0x0B0, 8, 2, 15),
531 MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, "pcie1_mcu_sel", scp_parents,
532 0x0B0, 16, 2, 23),
533 MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, "ssusb_mcu_sel", scp_parents,
534 0x0B0, 24, 2, 31),
535 /* CLK_CFG_8 */
536 MUX_GATE(CLK_TOP_CRYPTO_SEL, "crypto_sel", crypto_parents,
537 0x0C0, 0, 3, 7),
538 MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, "sgmii_ref_1_sel", f10m_ref_parents,
539 0x0C0, 8, 1, 15),
540 MUX_GATE(CLK_TOP_10M_SEL, "gpt10m_sel", gpt10m_parents,
541 0x0C0, 16, 1, 23),
542};
543
544static struct mtk_composite peri_muxes[] = {
545 /* PERI_GLOBALCON_CKSEL */
546 MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
547};
548
549static int mtk_topckgen_init(struct platform_device *pdev)
550{
551 struct clk_hw_onecell_data *clk_data;
552 void __iomem *base;
553 struct device_node *node = pdev->dev.of_node;
554
555 base = devm_platform_ioremap_resource(pdev, 0);
556 if (IS_ERR(base))
557 return PTR_ERR(base);
558
559 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
560
561 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
562 clk_data);
563
564 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
565 clk_data);
566
567 mtk_clk_register_composites(&pdev->dev, top_muxes,
568 ARRAY_SIZE(top_muxes), base,
569 &mt7629_clk_lock, clk_data);
570
571 clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
572 clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
573 clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
574
575 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
576}
577
578static int mtk_infrasys_init(struct platform_device *pdev)
579{
580 struct device_node *node = pdev->dev.of_node;
581 struct clk_hw_onecell_data *clk_data;
582
583 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
584
585 mtk_clk_register_gates(&pdev->dev, node, infra_clks,
586 ARRAY_SIZE(infra_clks), clk_data);
587
588 mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
589 ARRAY_SIZE(infra_muxes), clk_data);
590
591 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
592 clk_data);
593}
594
595static int mtk_pericfg_init(struct platform_device *pdev)
596{
597 struct clk_hw_onecell_data *clk_data;
598 void __iomem *base;
599 int r;
600 struct device_node *node = pdev->dev.of_node;
601
602 base = devm_platform_ioremap_resource(pdev, 0);
603 if (IS_ERR(base))
604 return PTR_ERR(base);
605
606 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
607
608 mtk_clk_register_gates(&pdev->dev, node, peri_clks,
609 ARRAY_SIZE(peri_clks), clk_data);
610
611 mtk_clk_register_composites(&pdev->dev, peri_muxes,
612 ARRAY_SIZE(peri_muxes), base,
613 &mt7629_clk_lock, clk_data);
614
615 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
616 if (r)
617 return r;
618
619 clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
620
621 return 0;
622}
623
624static int mtk_apmixedsys_init(struct platform_device *pdev)
625{
626 struct clk_hw_onecell_data *clk_data;
627 struct device_node *node = pdev->dev.of_node;
628
629 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
630 if (!clk_data)
631 return -ENOMEM;
632
633 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
634 clk_data);
635
636 mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
637 ARRAY_SIZE(apmixed_clks), clk_data);
638
639 clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
640 clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk);
641
642 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
643}
644
645
646static const struct of_device_id of_match_clk_mt7629[] = {
647 {
648 .compatible = "mediatek,mt7629-apmixedsys",
649 .data = mtk_apmixedsys_init,
650 }, {
651 .compatible = "mediatek,mt7629-infracfg",
652 .data = mtk_infrasys_init,
653 }, {
654 .compatible = "mediatek,mt7629-topckgen",
655 .data = mtk_topckgen_init,
656 }, {
657 .compatible = "mediatek,mt7629-pericfg",
658 .data = mtk_pericfg_init,
659 }, {
660 /* sentinel */
661 }
662};
663MODULE_DEVICE_TABLE(of, of_match_clk_mt7629);
664
665static int clk_mt7629_probe(struct platform_device *pdev)
666{
667 int (*clk_init)(struct platform_device *);
668 int r;
669
670 clk_init = of_device_get_match_data(&pdev->dev);
671 if (!clk_init)
672 return -EINVAL;
673
674 r = clk_init(pdev);
675 if (r)
676 dev_err(&pdev->dev,
677 "could not register clock provider: %s: %d\n",
678 pdev->name, r);
679
680 return r;
681}
682
683static struct platform_driver clk_mt7629_drv = {
684 .probe = clk_mt7629_probe,
685 .driver = {
686 .name = "clk-mt7629",
687 .of_match_table = of_match_clk_mt7629,
688 },
689};
690
691static int clk_mt7629_init(void)
692{
693 return platform_driver_register(&clk_mt7629_drv);
694}
695
696arch_initcall(clk_mt7629_init);
697MODULE_LICENSE("GPL");