tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6 */
7
8#include <linux/clk-provider.h>
9#include <linux/of.h>
10#include <linux/of_address.h>
11#include <linux/of_device.h>
12#include <linux/platform_device.h>
13
14#include "clk-mtk.h"
15#include "clk-gate.h"
16
17#include <dt-bindings/clock/mt7986-clk.h>
18
19static const struct mtk_gate_regs sgmii0_cg_regs = {
20 .set_ofs = 0xe4,
21 .clr_ofs = 0xe4,
22 .sta_ofs = 0xe4,
23};
24
25#define GATE_SGMII0(_id, _name, _parent, _shift) \
26 GATE_MTK(_id, _name, _parent, &sgmii0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
27
28static const struct mtk_gate sgmii0_clks[] = {
29 GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2),
30 GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3),
31 GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4),
32 GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5),
33};
34
35static const struct mtk_gate_regs sgmii1_cg_regs = {
36 .set_ofs = 0xe4,
37 .clr_ofs = 0xe4,
38 .sta_ofs = 0xe4,
39};
40
41#define GATE_SGMII1(_id, _name, _parent, _shift) \
42 GATE_MTK(_id, _name, _parent, &sgmii1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
43
44static const struct mtk_gate sgmii1_clks[] = {
45 GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2),
46 GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3),
47 GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4),
48 GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5),
49};
50
51static const struct mtk_gate_regs eth_cg_regs = {
52 .set_ofs = 0x30,
53 .clr_ofs = 0x30,
54 .sta_ofs = 0x30,
55};
56
57#define GATE_ETH(_id, _name, _parent, _shift) \
58 GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
59
60static const struct mtk_gate eth_clks[] = {
61 GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6),
62 GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7),
63 GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8),
64 GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14),
65 GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15),
66};
67
68static const struct mtk_clk_desc eth_desc = {
69 .clks = eth_clks,
70 .num_clks = ARRAY_SIZE(eth_clks),
71};
72
73static const struct mtk_clk_desc sgmii0_desc = {
74 .clks = sgmii0_clks,
75 .num_clks = ARRAY_SIZE(sgmii0_clks),
76};
77
78static const struct mtk_clk_desc sgmii1_desc = {
79 .clks = sgmii1_clks,
80 .num_clks = ARRAY_SIZE(sgmii1_clks),
81};
82
83static const struct of_device_id of_match_clk_mt7986_eth[] = {
84 { .compatible = "mediatek,mt7986-ethsys", .data = ð_desc },
85 { .compatible = "mediatek,mt7986-sgmiisys_0", .data = &sgmii0_desc },
86 { .compatible = "mediatek,mt7986-sgmiisys_1", .data = &sgmii1_desc },
87 { /* sentinel */ }
88};
89MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_eth);
90
91static struct platform_driver clk_mt7986_eth_drv = {
92 .driver = {
93 .name = "clk-mt7986-eth",
94 .of_match_table = of_match_clk_mt7986_eth,
95 },
96 .probe = mtk_clk_simple_probe,
97 .remove = mtk_clk_simple_remove,
98};
99module_platform_driver(clk_mt7986_eth_drv);
100
101MODULE_DESCRIPTION("MediaTek MT7986 Ethernet clocks driver");
102MODULE_LICENSE("GPL");