tjh.dev
Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Broadcom Ltd.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8
9/ {
10 compatible = "brcm,bcm6878", "brcm,bcmbca";
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 interrupt-parent = <&gic>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 CA7_0: cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a7";
23 reg = <0x0>;
24 next-level-cache = <&L2_0>;
25 enable-method = "psci";
26 };
27
28 CA7_1: cpu@1 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a7";
31 reg = <0x1>;
32 next-level-cache = <&L2_0>;
33 enable-method = "psci";
34 };
35
36 L2_0: l2-cache0 {
37 compatible = "cache";
38 cache-level = <2>;
39 };
40 };
41
42 timer {
43 compatible = "arm,armv7-timer";
44 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
45 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
46 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
47 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
48 arm,cpu-registers-not-fw-configured;
49 };
50
51 pmu: pmu {
52 compatible = "arm,cortex-a7-pmu";
53 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
54 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
55 interrupt-affinity = <&CA7_0>, <&CA7_1>;
56 };
57
58 clocks: clocks {
59 periph_clk: periph-clk {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <200000000>;
63 };
64
65 uart_clk: uart-clk {
66 compatible = "fixed-factor-clock";
67 #clock-cells = <0>;
68 clocks = <&periph_clk>;
69 clock-div = <4>;
70 clock-mult = <1>;
71 };
72
73 hsspi_pll: hsspi-pll {
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <200000000>;
77 };
78 };
79
80 psci {
81 compatible = "arm,psci-0.2";
82 method = "smc";
83 };
84
85 axi@81000000 {
86 compatible = "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges = <0 0x81000000 0x8000>;
90
91 gic: interrupt-controller@1000 {
92 compatible = "arm,cortex-a7-gic";
93 #interrupt-cells = <3>;
94 interrupt-controller;
95 reg = <0x1000 0x1000>,
96 <0x2000 0x2000>,
97 <0x4000 0x2000>,
98 <0x6000 0x2000>;
99 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
100 IRQ_TYPE_LEVEL_HIGH)>;
101 };
102 };
103
104 bus@ff800000 {
105 compatible = "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 ranges = <0 0xff800000 0x800000>;
109
110 hsspi: spi@1000 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 compatible = "brcm,bcm6878-hsspi", "brcm,bcmbca-hsspi-v1.0";
114 reg = <0x1000 0x600>;
115 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&hsspi_pll &hsspi_pll>;
117 clock-names = "hsspi", "pll";
118 num-cs = <8>;
119 status = "disabled";
120 };
121
122 uart0: serial@12000 {
123 compatible = "arm,pl011", "arm,primecell";
124 reg = <0x12000 0x1000>;
125 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&uart_clk>, <&uart_clk>;
127 clock-names = "uartclk", "apb_pclk";
128 status = "disabled";
129 };
130 };
131};