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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA core driver
5 *
6 * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
7 */
8
9#ifndef _DW_EDMA_H
10#define _DW_EDMA_H
11
12#include <linux/device.h>
13#include <linux/dmaengine.h>
14
15#define EDMA_MAX_WR_CH 8
16#define EDMA_MAX_RD_CH 8
17
18struct dw_edma;
19
20struct dw_edma_region {
21 u64 paddr;
22 union {
23 void *mem;
24 void __iomem *io;
25 } vaddr;
26 size_t sz;
27};
28
29/**
30 * struct dw_edma_core_ops - platform-specific eDMA methods
31 * @irq_vector: Get IRQ number of the passed eDMA channel. Note the
32 * method accepts the channel id in the end-to-end
33 * numbering with the eDMA write channels being placed
34 * first in the row.
35 * @pci_address: Get PCIe bus address corresponding to the passed CPU
36 * address. Note there is no need in specifying this
37 * function if the address translation is performed by
38 * the DW PCIe RP/EP controller with the DW eDMA device in
39 * subject and DMA_BYPASS isn't set for all the outbound
40 * iATU windows. That will be done by the controller
41 * automatically.
42 */
43struct dw_edma_core_ops {
44 int (*irq_vector)(struct device *dev, unsigned int nr);
45 u64 (*pci_address)(struct device *dev, phys_addr_t cpu_addr);
46};
47
48enum dw_edma_map_format {
49 EDMA_MF_EDMA_LEGACY = 0x0,
50 EDMA_MF_EDMA_UNROLL = 0x1,
51 EDMA_MF_HDMA_COMPAT = 0x5
52};
53
54/**
55 * enum dw_edma_chip_flags - Flags specific to an eDMA chip
56 * @DW_EDMA_CHIP_LOCAL: eDMA is used locally by an endpoint
57 */
58enum dw_edma_chip_flags {
59 DW_EDMA_CHIP_LOCAL = BIT(0),
60};
61
62/**
63 * struct dw_edma_chip - representation of DesignWare eDMA controller hardware
64 * @dev: struct device of the eDMA controller
65 * @id: instance ID
66 * @nr_irqs: total number of DMA IRQs
67 * @ops DMA channel to IRQ number mapping
68 * @flags dw_edma_chip_flags
69 * @reg_base DMA register base address
70 * @ll_wr_cnt DMA write link list count
71 * @ll_rd_cnt DMA read link list count
72 * @rg_region DMA register region
73 * @ll_region_wr DMA descriptor link list memory for write channel
74 * @ll_region_rd DMA descriptor link list memory for read channel
75 * @dt_region_wr DMA data memory for write channel
76 * @dt_region_rd DMA data memory for read channel
77 * @mf DMA register map format
78 * @dw: struct dw_edma that is filled by dw_edma_probe()
79 */
80struct dw_edma_chip {
81 struct device *dev;
82 int nr_irqs;
83 const struct dw_edma_core_ops *ops;
84 u32 flags;
85
86 void __iomem *reg_base;
87
88 u16 ll_wr_cnt;
89 u16 ll_rd_cnt;
90 /* link list address */
91 struct dw_edma_region ll_region_wr[EDMA_MAX_WR_CH];
92 struct dw_edma_region ll_region_rd[EDMA_MAX_RD_CH];
93
94 /* data region */
95 struct dw_edma_region dt_region_wr[EDMA_MAX_WR_CH];
96 struct dw_edma_region dt_region_rd[EDMA_MAX_RD_CH];
97
98 enum dw_edma_map_format mf;
99
100 struct dw_edma *dw;
101};
102
103/* Export to the platform drivers */
104#if IS_REACHABLE(CONFIG_DW_EDMA)
105int dw_edma_probe(struct dw_edma_chip *chip);
106int dw_edma_remove(struct dw_edma_chip *chip);
107#else
108static inline int dw_edma_probe(struct dw_edma_chip *chip)
109{
110 return -ENODEV;
111}
112
113static inline int dw_edma_remove(struct dw_edma_chip *chip)
114{
115 return 0;
116}
117#endif /* CONFIG_DW_EDMA */
118
119#endif /* _DW_EDMA_H */