tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 *
5 */
6
7#include <linux/device.h>
8#include <linux/interconnect.h>
9#include <linux/interconnect-provider.h>
10#include <linux/module.h>
11#include <linux/of_platform.h>
12#include <dt-bindings/interconnect/qcom,sm8150.h>
13
14#include "bcm-voter.h"
15#include "icc-rpmh.h"
16#include "sm8150.h"
17
18DEFINE_QNODE(qhm_a1noc_cfg, SM8150_MASTER_A1NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A1NOC);
19DEFINE_QNODE(qhm_qup0, SM8150_MASTER_QUP_0, 1, 4, SM8150_A1NOC_SNOC_SLV);
20DEFINE_QNODE(xm_emac, SM8150_MASTER_EMAC, 1, 8, SM8150_A1NOC_SNOC_SLV);
21DEFINE_QNODE(xm_ufs_mem, SM8150_MASTER_UFS_MEM, 1, 8, SM8150_A1NOC_SNOC_SLV);
22DEFINE_QNODE(xm_usb3_0, SM8150_MASTER_USB3, 1, 8, SM8150_A1NOC_SNOC_SLV);
23DEFINE_QNODE(xm_usb3_1, SM8150_MASTER_USB3_1, 1, 8, SM8150_A1NOC_SNOC_SLV);
24DEFINE_QNODE(qhm_a2noc_cfg, SM8150_MASTER_A2NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A2NOC);
25DEFINE_QNODE(qhm_qdss_bam, SM8150_MASTER_QDSS_BAM, 1, 4, SM8150_A2NOC_SNOC_SLV);
26DEFINE_QNODE(qhm_qspi, SM8150_MASTER_QSPI, 1, 4, SM8150_A2NOC_SNOC_SLV);
27DEFINE_QNODE(qhm_qup1, SM8150_MASTER_QUP_1, 1, 4, SM8150_A2NOC_SNOC_SLV);
28DEFINE_QNODE(qhm_qup2, SM8150_MASTER_QUP_2, 1, 4, SM8150_A2NOC_SNOC_SLV);
29DEFINE_QNODE(qhm_sensorss_ahb, SM8150_MASTER_SENSORS_AHB, 1, 4, SM8150_A2NOC_SNOC_SLV);
30DEFINE_QNODE(qhm_tsif, SM8150_MASTER_TSIF, 1, 4, SM8150_A2NOC_SNOC_SLV);
31DEFINE_QNODE(qnm_cnoc, SM8150_MASTER_CNOC_A2NOC, 1, 8, SM8150_A2NOC_SNOC_SLV);
32DEFINE_QNODE(qxm_crypto, SM8150_MASTER_CRYPTO_CORE_0, 1, 8, SM8150_A2NOC_SNOC_SLV);
33DEFINE_QNODE(qxm_ipa, SM8150_MASTER_IPA, 1, 8, SM8150_A2NOC_SNOC_SLV);
34DEFINE_QNODE(xm_pcie3_0, SM8150_MASTER_PCIE, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
35DEFINE_QNODE(xm_pcie3_1, SM8150_MASTER_PCIE_1, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
36DEFINE_QNODE(xm_qdss_etr, SM8150_MASTER_QDSS_ETR, 1, 8, SM8150_A2NOC_SNOC_SLV);
37DEFINE_QNODE(xm_sdc2, SM8150_MASTER_SDCC_2, 1, 8, SM8150_A2NOC_SNOC_SLV);
38DEFINE_QNODE(xm_sdc4, SM8150_MASTER_SDCC_4, 1, 8, SM8150_A2NOC_SNOC_SLV);
39DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM8150_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
40DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SM8150_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
41DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM8150_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
42DEFINE_QNODE(qnm_npu, SM8150_MASTER_NPU, 1, 32, SM8150_SLAVE_CDSP_MEM_NOC);
43DEFINE_QNODE(qhm_spdm, SM8150_MASTER_SPDM, 1, 4, SM8150_SLAVE_CNOC_A2NOC);
44DEFINE_QNODE(qnm_snoc, SM8150_SNOC_CNOC_MAS, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
45DEFINE_QNODE(xm_qdss_dap, SM8150_MASTER_QDSS_DAP, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_CNOC_A2NOC, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
46DEFINE_QNODE(qhm_cnoc_dc_noc, SM8150_MASTER_CNOC_DC_NOC, 1, 4, SM8150_SLAVE_GEM_NOC_CFG, SM8150_SLAVE_LLCC_CFG);
47DEFINE_QNODE(acm_apps, SM8150_MASTER_AMPSS_M0, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
48DEFINE_QNODE(acm_gpu_tcu, SM8150_MASTER_GPU_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
49DEFINE_QNODE(acm_sys_tcu, SM8150_MASTER_SYS_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
50DEFINE_QNODE(qhm_gemnoc_cfg, SM8150_MASTER_GEM_NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_GEM_NOC, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG);
51DEFINE_QNODE(qnm_cmpnoc, SM8150_MASTER_COMPUTE_NOC, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
52DEFINE_QNODE(qnm_gpu, SM8150_MASTER_GRAPHICS_3D, 2, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
53DEFINE_QNODE(qnm_mnoc_hf, SM8150_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8150_SLAVE_LLCC);
54DEFINE_QNODE(qnm_mnoc_sf, SM8150_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
55DEFINE_QNODE(qnm_pcie, SM8150_MASTER_GEM_NOC_PCIE_SNOC, 1, 16, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
56DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAVE_LLCC);
57DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLAVE_LLCC);
58DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC);
59DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0);
60DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_MNOC);
61DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
62DEFINE_QNODE(qxm_camnoc_hf1, SM8150_MASTER_CAMNOC_HF1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
63DEFINE_QNODE(qxm_camnoc_sf, SM8150_MASTER_CAMNOC_SF, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
64DEFINE_QNODE(qxm_mdp0, SM8150_MASTER_MDP_PORT0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
65DEFINE_QNODE(qxm_mdp1, SM8150_MASTER_MDP_PORT1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
66DEFINE_QNODE(qxm_rot, SM8150_MASTER_ROTATOR, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
67DEFINE_QNODE(qxm_venus0, SM8150_MASTER_VIDEO_P0, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
68DEFINE_QNODE(qxm_venus1, SM8150_MASTER_VIDEO_P1, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
69DEFINE_QNODE(qxm_venus_arm9, SM8150_MASTER_VIDEO_PROC, 1, 8, SM8150_SLAVE_MNOC_SF_MEM_NOC);
70DEFINE_QNODE(qhm_snoc_cfg, SM8150_MASTER_SNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_SNOC);
71DEFINE_QNODE(qnm_aggre1_noc, SM8150_A1NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_QDSS_STM);
72DEFINE_QNODE(qnm_aggre2_noc, SM8150_A2NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_PCIE_0, SM8150_SLAVE_PCIE_1, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
73DEFINE_QNODE(qnm_gemnoc, SM8150_MASTER_GEM_NOC_SNOC, 1, 8, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
74DEFINE_QNODE(qxm_pimem, SM8150_MASTER_PIMEM, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
75DEFINE_QNODE(xm_gic, SM8150_MASTER_GIC, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
76DEFINE_QNODE(qns_a1noc_snoc, SM8150_A1NOC_SNOC_SLV, 1, 16, SM8150_A1NOC_SNOC_MAS);
77DEFINE_QNODE(srvc_aggre1_noc, SM8150_SLAVE_SERVICE_A1NOC, 1, 4);
78DEFINE_QNODE(qns_a2noc_snoc, SM8150_A2NOC_SNOC_SLV, 1, 16, SM8150_A2NOC_SNOC_MAS);
79DEFINE_QNODE(qns_pcie_mem_noc, SM8150_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8150_MASTER_GEM_NOC_PCIE_SNOC);
80DEFINE_QNODE(srvc_aggre2_noc, SM8150_SLAVE_SERVICE_A2NOC, 1, 4);
81DEFINE_QNODE(qns_camnoc_uncomp, SM8150_SLAVE_CAMNOC_UNCOMP, 1, 32);
82DEFINE_QNODE(qns_cdsp_mem_noc, SM8150_SLAVE_CDSP_MEM_NOC, 2, 32, SM8150_MASTER_COMPUTE_NOC);
83DEFINE_QNODE(qhs_a1_noc_cfg, SM8150_SLAVE_A1NOC_CFG, 1, 4, SM8150_MASTER_A1NOC_CFG);
84DEFINE_QNODE(qhs_a2_noc_cfg, SM8150_SLAVE_A2NOC_CFG, 1, 4, SM8150_MASTER_A2NOC_CFG);
85DEFINE_QNODE(qhs_ahb2phy_south, SM8150_SLAVE_AHB2PHY_SOUTH, 1, 4);
86DEFINE_QNODE(qhs_aop, SM8150_SLAVE_AOP, 1, 4);
87DEFINE_QNODE(qhs_aoss, SM8150_SLAVE_AOSS, 1, 4);
88DEFINE_QNODE(qhs_camera_cfg, SM8150_SLAVE_CAMERA_CFG, 1, 4);
89DEFINE_QNODE(qhs_clk_ctl, SM8150_SLAVE_CLK_CTL, 1, 4);
90DEFINE_QNODE(qhs_compute_dsp, SM8150_SLAVE_CDSP_CFG, 1, 4);
91DEFINE_QNODE(qhs_cpr_cx, SM8150_SLAVE_RBCPR_CX_CFG, 1, 4);
92DEFINE_QNODE(qhs_cpr_mmcx, SM8150_SLAVE_RBCPR_MMCX_CFG, 1, 4);
93DEFINE_QNODE(qhs_cpr_mx, SM8150_SLAVE_RBCPR_MX_CFG, 1, 4);
94DEFINE_QNODE(qhs_crypto0_cfg, SM8150_SLAVE_CRYPTO_0_CFG, 1, 4);
95DEFINE_QNODE(qhs_ddrss_cfg, SM8150_SLAVE_CNOC_DDRSS, 1, 4, SM8150_MASTER_CNOC_DC_NOC);
96DEFINE_QNODE(qhs_display_cfg, SM8150_SLAVE_DISPLAY_CFG, 1, 4);
97DEFINE_QNODE(qhs_emac_cfg, SM8150_SLAVE_EMAC_CFG, 1, 4);
98DEFINE_QNODE(qhs_glm, SM8150_SLAVE_GLM, 1, 4);
99DEFINE_QNODE(qhs_gpuss_cfg, SM8150_SLAVE_GRAPHICS_3D_CFG, 1, 8);
100DEFINE_QNODE(qhs_imem_cfg, SM8150_SLAVE_IMEM_CFG, 1, 4);
101DEFINE_QNODE(qhs_ipa, SM8150_SLAVE_IPA_CFG, 1, 4);
102DEFINE_QNODE(qhs_mnoc_cfg, SM8150_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8150_MASTER_CNOC_MNOC_CFG);
103DEFINE_QNODE(qhs_npu_cfg, SM8150_SLAVE_NPU_CFG, 1, 4);
104DEFINE_QNODE(qhs_pcie0_cfg, SM8150_SLAVE_PCIE_0_CFG, 1, 4);
105DEFINE_QNODE(qhs_pcie1_cfg, SM8150_SLAVE_PCIE_1_CFG, 1, 4);
106DEFINE_QNODE(qhs_phy_refgen_north, SM8150_SLAVE_NORTH_PHY_CFG, 1, 4);
107DEFINE_QNODE(qhs_pimem_cfg, SM8150_SLAVE_PIMEM_CFG, 1, 4);
108DEFINE_QNODE(qhs_prng, SM8150_SLAVE_PRNG, 1, 4);
109DEFINE_QNODE(qhs_qdss_cfg, SM8150_SLAVE_QDSS_CFG, 1, 4);
110DEFINE_QNODE(qhs_qspi, SM8150_SLAVE_QSPI, 1, 4);
111DEFINE_QNODE(qhs_qupv3_east, SM8150_SLAVE_QUP_2, 1, 4);
112DEFINE_QNODE(qhs_qupv3_north, SM8150_SLAVE_QUP_1, 1, 4);
113DEFINE_QNODE(qhs_qupv3_south, SM8150_SLAVE_QUP_0, 1, 4);
114DEFINE_QNODE(qhs_sdc2, SM8150_SLAVE_SDCC_2, 1, 4);
115DEFINE_QNODE(qhs_sdc4, SM8150_SLAVE_SDCC_4, 1, 4);
116DEFINE_QNODE(qhs_snoc_cfg, SM8150_SLAVE_SNOC_CFG, 1, 4, SM8150_MASTER_SNOC_CFG);
117DEFINE_QNODE(qhs_spdm, SM8150_SLAVE_SPDM_WRAPPER, 1, 4);
118DEFINE_QNODE(qhs_spss_cfg, SM8150_SLAVE_SPSS_CFG, 1, 4);
119DEFINE_QNODE(qhs_ssc_cfg, SM8150_SLAVE_SSC_CFG, 1, 4);
120DEFINE_QNODE(qhs_tcsr, SM8150_SLAVE_TCSR, 1, 4);
121DEFINE_QNODE(qhs_tlmm_east, SM8150_SLAVE_TLMM_EAST, 1, 4);
122DEFINE_QNODE(qhs_tlmm_north, SM8150_SLAVE_TLMM_NORTH, 1, 4);
123DEFINE_QNODE(qhs_tlmm_south, SM8150_SLAVE_TLMM_SOUTH, 1, 4);
124DEFINE_QNODE(qhs_tlmm_west, SM8150_SLAVE_TLMM_WEST, 1, 4);
125DEFINE_QNODE(qhs_tsif, SM8150_SLAVE_TSIF, 1, 4);
126DEFINE_QNODE(qhs_ufs_card_cfg, SM8150_SLAVE_UFS_CARD_CFG, 1, 4);
127DEFINE_QNODE(qhs_ufs_mem_cfg, SM8150_SLAVE_UFS_MEM_CFG, 1, 4);
128DEFINE_QNODE(qhs_usb3_0, SM8150_SLAVE_USB3, 1, 4);
129DEFINE_QNODE(qhs_usb3_1, SM8150_SLAVE_USB3_1, 1, 4);
130DEFINE_QNODE(qhs_venus_cfg, SM8150_SLAVE_VENUS_CFG, 1, 4);
131DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8150_SLAVE_VSENSE_CTRL_CFG, 1, 4);
132DEFINE_QNODE(qns_cnoc_a2noc, SM8150_SLAVE_CNOC_A2NOC, 1, 8, SM8150_MASTER_CNOC_A2NOC);
133DEFINE_QNODE(srvc_cnoc, SM8150_SLAVE_SERVICE_CNOC, 1, 4);
134DEFINE_QNODE(qhs_llcc, SM8150_SLAVE_LLCC_CFG, 1, 4);
135DEFINE_QNODE(qhs_memnoc, SM8150_SLAVE_GEM_NOC_CFG, 1, 4, SM8150_MASTER_GEM_NOC_CFG);
136DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
137DEFINE_QNODE(qns_ecc, SM8150_SLAVE_ECC, 1, 32);
138DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MASTER_GEM_NOC_SNOC);
139DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC);
140DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4);
141DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4);
142DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MASTER_MNOC_SF_MEM_NOC);
143DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_MASTER_MNOC_HF_MEM_NOC);
144DEFINE_QNODE(srvc_mnoc, SM8150_SLAVE_SERVICE_MNOC, 1, 4);
145DEFINE_QNODE(qhs_apss, SM8150_SLAVE_APPSS, 1, 8);
146DEFINE_QNODE(qns_cnoc, SM8150_SNOC_CNOC_SLV, 1, 8, SM8150_SNOC_CNOC_MAS);
147DEFINE_QNODE(qns_gemnoc_gc, SM8150_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8150_MASTER_SNOC_GC_MEM_NOC);
148DEFINE_QNODE(qns_gemnoc_sf, SM8150_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8150_MASTER_SNOC_SF_MEM_NOC);
149DEFINE_QNODE(qxs_imem, SM8150_SLAVE_OCIMEM, 1, 8);
150DEFINE_QNODE(qxs_pimem, SM8150_SLAVE_PIMEM, 1, 8);
151DEFINE_QNODE(srvc_snoc, SM8150_SLAVE_SERVICE_SNOC, 1, 4);
152DEFINE_QNODE(xs_pcie_0, SM8150_SLAVE_PCIE_0, 1, 8);
153DEFINE_QNODE(xs_pcie_1, SM8150_SLAVE_PCIE_1, 1, 8);
154DEFINE_QNODE(xs_qdss_stm, SM8150_SLAVE_QDSS_STM, 1, 4);
155DEFINE_QNODE(xs_sys_tcu_cfg, SM8150_SLAVE_TCU, 1, 8);
156
157DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
158DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
159DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
160DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
161DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
162DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_gem_noc_snoc);
163DEFINE_QBCM(bcm_mm2, "MM2", false, &qxm_camnoc_sf, &qns2_mem_noc);
164DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_gpu_tcu, &acm_sys_tcu);
165DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
166DEFINE_QBCM(bcm_sh4, "SH4", false, &qnm_cmpnoc);
167DEFINE_QBCM(bcm_sh5, "SH5", false, &acm_apps);
168DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
169DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
170DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
171DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
172DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu);
173DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy_south, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emac_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_phy_refgen_north, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qupv3_east, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_ssc_cfg, &qhs_tcsr, &qhs_tlmm_east, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tlmm_west, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
174DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2);
175DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
176DEFINE_QBCM(bcm_sn3, "SN3", false, &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc);
177DEFINE_QBCM(bcm_sn4, "SN4", false, &qxs_pimem);
178DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
179DEFINE_QBCM(bcm_sn8, "SN8", false, &xs_pcie_0, &xs_pcie_1);
180DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre1_noc);
181DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_aggre2_noc);
182DEFINE_QBCM(bcm_sn12, "SN12", false, &qxm_pimem, &xm_gic);
183DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc);
184DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_gemnoc);
185
186static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
187 &bcm_qup0,
188 &bcm_sn3,
189};
190
191static struct qcom_icc_node * const aggre1_noc_nodes[] = {
192 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
193 [MASTER_QUP_0] = &qhm_qup0,
194 [MASTER_EMAC] = &xm_emac,
195 [MASTER_UFS_MEM] = &xm_ufs_mem,
196 [MASTER_USB3] = &xm_usb3_0,
197 [MASTER_USB3_1] = &xm_usb3_1,
198 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
199 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
200};
201
202static const struct qcom_icc_desc sm8150_aggre1_noc = {
203 .nodes = aggre1_noc_nodes,
204 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
205 .bcms = aggre1_noc_bcms,
206 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
207};
208
209static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
210 &bcm_ce0,
211 &bcm_qup0,
212 &bcm_sn14,
213 &bcm_sn3,
214};
215
216static struct qcom_icc_node * const aggre2_noc_nodes[] = {
217 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
218 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
219 [MASTER_QSPI] = &qhm_qspi,
220 [MASTER_QUP_1] = &qhm_qup1,
221 [MASTER_QUP_2] = &qhm_qup2,
222 [MASTER_SENSORS_AHB] = &qhm_sensorss_ahb,
223 [MASTER_TSIF] = &qhm_tsif,
224 [MASTER_CNOC_A2NOC] = &qnm_cnoc,
225 [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
226 [MASTER_IPA] = &qxm_ipa,
227 [MASTER_PCIE] = &xm_pcie3_0,
228 [MASTER_PCIE_1] = &xm_pcie3_1,
229 [MASTER_QDSS_ETR] = &xm_qdss_etr,
230 [MASTER_SDCC_2] = &xm_sdc2,
231 [MASTER_SDCC_4] = &xm_sdc4,
232 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
233 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
234 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
235};
236
237static const struct qcom_icc_desc sm8150_aggre2_noc = {
238 .nodes = aggre2_noc_nodes,
239 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
240 .bcms = aggre2_noc_bcms,
241 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
242};
243
244static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
245 &bcm_mm1,
246};
247
248static struct qcom_icc_node * const camnoc_virt_nodes[] = {
249 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
250 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
251 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
252 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
253};
254
255static const struct qcom_icc_desc sm8150_camnoc_virt = {
256 .nodes = camnoc_virt_nodes,
257 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
258 .bcms = camnoc_virt_bcms,
259 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
260};
261
262static struct qcom_icc_bcm * const compute_noc_bcms[] = {
263 &bcm_co0,
264 &bcm_co1,
265};
266
267static struct qcom_icc_node * const compute_noc_nodes[] = {
268 [MASTER_NPU] = &qnm_npu,
269 [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc,
270};
271
272static const struct qcom_icc_desc sm8150_compute_noc = {
273 .nodes = compute_noc_nodes,
274 .num_nodes = ARRAY_SIZE(compute_noc_nodes),
275 .bcms = compute_noc_bcms,
276 .num_bcms = ARRAY_SIZE(compute_noc_bcms),
277};
278
279static struct qcom_icc_bcm * const config_noc_bcms[] = {
280 &bcm_cn0,
281};
282
283static struct qcom_icc_node * const config_noc_nodes[] = {
284 [MASTER_SPDM] = &qhm_spdm,
285 [SNOC_CNOC_MAS] = &qnm_snoc,
286 [MASTER_QDSS_DAP] = &xm_qdss_dap,
287 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
288 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
289 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy_south,
290 [SLAVE_AOP] = &qhs_aop,
291 [SLAVE_AOSS] = &qhs_aoss,
292 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
293 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
294 [SLAVE_CDSP_CFG] = &qhs_compute_dsp,
295 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
296 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
297 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
298 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
299 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
300 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
301 [SLAVE_EMAC_CFG] = &qhs_emac_cfg,
302 [SLAVE_GLM] = &qhs_glm,
303 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
304 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
305 [SLAVE_IPA_CFG] = &qhs_ipa,
306 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
307 [SLAVE_NPU_CFG] = &qhs_npu_cfg,
308 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
309 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
310 [SLAVE_NORTH_PHY_CFG] = &qhs_phy_refgen_north,
311 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
312 [SLAVE_PRNG] = &qhs_prng,
313 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
314 [SLAVE_QSPI] = &qhs_qspi,
315 [SLAVE_QUP_2] = &qhs_qupv3_east,
316 [SLAVE_QUP_1] = &qhs_qupv3_north,
317 [SLAVE_QUP_0] = &qhs_qupv3_south,
318 [SLAVE_SDCC_2] = &qhs_sdc2,
319 [SLAVE_SDCC_4] = &qhs_sdc4,
320 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
321 [SLAVE_SPDM_WRAPPER] = &qhs_spdm,
322 [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
323 [SLAVE_SSC_CFG] = &qhs_ssc_cfg,
324 [SLAVE_TCSR] = &qhs_tcsr,
325 [SLAVE_TLMM_EAST] = &qhs_tlmm_east,
326 [SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
327 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
328 [SLAVE_TLMM_WEST] = &qhs_tlmm_west,
329 [SLAVE_TSIF] = &qhs_tsif,
330 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
331 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
332 [SLAVE_USB3] = &qhs_usb3_0,
333 [SLAVE_USB3_1] = &qhs_usb3_1,
334 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
335 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
336 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
337 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
338};
339
340static const struct qcom_icc_desc sm8150_config_noc = {
341 .nodes = config_noc_nodes,
342 .num_nodes = ARRAY_SIZE(config_noc_nodes),
343 .bcms = config_noc_bcms,
344 .num_bcms = ARRAY_SIZE(config_noc_bcms),
345};
346
347static struct qcom_icc_bcm * const dc_noc_bcms[] = {
348};
349
350static struct qcom_icc_node * const dc_noc_nodes[] = {
351 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
352 [SLAVE_LLCC_CFG] = &qhs_llcc,
353 [SLAVE_GEM_NOC_CFG] = &qhs_memnoc,
354};
355
356static const struct qcom_icc_desc sm8150_dc_noc = {
357 .nodes = dc_noc_nodes,
358 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
359 .bcms = dc_noc_bcms,
360 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
361};
362
363static struct qcom_icc_bcm * const gem_noc_bcms[] = {
364 &bcm_sh0,
365 &bcm_sh2,
366 &bcm_sh3,
367 &bcm_sh4,
368 &bcm_sh5,
369};
370
371static struct qcom_icc_node * const gem_noc_nodes[] = {
372 [MASTER_AMPSS_M0] = &acm_apps,
373 [MASTER_GPU_TCU] = &acm_gpu_tcu,
374 [MASTER_SYS_TCU] = &acm_sys_tcu,
375 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
376 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
377 [MASTER_GRAPHICS_3D] = &qnm_gpu,
378 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
379 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
380 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie,
381 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
382 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
383 [MASTER_ECC] = &qxm_ecc,
384 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
385 [SLAVE_ECC] = &qns_ecc,
386 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
387 [SLAVE_LLCC] = &qns_llcc,
388 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
389};
390
391static const struct qcom_icc_desc sm8150_gem_noc = {
392 .nodes = gem_noc_nodes,
393 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
394 .bcms = gem_noc_bcms,
395 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
396};
397
398static struct qcom_icc_bcm * const mc_virt_bcms[] = {
399 &bcm_acv,
400 &bcm_mc0,
401};
402
403static struct qcom_icc_node * const mc_virt_nodes[] = {
404 [MASTER_LLCC] = &llcc_mc,
405 [SLAVE_EBI_CH0] = &ebi,
406};
407
408static const struct qcom_icc_desc sm8150_mc_virt = {
409 .nodes = mc_virt_nodes,
410 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
411 .bcms = mc_virt_bcms,
412 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
413};
414
415static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
416 &bcm_mm0,
417 &bcm_mm1,
418 &bcm_mm2,
419 &bcm_mm3,
420};
421
422static struct qcom_icc_node * const mmss_noc_nodes[] = {
423 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
424 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
425 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
426 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
427 [MASTER_MDP_PORT0] = &qxm_mdp0,
428 [MASTER_MDP_PORT1] = &qxm_mdp1,
429 [MASTER_ROTATOR] = &qxm_rot,
430 [MASTER_VIDEO_P0] = &qxm_venus0,
431 [MASTER_VIDEO_P1] = &qxm_venus1,
432 [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
433 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
434 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
435 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
436};
437
438static const struct qcom_icc_desc sm8150_mmss_noc = {
439 .nodes = mmss_noc_nodes,
440 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
441 .bcms = mmss_noc_bcms,
442 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
443};
444
445static struct qcom_icc_bcm * const system_noc_bcms[] = {
446 &bcm_sn0,
447 &bcm_sn1,
448 &bcm_sn11,
449 &bcm_sn12,
450 &bcm_sn15,
451 &bcm_sn2,
452 &bcm_sn3,
453 &bcm_sn4,
454 &bcm_sn5,
455 &bcm_sn8,
456 &bcm_sn9,
457};
458
459static struct qcom_icc_node * const system_noc_nodes[] = {
460 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
461 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
462 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
463 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
464 [MASTER_PIMEM] = &qxm_pimem,
465 [MASTER_GIC] = &xm_gic,
466 [SLAVE_APPSS] = &qhs_apss,
467 [SNOC_CNOC_SLV] = &qns_cnoc,
468 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
469 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
470 [SLAVE_OCIMEM] = &qxs_imem,
471 [SLAVE_PIMEM] = &qxs_pimem,
472 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
473 [SLAVE_PCIE_0] = &xs_pcie_0,
474 [SLAVE_PCIE_1] = &xs_pcie_1,
475 [SLAVE_QDSS_STM] = &xs_qdss_stm,
476 [SLAVE_TCU] = &xs_sys_tcu_cfg,
477};
478
479static const struct qcom_icc_desc sm8150_system_noc = {
480 .nodes = system_noc_nodes,
481 .num_nodes = ARRAY_SIZE(system_noc_nodes),
482 .bcms = system_noc_bcms,
483 .num_bcms = ARRAY_SIZE(system_noc_bcms),
484};
485
486static const struct of_device_id qnoc_of_match[] = {
487 { .compatible = "qcom,sm8150-aggre1-noc",
488 .data = &sm8150_aggre1_noc},
489 { .compatible = "qcom,sm8150-aggre2-noc",
490 .data = &sm8150_aggre2_noc},
491 { .compatible = "qcom,sm8150-camnoc-virt",
492 .data = &sm8150_camnoc_virt},
493 { .compatible = "qcom,sm8150-compute-noc",
494 .data = &sm8150_compute_noc},
495 { .compatible = "qcom,sm8150-config-noc",
496 .data = &sm8150_config_noc},
497 { .compatible = "qcom,sm8150-dc-noc",
498 .data = &sm8150_dc_noc},
499 { .compatible = "qcom,sm8150-gem-noc",
500 .data = &sm8150_gem_noc},
501 { .compatible = "qcom,sm8150-mc-virt",
502 .data = &sm8150_mc_virt},
503 { .compatible = "qcom,sm8150-mmss-noc",
504 .data = &sm8150_mmss_noc},
505 { .compatible = "qcom,sm8150-system-noc",
506 .data = &sm8150_system_noc},
507 { }
508};
509MODULE_DEVICE_TABLE(of, qnoc_of_match);
510
511static struct platform_driver qnoc_driver = {
512 .probe = qcom_icc_rpmh_probe,
513 .remove = qcom_icc_rpmh_remove,
514 .driver = {
515 .name = "qnoc-sm8150",
516 .of_match_table = qnoc_of_match,
517 },
518};
519module_platform_driver(qnoc_driver);
520
521MODULE_DESCRIPTION("Qualcomm SM8150 NoC driver");
522MODULE_LICENSE("GPL v2");