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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/include/asm/barrier.h
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 * Copyright (C) 2013 Regents of the University of California
7 * Copyright (C) 2017 SiFive
8 */
9
10#ifndef _ASM_RISCV_BARRIER_H
11#define _ASM_RISCV_BARRIER_H
12
13#ifndef __ASSEMBLY__
14
15#define nop() __asm__ __volatile__ ("nop")
16#define __nops(n) ".rept " #n "\nnop\n.endr\n"
17#define nops(n) __asm__ __volatile__ (__nops(n))
18
19#define RISCV_FENCE(p, s) \
20 __asm__ __volatile__ ("fence " #p "," #s : : : "memory")
21
22/* These barriers need to enforce ordering on both devices or memory. */
23#define mb() RISCV_FENCE(iorw,iorw)
24#define rmb() RISCV_FENCE(ir,ir)
25#define wmb() RISCV_FENCE(ow,ow)
26
27/* These barriers do not need to enforce ordering on devices, just memory. */
28#define __smp_mb() RISCV_FENCE(rw,rw)
29#define __smp_rmb() RISCV_FENCE(r,r)
30#define __smp_wmb() RISCV_FENCE(w,w)
31
32#define __smp_store_release(p, v) \
33do { \
34 compiletime_assert_atomic_type(*p); \
35 RISCV_FENCE(rw,w); \
36 WRITE_ONCE(*p, v); \
37} while (0)
38
39#define __smp_load_acquire(p) \
40({ \
41 typeof(*p) ___p1 = READ_ONCE(*p); \
42 compiletime_assert_atomic_type(*p); \
43 RISCV_FENCE(r,rw); \
44 ___p1; \
45})
46
47/*
48 * This is a very specific barrier: it's currently only used in two places in
49 * the kernel, both in the scheduler. See include/linux/spinlock.h for the two
50 * orderings it guarantees, but the "critical section is RCsc" guarantee
51 * mandates a barrier on RISC-V. The sequence looks like:
52 *
53 * lr.aq lock
54 * sc lock <= LOCKED
55 * smp_mb__after_spinlock()
56 * // critical section
57 * lr lock
58 * sc.rl lock <= UNLOCKED
59 *
60 * The AQ/RL pair provides a RCpc critical section, but there's not really any
61 * way we can take advantage of that here because the ordering is only enforced
62 * on that one lock. Thus, we're just doing a full fence.
63 *
64 * Since we allow writeX to be called from preemptive regions we need at least
65 * an "o" in the predecessor set to ensure device writes are visible before the
66 * task is marked as available for scheduling on a new hart. While I don't see
67 * any concrete reason we need a full IO fence, it seems safer to just upgrade
68 * this in order to avoid any IO crossing a scheduling boundary. In both
69 * instances the scheduler pairs this with an mb(), so nothing is necessary on
70 * the new hart.
71 */
72#define smp_mb__after_spinlock() RISCV_FENCE(iorw,iorw)
73
74#include <asm-generic/barrier.h>
75
76#endif /* __ASSEMBLY__ */
77
78#endif /* _ASM_RISCV_BARRIER_H */