tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright (C) 2023 DH electronics GmbH
4 */
5
6#include "imx6ull-dhcor-som.dtsi"
7
8/ {
9 aliases {
10 /delete-property/ mmc0; /* Avoid double definitions */
11 /delete-property/ mmc1;
12 /delete-property/ spi2;
13 /delete-property/ spi3;
14 i2c0 = &i2c2;
15 i2c1 = &i2c1;
16 mmc2 = &usdhc2;
17 rtc0 = &rtc_i2c;
18 rtc1 = &snvs_rtc;
19 serial0 = &uart1;
20 serial1 = &uart6; /* DHCOM UART2, special hardware required */
21 serial2 = &uart3;
22 serial3 = &uart2; /* Use BT UART always as ttymxc3 */
23 serial4 = &uart4;
24 serial5 = &uart5;
25 spi0 = &ecspi1;
26 spi1 = &ecspi4; /* DHCOM SPI2, special hardware required */
27 };
28
29 chosen {
30 stdout-path = "serial0:115200n8";
31 };
32
33 reg_ext_3v3_ref: regulator-ext-3v3-ref {
34 compatible = "regulator-fixed";
35 regulator-always-on;
36 regulator-max-microvolt = <3300000>;
37 regulator-min-microvolt = <3300000>;
38 regulator-name = "VCC_3V3_REF";
39 };
40
41 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
42 compatible = "regulator-fixed";
43 regulator-max-microvolt = <5000000>;
44 regulator-min-microvolt = <5000000>;
45 regulator-name = "usb-otg1-vbus";
46 };
47
48 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
49 compatible = "regulator-fixed";
50 gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
51 regulator-max-microvolt = <5000000>;
52 regulator-min-microvolt = <5000000>;
53 regulator-name = "usb-otg2-vbus";
54 };
55
56 /* SoM with WiFi/BT: WiFi pin WL_REG_ON is connected to a DHCOM GPIO */
57 /omit-if-no-ref/ usdhc1_pwrseq: usdhc1-pwrseq {
58 compatible = "mmc-pwrseq-simple";
59 reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; /* GPIO H */
60 };
61};
62
63/* SoM with WiFi/BT: BT pin BT_REG_ON is connected to a DHCOM GPIO */
64&bluetooth {
65 shutdown-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */
66};
67
68&can1 {
69 pinctrl-0 = <&pinctrl_flexcan1>;
70 pinctrl-names = "default";
71 status = "okay";
72};
73
74/*
75 * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins.
76 * Only if this pins are used as CAN interface enable it on board layer.
77 */
78&can2 {
79 pinctrl-0 = <&pinctrl_flexcan2>;
80 pinctrl-names = "default";
81};
82
83/* DHCOM SPI1 */
84&ecspi1 {
85 cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
86 pinctrl-0 = <&pinctrl_ecspi1>;
87 pinctrl-names = "default";
88 status = "okay";
89};
90
91/*
92 * DHCOM SPI2
93 * Special hardware required that uses the pins of FEC2. Therefore this SPI
94 * interface can only be used if FEC2 is disabled.
95 */
96&ecspi4 {
97 cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
98 pinctrl-0 = <&pinctrl_ecspi4>;
99 pinctrl-names = "default";
100};
101
102/* DHCOM ETH1 */
103&fec1 {
104 phy-handle = <&mdio2_phy0>;
105 phy-mode = "rmii";
106 pinctrl-0 = <&pinctrl_fec1>;
107 pinctrl-names = "default";
108 status = "okay";
109};
110
111/* DHCOM ETH2 */
112&fec2 {
113 phy-handle = <&mdio2_phy1>;
114 phy-mode = "rmii";
115 pinctrl-0 = <&pinctrl_fec2>;
116 pinctrl-names = "default";
117 status = "okay";
118
119 mdio {
120 #address-cells = <1>;
121 #size-cells = <0>;
122
123 mdio2_phy0: ethernet-phy@0 {
124 compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */
125 "ethernet-phy-ieee802.3-c22";
126 reg = <0>;
127 clock-names = "rmii-ref";
128 clocks = <&clks IMX6UL_CLK_ENET_REF>;
129 interrupt-parent = <&gpio5>;
130 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
131 pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>;
132 pinctrl-names = "default";
133 reset-assert-us = <500>;
134 reset-deassert-us = <500>;
135 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
136 smsc,disable-energy-detect; /* Make plugin detection reliable */
137 };
138
139 mdio2_phy1: ethernet-phy@1 {
140 compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */
141 "ethernet-phy-ieee802.3-c22";
142 reg = <1>;
143 clock-names = "rmii-ref";
144 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
145 interrupt-parent = <&gpio5>;
146 interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
147 pinctrl-0 = <&pinctrl_fec2_phy &pinctrl_snvs_fec2_phy>;
148 pinctrl-names = "default";
149 reset-assert-us = <500>;
150 reset-deassert-us = <500>;
151 reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
152 smsc,disable-energy-detect; /* Make plugin detection reliable */
153 };
154 };
155};
156
157&gpio1 {
158 gpio-line-names =
159 "", "", "", "",
160 "", "", "", "",
161 "", "", "", "DHCOM-INT",
162 "", "", "", "",
163 "", "", "DHCOM-I", "",
164 "", "", "", "",
165 "", "", "", "",
166 "", "", "", "";
167 pinctrl-0 = <&pinctrl_spi1_switch
168 &pinctrl_dhcom_i &pinctrl_dhcom_int>;
169 pinctrl-names = "default";
170};
171
172&gpio4 {
173 gpio-line-names =
174 "", "", "", "",
175 "", "", "", "",
176 "", "", "", "",
177 "", "", "", "",
178 "", "DHCOM-L", "DHCOM-K", "DHCOM-M",
179 "DHCOM-J", "DHCOM-U", "DHCOM-T", "DHCOM-S",
180 "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O",
181 "DHCOM-N", "", "", "";
182 pinctrl-0 = <&pinctrl_dhcom_j &pinctrl_dhcom_k
183 &pinctrl_dhcom_l &pinctrl_dhcom_m
184 &pinctrl_dhcom_n &pinctrl_dhcom_o
185 &pinctrl_dhcom_p &pinctrl_dhcom_q
186 &pinctrl_dhcom_r &pinctrl_dhcom_s
187 &pinctrl_dhcom_t &pinctrl_dhcom_u>;
188 pinctrl-names = "default";
189};
190
191&gpio5 {
192 gpio-line-names =
193 "DHCOM-A", "DHCOM-B", "DHCOM-C", "DHCOM-D",
194 "DHCOM-E", "", "", "DHCOM-F",
195 "DHCOM-G", "DHCOM-H", "", "",
196 "", "", "", "",
197 "", "", "", "",
198 "", "", "", "",
199 "", "", "", "",
200 "", "", "", "";
201 pinctrl-0 = <&pinctrl_snvs_dhcom_a &pinctrl_snvs_dhcom_b
202 &pinctrl_snvs_dhcom_c &pinctrl_snvs_dhcom_d
203 &pinctrl_snvs_dhcom_e &pinctrl_snvs_dhcom_f
204 &pinctrl_snvs_dhcom_g &pinctrl_snvs_dhcom_h>;
205 pinctrl-names = "default";
206};
207
208/* DHCOM I2C2 */
209&i2c1 {
210 rtc_i2c: rtc@32 {
211 compatible = "microcrystal,rv8803";
212 reg = <0x32>;
213 };
214
215 /* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH1 */
216 eeprom@50 {
217 compatible = "atmel,24c02";
218 reg = <0x50>;
219 pagesize = <16>;
220 };
221
222 /* TI ADC101C027 */
223 adc@51 {
224 compatible = "ti,adc101c";
225 reg = <0x51>;
226 vref-supply = <®_ext_3v3_ref>;
227 };
228
229 /* TI ADC101C027 */
230 adc@52 {
231 compatible = "ti,adc101c";
232 reg = <0x52>;
233 vref-supply = <®_ext_3v3_ref>;
234 };
235
236 /* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH2 */
237 eeprom@53 {
238 compatible = "atmel,24c02";
239 reg = <0x53>;
240 pagesize = <16>;
241 };
242};
243
244/* DHCOM I2C1 */
245&i2c2 {
246 clock-frequency = <100000>;
247 pinctrl-0 = <&pinctrl_i2c2>;
248 pinctrl-1 = <&pinctrl_i2c2_gpio>;
249 pinctrl-names = "default", "gpio";
250 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
251 sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
252 status = "okay";
253};
254
255&lcdif {
256 pinctrl-0 = <&pinctrl_lcdif>;
257 pinctrl-names = "default";
258};
259
260&pwm1 {
261 pinctrl-0 = <&pinctrl_pwm1>;
262 pinctrl-names = "default";
263};
264
265&sai2 {
266 assigned-clock-rates = <320000000>;
267 assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>;
268 pinctrl-0 = <&pinctrl_sai2>;
269 pinctrl-names = "default";
270};
271
272&tsc {
273 measure-delay-time = <0xffff>;
274 pinctrl-0 = <&pinctrl_tsc>;
275 pinctrl-names = "default";
276 pre-charge-time = <0xfff>;
277 touchscreen-average-samples = <32>;
278 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
279};
280
281/* DHCOM UART1 */
282&uart1 {
283 pinctrl-0 = <&pinctrl_uart1>;
284 pinctrl-names = "default";
285 status = "okay";
286};
287
288/*
289 * DHCOM UART2 (alternative)
290 * Special hardware required that uses DHCOM GPIO pins for DHCOM UART2.
291 * Therefore this UART interface can only be used if DHCOM GPIOs J/K/L/M are
292 * removed from GPIO hog muxing.
293 */
294&uart6 {
295 pinctrl-0 = <&pinctrl_uart6>;
296 pinctrl-names = "default";
297 uart-has-rtscts;
298};
299
300&usbotg1 {
301 adp-disable;
302 disable-over-current;
303 dr_mode = "otg";
304 hnp-disable;
305 pinctrl-0 = <&pinctrl_usbotg1>;
306 pinctrl-names = "default";
307 srp-disable;
308 vbus-supply = <®_usb_otg1_vbus>;
309 status = "okay";
310};
311
312&usbotg2 {
313 disable-over-current; /* Overcurrent pin is used for TSC */
314 dr_mode = "host";
315 pinctrl-0 = <&pinctrl_usbotg2>;
316 pinctrl-names = "default";
317 tpl-support;
318 vbus-supply = <®_usb_otg2_vbus>;
319 status = "okay";
320};
321
322&usbphy1 {
323 fsl,tx-d-cal = <106>;
324};
325
326&usbphy2 {
327 fsl,tx-d-cal = <106>;
328};
329
330/* WiFi on LGA */
331&usdhc1 {
332 mmc-pwrseq = <&usdhc1_pwrseq>;
333};
334
335/* eMMC on module */
336&usdhc2 {
337 bus-width = <8>;
338 no-1-8-v;
339 non-removable;
340 pinctrl-0 = <&pinctrl_usdhc2>;
341 pinctrl-names = "default";
342 vmmc-supply = <&vcc_3v3>;
343 vqmmc-supply = <&vcc_3v3>;
344 status = "okay";
345};
346
347&iomuxc {
348 /* DHCOM GPIOs I..U + INT_HIGHEST_PRIORITY */
349 pinctrl_dhcom_i: dhcom-i-grp {
350 fsl,pins = <MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x400120b0>;
351 };
352
353 pinctrl_dhcom_j: dhcom-j-grp {
354 fsl,pins = <MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x400120b0>;
355 };
356
357 pinctrl_dhcom_k: dhcom-k-grp {
358 fsl,pins = <MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x400120b0>;
359 };
360
361 pinctrl_dhcom_l: dhcom-l-grp {
362 fsl,pins = <MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x400120b0>;
363 };
364
365 pinctrl_dhcom_m: dhcom-m-grp {
366 fsl,pins = <MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x400120b0>;
367 };
368
369 pinctrl_dhcom_n: dhcom-n-grp {
370 fsl,pins = <MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x400120b0>;
371 };
372
373 pinctrl_dhcom_o: dhcom-o-grp {
374 fsl,pins = <MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x400120b0>;
375 };
376
377 pinctrl_dhcom_p: dhcom-p-grp {
378 fsl,pins = <MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x400120b0>;
379 };
380
381 pinctrl_dhcom_q: dhcom-q-grp {
382 fsl,pins = <MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x400120b0>;
383 };
384
385 pinctrl_dhcom_r: dhcom-r-grp {
386 fsl,pins = <MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x400120b0>;
387 };
388
389 pinctrl_dhcom_s: dhcom-s-grp {
390 fsl,pins = <MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x400120b0>;
391 };
392
393 pinctrl_dhcom_t: dhcom-t-grp {
394 fsl,pins = <MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x400120b0>;
395 };
396
397 pinctrl_dhcom_u: dhcom-u-grp {
398 fsl,pins = <MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x400120b0>;
399 };
400
401 pinctrl_dhcom_int: dhcom-int-grp {
402 fsl,pins = <MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x400120b0>;
403 };
404
405 pinctrl_ecspi1: ecspi1-grp {
406 fsl,pins = <
407 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1
408 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1
409 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1
410 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x1b0b0 /* SS0 */
411 >;
412 };
413
414 pinctrl_ecspi4: ecspi4-grp {
415 fsl,pins = <
416 MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x100b1
417 MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x100b1
418 MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x100b1
419 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* SS0 */
420 >;
421 };
422
423 pinctrl_fec1: fec1-grp {
424 fsl,pins = <
425 /* FEC1 uses MDIO bus from FEC2 */
426 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
427 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
428 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
429 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
430 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
431 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
432 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
433 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010
434 >;
435 };
436
437 pinctrl_fec1_phy: fec1-phy-grp {
438 fsl,pins = <
439 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0xb0 /* SMSC PHY reset */
440 >;
441 };
442
443 pinctrl_fec2: fec2-grp {
444 fsl,pins = <
445 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
446 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
447 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
448 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
449 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
450 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
451 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
452 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
453 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
454 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
455 >;
456 };
457
458 pinctrl_fec2_phy: fec2-phy-grp {
459 fsl,pins = <
460 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0xb0 /* SMSC PHY reset */
461 >;
462 };
463
464 pinctrl_flexcan1: flexcan1-grp {
465 fsl,pins = <
466 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
467 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
468 >;
469 };
470
471 pinctrl_flexcan2: flexcan2-grp {
472 fsl,pins = <
473 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
474 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
475 >;
476 };
477
478 pinctrl_i2c2: i2c2-grp {
479 fsl,pins = <
480 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
481 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
482 >;
483 };
484
485 pinctrl_i2c2_gpio: i2c2-gpio-grp {
486 fsl,pins = <
487 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
488 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
489 >;
490 };
491
492 pinctrl_lcdif: lcdif-grp {
493 fsl,pins = <
494 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
495 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
496 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
497 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
498 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
499 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
500 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
501 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
502 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
503 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
504 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
505 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
506 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
507 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
508 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
509 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
510 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
511 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
512 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
513 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
514 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
515 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
516 >;
517 };
518
519 pinctrl_pwm1: pwm1-grp {
520 fsl,pins = <
521 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
522 >;
523 };
524
525 pinctrl_sai2: sai2-grp {
526 fsl,pins = <
527 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
528 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
529 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
530 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
531 >;
532 };
533
534 pinctrl_tsc: tsc-grp {
535 fsl,pins = <
536 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
537 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
538 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
539 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
540 >;
541 };
542
543 pinctrl_uart1: uart1-grp {
544 fsl,pins = <
545 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
546 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
547 >;
548 };
549
550 pinctrl_uart6: uart6-grp {
551 fsl,pins = <
552 MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
553 MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
554 MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1
555 MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1
556 >;
557 };
558
559 pinctrl_usbotg1: usbotg1-grp {
560 fsl,pins = <
561 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
562 >;
563 };
564
565 pinctrl_usbotg2: usbotg2-grp {
566 fsl,pins = <
567 MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x120b0
568 >;
569 };
570
571 pinctrl_usdhc2: usdhc2-grp {
572 fsl,pins = <
573 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
574 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
575 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
576 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
577 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
578 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
579 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
580 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
581 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
582 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
583 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 /* SD2 Reset */
584 >;
585 };
586};
587
588&iomuxc_snvs {
589 /* DHCOM GPIOs A..H */
590 pinctrl_snvs_dhcom_a: snvs-dhcom-a-grp {
591 fsl,pins = <MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x400120b0>;
592 };
593
594 pinctrl_snvs_dhcom_b: snvs-dhcom-b-grp {
595 fsl,pins = <MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x400120b0>;
596 };
597
598 pinctrl_snvs_dhcom_c: snvs-dhcom-c-grp {
599 fsl,pins = <MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x400120b0>;
600 };
601
602 pinctrl_snvs_dhcom_d: snvs-dhcom-d-grp {
603 fsl,pins = <MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x400120b0>;
604 };
605
606 pinctrl_snvs_dhcom_e: snvs-dhcom-e-grp {
607 fsl,pins = <MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x400120b0>;
608 };
609
610 pinctrl_snvs_dhcom_f: snvs-dhcom-f-grp {
611 fsl,pins = <MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x400120b0>;
612 };
613
614 pinctrl_snvs_dhcom_g: snvs-dhcom-g-grp {
615 fsl,pins = <MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x400120b0>;
616 };
617
618 pinctrl_snvs_dhcom_h: snvs-dhcom-h-grp {
619 fsl,pins = <MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400120b0>;
620 };
621
622 pinctrl_snvs_fec1_phy: snvs-fec1-phy-grp {
623 fsl,pins = <
624 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0xb1 /* SMSC PHY Int */
625 >;
626 };
627
628 pinctrl_snvs_fec2_phy: snvs-fec2-phy-grp {
629 fsl,pins = <
630 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0xb1 /* SMSC PHY Int */
631 >;
632 };
633};